Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/bus/mvebu-mbus.c

  1 /*
  2  * Address map functions for Marvell EBU SoCs (Kirkwood, Armada
  3  * 370/XP, Dove, Orion5x and MV78xx0)
  4  *
  5  * This file is licensed under the terms of the GNU General Public
  6  * License version 2.  This program is licensed "as is" without any
  7  * warranty of any kind, whether express or implied.
  8  *
  9  * The Marvell EBU SoCs have a configurable physical address space:
 10  * the physical address at which certain devices (PCIe, NOR, NAND,
 11  * etc.) sit can be configured. The configuration takes place through
 12  * two sets of registers:
 13  *
 14  * - One to configure the access of the CPU to the devices. Depending
 15  *   on the families, there are between 8 and 20 configurable windows,
 16  *   each can be use to create a physical memory window that maps to a
 17  *   specific device. Devices are identified by a tuple (target,
 18  *   attribute).
 19  *
 20  * - One to configure the access to the CPU to the SDRAM. There are
 21  *   either 2 (for Dove) or 4 (for other families) windows to map the
 22  *   SDRAM into the physical address space.
 23  *
 24  * This driver:
 25  *
 26  * - Reads out the SDRAM address decoding windows at initialization
 27  *   time, and fills the mvebu_mbus_dram_info structure with these
 28  *   informations. The exported function mv_mbus_dram_info() allow
 29  *   device drivers to get those informations related to the SDRAM
 30  *   address decoding windows. This is because devices also have their
 31  *   own windows (configured through registers that are part of each
 32  *   device register space), and therefore the drivers for Marvell
 33  *   devices have to configure those device -> SDRAM windows to ensure
 34  *   that DMA works properly.
 35  *
 36  * - Provides an API for platform code or device drivers to
 37  *   dynamically add or remove address decoding windows for the CPU ->
 38  *   device accesses. This API is mvebu_mbus_add_window_by_id(),
 39  *   mvebu_mbus_add_window_remap_by_id() and
 40  *   mvebu_mbus_del_window().
 41  *
 42  * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
 43  *   see the list of CPU -> SDRAM windows and their configuration
 44  *   (file 'sdram') and the list of CPU -> devices windows and their
 45  *   configuration (file 'devices').
 46  */
 47 
 48 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 49 
 50 #include <linux/kernel.h>
 51 #include <linux/module.h>
 52 #include <linux/init.h>
 53 #include <linux/mbus.h>
 54 #include <linux/io.h>
 55 #include <linux/ioport.h>
 56 #include <linux/of.h>
 57 #include <linux/of_address.h>
 58 #include <linux/debugfs.h>
 59 #include <linux/log2.h>
 60 #include <linux/syscore_ops.h>
 61 #include <linux/memblock.h>
 62 
 63 /*
 64  * DDR target is the same on all platforms.
 65  */
 66 #define TARGET_DDR              0
 67 
 68 /*
 69  * CPU Address Decode Windows registers
 70  */
 71 #define WIN_CTRL_OFF            0x0000
 72 #define   WIN_CTRL_ENABLE       BIT(0)
 73 #define   WIN_CTRL_SYNCBARRIER  BIT(1)
 74 #define   WIN_CTRL_TGT_MASK     0xf0
 75 #define   WIN_CTRL_TGT_SHIFT    4
 76 #define   WIN_CTRL_ATTR_MASK    0xff00
 77 #define   WIN_CTRL_ATTR_SHIFT   8
 78 #define   WIN_CTRL_SIZE_MASK    0xffff0000
 79 #define   WIN_CTRL_SIZE_SHIFT   16
 80 #define WIN_BASE_OFF            0x0004
 81 #define   WIN_BASE_LOW          0xffff0000
 82 #define   WIN_BASE_HIGH         0xf
 83 #define WIN_REMAP_LO_OFF        0x0008
 84 #define   WIN_REMAP_LOW         0xffff0000
 85 #define WIN_REMAP_HI_OFF        0x000c
 86 
 87 #define UNIT_SYNC_BARRIER_OFF   0x84
 88 #define   UNIT_SYNC_BARRIER_ALL 0xFFFF
 89 
 90 #define ATTR_HW_COHERENCY       (0x1 << 4)
 91 
 92 #define DDR_BASE_CS_OFF(n)      (0x0000 + ((n) << 3))
 93 #define  DDR_BASE_CS_HIGH_MASK  0xf
 94 #define  DDR_BASE_CS_LOW_MASK   0xff000000
 95 #define DDR_SIZE_CS_OFF(n)      (0x0004 + ((n) << 3))
 96 #define  DDR_SIZE_ENABLED       BIT(0)
 97 #define  DDR_SIZE_CS_MASK       0x1c
 98 #define  DDR_SIZE_CS_SHIFT      2
 99 #define  DDR_SIZE_MASK          0xff000000
100 
101 #define DOVE_DDR_BASE_CS_OFF(n) ((n) << 4)
102 
103 /* Relative to mbusbridge_base */
104 #define MBUS_BRIDGE_CTRL_OFF    0x0
105 #define  MBUS_BRIDGE_SIZE_MASK  0xffff0000
106 #define MBUS_BRIDGE_BASE_OFF    0x4
107 #define  MBUS_BRIDGE_BASE_MASK  0xffff0000
108 
109 /* Maximum number of windows, for all known platforms */
110 #define MBUS_WINS_MAX           20
111 
112 struct mvebu_mbus_state;
113 
114 struct mvebu_mbus_soc_data {
115         unsigned int num_wins;
116         bool has_mbus_bridge;
117         unsigned int (*win_cfg_offset)(const int win);
118         unsigned int (*win_remap_offset)(const int win);
119         void (*setup_cpu_target)(struct mvebu_mbus_state *s);
120         int (*save_cpu_target)(struct mvebu_mbus_state *s,
121                                u32 *store_addr);
122         int (*show_cpu_target)(struct mvebu_mbus_state *s,
123                                struct seq_file *seq, void *v);
124 };
125 
126 /*
127  * Used to store the state of one MBus window accross suspend/resume.
128  */
129 struct mvebu_mbus_win_data {
130         u32 ctrl;
131         u32 base;
132         u32 remap_lo;
133         u32 remap_hi;
134 };
135 
136 struct mvebu_mbus_state {
137         void __iomem *mbuswins_base;
138         void __iomem *sdramwins_base;
139         void __iomem *mbusbridge_base;
140         phys_addr_t sdramwins_phys_base;
141         struct dentry *debugfs_root;
142         struct dentry *debugfs_sdram;
143         struct dentry *debugfs_devs;
144         struct resource pcie_mem_aperture;
145         struct resource pcie_io_aperture;
146         const struct mvebu_mbus_soc_data *soc;
147         int hw_io_coherency;
148 
149         /* Used during suspend/resume */
150         u32 mbus_bridge_ctrl;
151         u32 mbus_bridge_base;
152         struct mvebu_mbus_win_data wins[MBUS_WINS_MAX];
153 };
154 
155 static struct mvebu_mbus_state mbus_state;
156 
157 static struct mbus_dram_target_info mvebu_mbus_dram_info;
158 const struct mbus_dram_target_info *mv_mbus_dram_info(void)
159 {
160         return &mvebu_mbus_dram_info;
161 }
162 EXPORT_SYMBOL_GPL(mv_mbus_dram_info);
163 
164 /* Checks whether the given window has remap capability */
165 static bool mvebu_mbus_window_is_remappable(struct mvebu_mbus_state *mbus,
166                                             const int win)
167 {
168         return mbus->soc->win_remap_offset(win) != MVEBU_MBUS_NO_REMAP;
169 }
170 
171 /*
172  * Functions to manipulate the address decoding windows
173  */
174 
175 static void mvebu_mbus_read_window(struct mvebu_mbus_state *mbus,
176                                    int win, int *enabled, u64 *base,
177                                    u32 *size, u8 *target, u8 *attr,
178                                    u64 *remap)
179 {
180         void __iomem *addr = mbus->mbuswins_base +
181                 mbus->soc->win_cfg_offset(win);
182         u32 basereg = readl(addr + WIN_BASE_OFF);
183         u32 ctrlreg = readl(addr + WIN_CTRL_OFF);
184 
185         if (!(ctrlreg & WIN_CTRL_ENABLE)) {
186                 *enabled = 0;
187                 return;
188         }
189 
190         *enabled = 1;
191         *base = ((u64)basereg & WIN_BASE_HIGH) << 32;
192         *base |= (basereg & WIN_BASE_LOW);
193         *size = (ctrlreg | ~WIN_CTRL_SIZE_MASK) + 1;
194 
195         if (target)
196                 *target = (ctrlreg & WIN_CTRL_TGT_MASK) >> WIN_CTRL_TGT_SHIFT;
197 
198         if (attr)
199                 *attr = (ctrlreg & WIN_CTRL_ATTR_MASK) >> WIN_CTRL_ATTR_SHIFT;
200 
201         if (remap) {
202                 if (mvebu_mbus_window_is_remappable(mbus, win)) {
203                         u32 remap_low, remap_hi;
204                         void __iomem *addr_rmp = mbus->mbuswins_base +
205                                 mbus->soc->win_remap_offset(win);
206                         remap_low = readl(addr_rmp + WIN_REMAP_LO_OFF);
207                         remap_hi  = readl(addr_rmp + WIN_REMAP_HI_OFF);
208                         *remap = ((u64)remap_hi << 32) | remap_low;
209                 } else
210                         *remap = 0;
211         }
212 }
213 
214 static void mvebu_mbus_disable_window(struct mvebu_mbus_state *mbus,
215                                       int win)
216 {
217         void __iomem *addr;
218 
219         addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);
220         writel(0, addr + WIN_BASE_OFF);
221         writel(0, addr + WIN_CTRL_OFF);
222 
223         if (mvebu_mbus_window_is_remappable(mbus, win)) {
224                 addr = mbus->mbuswins_base + mbus->soc->win_remap_offset(win);
225                 writel(0, addr + WIN_REMAP_LO_OFF);
226                 writel(0, addr + WIN_REMAP_HI_OFF);
227         }
228 }
229 
230 /* Checks whether the given window number is available */
231 
232 static int mvebu_mbus_window_is_free(struct mvebu_mbus_state *mbus,
233                                      const int win)
234 {
235         void __iomem *addr = mbus->mbuswins_base +
236                 mbus->soc->win_cfg_offset(win);
237         u32 ctrl = readl(addr + WIN_CTRL_OFF);
238 
239         return !(ctrl & WIN_CTRL_ENABLE);
240 }
241 
242 /*
243  * Checks whether the given (base, base+size) area doesn't overlap an
244  * existing region
245  */
246 static int mvebu_mbus_window_conflicts(struct mvebu_mbus_state *mbus,
247                                        phys_addr_t base, size_t size,
248                                        u8 target, u8 attr)
249 {
250         u64 end = (u64)base + size;
251         int win;
252 
253         for (win = 0; win < mbus->soc->num_wins; win++) {
254                 u64 wbase, wend;
255                 u32 wsize;
256                 u8 wtarget, wattr;
257                 int enabled;
258 
259                 mvebu_mbus_read_window(mbus, win,
260                                        &enabled, &wbase, &wsize,
261                                        &wtarget, &wattr, NULL);
262 
263                 if (!enabled)
264                         continue;
265 
266                 wend = wbase + wsize;
267 
268                 /*
269                  * Check if the current window overlaps with the
270                  * proposed physical range
271                  */
272                 if ((u64)base < wend && end > wbase)
273                         return 0;
274         }
275 
276         return 1;
277 }
278 
279 static int mvebu_mbus_find_window(struct mvebu_mbus_state *mbus,
280                                   phys_addr_t base, size_t size)
281 {
282         int win;
283 
284         for (win = 0; win < mbus->soc->num_wins; win++) {
285                 u64 wbase;
286                 u32 wsize;
287                 int enabled;
288 
289                 mvebu_mbus_read_window(mbus, win,
290                                        &enabled, &wbase, &wsize,
291                                        NULL, NULL, NULL);
292 
293                 if (!enabled)
294                         continue;
295 
296                 if (base == wbase && size == wsize)
297                         return win;
298         }
299 
300         return -ENODEV;
301 }
302 
303 static int mvebu_mbus_setup_window(struct mvebu_mbus_state *mbus,
304                                    int win, phys_addr_t base, size_t size,
305                                    phys_addr_t remap, u8 target,
306                                    u8 attr)
307 {
308         void __iomem *addr = mbus->mbuswins_base +
309                 mbus->soc->win_cfg_offset(win);
310         u32 ctrl, remap_addr;
311 
312         if (!is_power_of_2(size)) {
313                 WARN(true, "Invalid MBus window size: 0x%zx\n", size);
314                 return -EINVAL;
315         }
316 
317         if ((base & (phys_addr_t)(size - 1)) != 0) {
318                 WARN(true, "Invalid MBus base/size: %pa len 0x%zx\n", &base,
319                      size);
320                 return -EINVAL;
321         }
322 
323         ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |
324                 (attr << WIN_CTRL_ATTR_SHIFT)    |
325                 (target << WIN_CTRL_TGT_SHIFT)   |
326                 WIN_CTRL_SYNCBARRIER             |
327                 WIN_CTRL_ENABLE;
328 
329         writel(base & WIN_BASE_LOW, addr + WIN_BASE_OFF);
330         writel(ctrl, addr + WIN_CTRL_OFF);
331 
332         if (mvebu_mbus_window_is_remappable(mbus, win)) {
333                 void __iomem *addr_rmp = mbus->mbuswins_base +
334                         mbus->soc->win_remap_offset(win);
335 
336                 if (remap == MVEBU_MBUS_NO_REMAP)
337                         remap_addr = base;
338                 else
339                         remap_addr = remap;
340                 writel(remap_addr & WIN_REMAP_LOW, addr_rmp + WIN_REMAP_LO_OFF);
341                 writel(0, addr_rmp + WIN_REMAP_HI_OFF);
342         }
343 
344         return 0;
345 }
346 
347 static int mvebu_mbus_alloc_window(struct mvebu_mbus_state *mbus,
348                                    phys_addr_t base, size_t size,
349                                    phys_addr_t remap, u8 target,
350                                    u8 attr)
351 {
352         int win;
353 
354         if (remap == MVEBU_MBUS_NO_REMAP) {
355                 for (win = 0; win < mbus->soc->num_wins; win++) {
356                         if (mvebu_mbus_window_is_remappable(mbus, win))
357                                 continue;
358 
359                         if (mvebu_mbus_window_is_free(mbus, win))
360                                 return mvebu_mbus_setup_window(mbus, win, base,
361                                                                size, remap,
362                                                                target, attr);
363                 }
364         }
365 
366         for (win = 0; win < mbus->soc->num_wins; win++) {
367                 /* Skip window if need remap but is not supported */
368                 if ((remap != MVEBU_MBUS_NO_REMAP) &&
369                     !mvebu_mbus_window_is_remappable(mbus, win))
370                         continue;
371 
372                 if (mvebu_mbus_window_is_free(mbus, win))
373                         return mvebu_mbus_setup_window(mbus, win, base, size,
374                                                        remap, target, attr);
375         }
376 
377         return -ENOMEM;
378 }
379 
380 /*
381  * Debugfs debugging
382  */
383 
384 /* Common function used for Dove, Kirkwood, Armada 370/XP and Orion 5x */
385 static int mvebu_sdram_debug_show_orion(struct mvebu_mbus_state *mbus,
386                                         struct seq_file *seq, void *v)
387 {
388         int i;
389 
390         for (i = 0; i < 4; i++) {
391                 u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
392                 u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
393                 u64 base;
394                 u32 size;
395 
396                 if (!(sizereg & DDR_SIZE_ENABLED)) {
397                         seq_printf(seq, "[%d] disabled\n", i);
398                         continue;
399                 }
400 
401                 base = ((u64)basereg & DDR_BASE_CS_HIGH_MASK) << 32;
402                 base |= basereg & DDR_BASE_CS_LOW_MASK;
403                 size = (sizereg | ~DDR_SIZE_MASK);
404 
405                 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
406                            i, (unsigned long long)base,
407                            (unsigned long long)base + size + 1,
408                            (sizereg & DDR_SIZE_CS_MASK) >> DDR_SIZE_CS_SHIFT);
409         }
410 
411         return 0;
412 }
413 
414 /* Special function for Dove */
415 static int mvebu_sdram_debug_show_dove(struct mvebu_mbus_state *mbus,
416                                        struct seq_file *seq, void *v)
417 {
418         int i;
419 
420         for (i = 0; i < 2; i++) {
421                 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
422                 u64 base;
423                 u32 size;
424 
425                 if (!(map & 1)) {
426                         seq_printf(seq, "[%d] disabled\n", i);
427                         continue;
428                 }
429 
430                 base = map & 0xff800000;
431                 size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
432 
433                 seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",
434                            i, (unsigned long long)base,
435                            (unsigned long long)base + size, i);
436         }
437 
438         return 0;
439 }
440 
441 static int mvebu_sdram_debug_show(struct seq_file *seq, void *v)
442 {
443         struct mvebu_mbus_state *mbus = &mbus_state;
444         return mbus->soc->show_cpu_target(mbus, seq, v);
445 }
446 
447 static int mvebu_sdram_debug_open(struct inode *inode, struct file *file)
448 {
449         return single_open(file, mvebu_sdram_debug_show, inode->i_private);
450 }
451 
452 static const struct file_operations mvebu_sdram_debug_fops = {
453         .open = mvebu_sdram_debug_open,
454         .read = seq_read,
455         .llseek = seq_lseek,
456         .release = single_release,
457 };
458 
459 static int mvebu_devs_debug_show(struct seq_file *seq, void *v)
460 {
461         struct mvebu_mbus_state *mbus = &mbus_state;
462         int win;
463 
464         for (win = 0; win < mbus->soc->num_wins; win++) {
465                 u64 wbase, wremap;
466                 u32 wsize;
467                 u8 wtarget, wattr;
468                 int enabled;
469 
470                 mvebu_mbus_read_window(mbus, win,
471                                        &enabled, &wbase, &wsize,
472                                        &wtarget, &wattr, &wremap);
473 
474                 if (!enabled) {
475                         seq_printf(seq, "[%02d] disabled\n", win);
476                         continue;
477                 }
478 
479                 seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",
480                            win, (unsigned long long)wbase,
481                            (unsigned long long)(wbase + wsize), wtarget, wattr);
482 
483                 if (!is_power_of_2(wsize) ||
484                     ((wbase & (u64)(wsize - 1)) != 0))
485                         seq_puts(seq, " (Invalid base/size!!)");
486 
487                 if (mvebu_mbus_window_is_remappable(mbus, win)) {
488                         seq_printf(seq, " (remap %016llx)\n",
489                                    (unsigned long long)wremap);
490                 } else
491                         seq_printf(seq, "\n");
492         }
493 
494         return 0;
495 }
496 
497 static int mvebu_devs_debug_open(struct inode *inode, struct file *file)
498 {
499         return single_open(file, mvebu_devs_debug_show, inode->i_private);
500 }
501 
502 static const struct file_operations mvebu_devs_debug_fops = {
503         .open = mvebu_devs_debug_open,
504         .read = seq_read,
505         .llseek = seq_lseek,
506         .release = single_release,
507 };
508 
509 /*
510  * SoC-specific functions and definitions
511  */
512 
513 static unsigned int generic_mbus_win_cfg_offset(int win)
514 {
515         return win << 4;
516 }
517 
518 static unsigned int armada_370_xp_mbus_win_cfg_offset(int win)
519 {
520         /* The register layout is a bit annoying and the below code
521          * tries to cope with it.
522          * - At offset 0x0, there are the registers for the first 8
523          *   windows, with 4 registers of 32 bits per window (ctrl,
524          *   base, remap low, remap high)
525          * - Then at offset 0x80, there is a hole of 0x10 bytes for
526          *   the internal registers base address and internal units
527          *   sync barrier register.
528          * - Then at offset 0x90, there the registers for 12
529          *   windows, with only 2 registers of 32 bits per window
530          *   (ctrl, base).
531          */
532         if (win < 8)
533                 return win << 4;
534         else
535                 return 0x90 + ((win - 8) << 3);
536 }
537 
538 static unsigned int mv78xx0_mbus_win_cfg_offset(int win)
539 {
540         if (win < 8)
541                 return win << 4;
542         else
543                 return 0x900 + ((win - 8) << 4);
544 }
545 
546 static unsigned int generic_mbus_win_remap_2_offset(int win)
547 {
548         if (win < 2)
549                 return generic_mbus_win_cfg_offset(win);
550         else
551                 return MVEBU_MBUS_NO_REMAP;
552 }
553 
554 static unsigned int generic_mbus_win_remap_4_offset(int win)
555 {
556         if (win < 4)
557                 return generic_mbus_win_cfg_offset(win);
558         else
559                 return MVEBU_MBUS_NO_REMAP;
560 }
561 
562 static unsigned int generic_mbus_win_remap_8_offset(int win)
563 {
564         if (win < 8)
565                 return generic_mbus_win_cfg_offset(win);
566         else
567                 return MVEBU_MBUS_NO_REMAP;
568 }
569 
570 static unsigned int armada_xp_mbus_win_remap_offset(int win)
571 {
572         if (win < 8)
573                 return generic_mbus_win_cfg_offset(win);
574         else if (win == 13)
575                 return 0xF0 - WIN_REMAP_LO_OFF;
576         else
577                 return MVEBU_MBUS_NO_REMAP;
578 }
579 
580 /*
581  * Use the memblock information to find the MBus bridge hole in the
582  * physical address space.
583  */
584 static void __init
585 mvebu_mbus_find_bridge_hole(uint64_t *start, uint64_t *end)
586 {
587         struct memblock_region *r;
588         uint64_t s = 0;
589 
590         for_each_memblock(memory, r) {
591                 /*
592                  * This part of the memory is above 4 GB, so we don't
593                  * care for the MBus bridge hole.
594                  */
595                 if (r->base >= 0x100000000)
596                         continue;
597 
598                 /*
599                  * The MBus bridge hole is at the end of the RAM under
600                  * the 4 GB limit.
601                  */
602                 if (r->base + r->size > s)
603                         s = r->base + r->size;
604         }
605 
606         *start = s;
607         *end = 0x100000000;
608 }
609 
610 static void __init
611 mvebu_mbus_default_setup_cpu_target(struct mvebu_mbus_state *mbus)
612 {
613         int i;
614         int cs;
615         uint64_t mbus_bridge_base, mbus_bridge_end;
616 
617         mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
618 
619         mvebu_mbus_find_bridge_hole(&mbus_bridge_base, &mbus_bridge_end);
620 
621         for (i = 0, cs = 0; i < 4; i++) {
622                 u64 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
623                 u64 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
624                 u64 end;
625                 struct mbus_dram_window *w;
626 
627                 /* Ignore entries that are not enabled */
628                 if (!(size & DDR_SIZE_ENABLED))
629                         continue;
630 
631                 /*
632                  * Ignore entries whose base address is above 2^32,
633                  * since devices cannot DMA to such high addresses
634                  */
635                 if (base & DDR_BASE_CS_HIGH_MASK)
636                         continue;
637 
638                 base = base & DDR_BASE_CS_LOW_MASK;
639                 size = (size | ~DDR_SIZE_MASK) + 1;
640                 end = base + size;
641 
642                 /*
643                  * Adjust base/size of the current CS to make sure it
644                  * doesn't overlap with the MBus bridge hole. This is
645                  * particularly important for devices that do DMA from
646                  * DRAM to a SRAM mapped in a MBus window, such as the
647                  * CESA cryptographic engine.
648                  */
649 
650                 /*
651                  * The CS is fully enclosed inside the MBus bridge
652                  * area, so ignore it.
653                  */
654                 if (base >= mbus_bridge_base && end <= mbus_bridge_end)
655                         continue;
656 
657                 /*
658                  * Beginning of CS overlaps with end of MBus, raise CS
659                  * base address, and shrink its size.
660                  */
661                 if (base >= mbus_bridge_base && end > mbus_bridge_end) {
662                         size -= mbus_bridge_end - base;
663                         base = mbus_bridge_end;
664                 }
665 
666                 /*
667                  * End of CS overlaps with beginning of MBus, shrink
668                  * CS size.
669                  */
670                 if (base < mbus_bridge_base && end > mbus_bridge_base)
671                         size -= end - mbus_bridge_base;
672 
673                 w = &mvebu_mbus_dram_info.cs[cs++];
674                 w->cs_index = i;
675                 w->mbus_attr = 0xf & ~(1 << i);
676                 if (mbus->hw_io_coherency)
677                         w->mbus_attr |= ATTR_HW_COHERENCY;
678                 w->base = base;
679                 w->size = size;
680         }
681         mvebu_mbus_dram_info.num_cs = cs;
682 }
683 
684 static int
685 mvebu_mbus_default_save_cpu_target(struct mvebu_mbus_state *mbus,
686                                    u32 *store_addr)
687 {
688         int i;
689 
690         for (i = 0; i < 4; i++) {
691                 u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));
692                 u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));
693 
694                 writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i),
695                        store_addr++);
696                 writel(base, store_addr++);
697                 writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i),
698                        store_addr++);
699                 writel(size, store_addr++);
700         }
701 
702         /* We've written 16 words to the store address */
703         return 16;
704 }
705 
706 static void __init
707 mvebu_mbus_dove_setup_cpu_target(struct mvebu_mbus_state *mbus)
708 {
709         int i;
710         int cs;
711 
712         mvebu_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
713 
714         for (i = 0, cs = 0; i < 2; i++) {
715                 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
716 
717                 /*
718                  * Chip select enabled?
719                  */
720                 if (map & 1) {
721                         struct mbus_dram_window *w;
722 
723                         w = &mvebu_mbus_dram_info.cs[cs++];
724                         w->cs_index = i;
725                         w->mbus_attr = 0; /* CS address decoding done inside */
726                                           /* the DDR controller, no need to  */
727                                           /* provide attributes */
728                         w->base = map & 0xff800000;
729                         w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);
730                 }
731         }
732 
733         mvebu_mbus_dram_info.num_cs = cs;
734 }
735 
736 static int
737 mvebu_mbus_dove_save_cpu_target(struct mvebu_mbus_state *mbus,
738                                 u32 *store_addr)
739 {
740         int i;
741 
742         for (i = 0; i < 2; i++) {
743                 u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));
744 
745                 writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i),
746                        store_addr++);
747                 writel(map, store_addr++);
748         }
749 
750         /* We've written 4 words to the store address */
751         return 4;
752 }
753 
754 int mvebu_mbus_save_cpu_target(u32 *store_addr)
755 {
756         return mbus_state.soc->save_cpu_target(&mbus_state, store_addr);
757 }
758 
759 static const struct mvebu_mbus_soc_data armada_370_mbus_data = {
760         .num_wins            = 20,
761         .has_mbus_bridge     = true,
762         .win_cfg_offset      = armada_370_xp_mbus_win_cfg_offset,
763         .win_remap_offset    = generic_mbus_win_remap_8_offset,
764         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
765         .show_cpu_target     = mvebu_sdram_debug_show_orion,
766         .save_cpu_target     = mvebu_mbus_default_save_cpu_target,
767 };
768 
769 static const struct mvebu_mbus_soc_data armada_xp_mbus_data = {
770         .num_wins            = 20,
771         .has_mbus_bridge     = true,
772         .win_cfg_offset      = armada_370_xp_mbus_win_cfg_offset,
773         .win_remap_offset    = armada_xp_mbus_win_remap_offset,
774         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
775         .show_cpu_target     = mvebu_sdram_debug_show_orion,
776         .save_cpu_target     = mvebu_mbus_default_save_cpu_target,
777 };
778 
779 static const struct mvebu_mbus_soc_data kirkwood_mbus_data = {
780         .num_wins            = 8,
781         .win_cfg_offset      = generic_mbus_win_cfg_offset,
782         .save_cpu_target     = mvebu_mbus_default_save_cpu_target,
783         .win_remap_offset    = generic_mbus_win_remap_4_offset,
784         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
785         .show_cpu_target     = mvebu_sdram_debug_show_orion,
786 };
787 
788 static const struct mvebu_mbus_soc_data dove_mbus_data = {
789         .num_wins            = 8,
790         .win_cfg_offset      = generic_mbus_win_cfg_offset,
791         .save_cpu_target     = mvebu_mbus_dove_save_cpu_target,
792         .win_remap_offset    = generic_mbus_win_remap_4_offset,
793         .setup_cpu_target    = mvebu_mbus_dove_setup_cpu_target,
794         .show_cpu_target     = mvebu_sdram_debug_show_dove,
795 };
796 
797 /*
798  * Some variants of Orion5x have 4 remappable windows, some other have
799  * only two of them.
800  */
801 static const struct mvebu_mbus_soc_data orion5x_4win_mbus_data = {
802         .num_wins            = 8,
803         .win_cfg_offset      = generic_mbus_win_cfg_offset,
804         .save_cpu_target     = mvebu_mbus_default_save_cpu_target,
805         .win_remap_offset    = generic_mbus_win_remap_4_offset,
806         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
807         .show_cpu_target     = mvebu_sdram_debug_show_orion,
808 };
809 
810 static const struct mvebu_mbus_soc_data orion5x_2win_mbus_data = {
811         .num_wins            = 8,
812         .win_cfg_offset      = generic_mbus_win_cfg_offset,
813         .save_cpu_target     = mvebu_mbus_default_save_cpu_target,
814         .win_remap_offset    = generic_mbus_win_remap_2_offset,
815         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
816         .show_cpu_target     = mvebu_sdram_debug_show_orion,
817 };
818 
819 static const struct mvebu_mbus_soc_data mv78xx0_mbus_data = {
820         .num_wins            = 14,
821         .win_cfg_offset      = mv78xx0_mbus_win_cfg_offset,
822         .save_cpu_target     = mvebu_mbus_default_save_cpu_target,
823         .win_remap_offset    = generic_mbus_win_remap_8_offset,
824         .setup_cpu_target    = mvebu_mbus_default_setup_cpu_target,
825         .show_cpu_target     = mvebu_sdram_debug_show_orion,
826 };
827 
828 static const struct of_device_id of_mvebu_mbus_ids[] = {
829         { .compatible = "marvell,armada370-mbus",
830           .data = &armada_370_mbus_data, },
831         { .compatible = "marvell,armada375-mbus",
832           .data = &armada_xp_mbus_data, },
833         { .compatible = "marvell,armada380-mbus",
834           .data = &armada_xp_mbus_data, },
835         { .compatible = "marvell,armadaxp-mbus",
836           .data = &armada_xp_mbus_data, },
837         { .compatible = "marvell,kirkwood-mbus",
838           .data = &kirkwood_mbus_data, },
839         { .compatible = "marvell,dove-mbus",
840           .data = &dove_mbus_data, },
841         { .compatible = "marvell,orion5x-88f5281-mbus",
842           .data = &orion5x_4win_mbus_data, },
843         { .compatible = "marvell,orion5x-88f5182-mbus",
844           .data = &orion5x_2win_mbus_data, },
845         { .compatible = "marvell,orion5x-88f5181-mbus",
846           .data = &orion5x_2win_mbus_data, },
847         { .compatible = "marvell,orion5x-88f6183-mbus",
848           .data = &orion5x_4win_mbus_data, },
849         { .compatible = "marvell,mv78xx0-mbus",
850           .data = &mv78xx0_mbus_data, },
851         { },
852 };
853 
854 /*
855  * Public API of the driver
856  */
857 int mvebu_mbus_add_window_remap_by_id(unsigned int target,
858                                       unsigned int attribute,
859                                       phys_addr_t base, size_t size,
860                                       phys_addr_t remap)
861 {
862         struct mvebu_mbus_state *s = &mbus_state;
863 
864         if (!mvebu_mbus_window_conflicts(s, base, size, target, attribute)) {
865                 pr_err("cannot add window '%x:%x', conflicts with another window\n",
866                        target, attribute);
867                 return -EINVAL;
868         }
869 
870         return mvebu_mbus_alloc_window(s, base, size, remap, target, attribute);
871 }
872 
873 int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
874                                 phys_addr_t base, size_t size)
875 {
876         return mvebu_mbus_add_window_remap_by_id(target, attribute, base,
877                                                  size, MVEBU_MBUS_NO_REMAP);
878 }
879 
880 int mvebu_mbus_del_window(phys_addr_t base, size_t size)
881 {
882         int win;
883 
884         win = mvebu_mbus_find_window(&mbus_state, base, size);
885         if (win < 0)
886                 return win;
887 
888         mvebu_mbus_disable_window(&mbus_state, win);
889         return 0;
890 }
891 
892 void mvebu_mbus_get_pcie_mem_aperture(struct resource *res)
893 {
894         if (!res)
895                 return;
896         *res = mbus_state.pcie_mem_aperture;
897 }
898 
899 void mvebu_mbus_get_pcie_io_aperture(struct resource *res)
900 {
901         if (!res)
902                 return;
903         *res = mbus_state.pcie_io_aperture;
904 }
905 
906 static __init int mvebu_mbus_debugfs_init(void)
907 {
908         struct mvebu_mbus_state *s = &mbus_state;
909 
910         /*
911          * If no base has been initialized, doesn't make sense to
912          * register the debugfs entries. We may be on a multiplatform
913          * kernel that isn't running a Marvell EBU SoC.
914          */
915         if (!s->mbuswins_base)
916                 return 0;
917 
918         s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);
919         if (s->debugfs_root) {
920                 s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,
921                                                        s->debugfs_root, NULL,
922                                                        &mvebu_sdram_debug_fops);
923                 s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,
924                                                       s->debugfs_root, NULL,
925                                                       &mvebu_devs_debug_fops);
926         }
927 
928         return 0;
929 }
930 fs_initcall(mvebu_mbus_debugfs_init);
931 
932 static int mvebu_mbus_suspend(void)
933 {
934         struct mvebu_mbus_state *s = &mbus_state;
935         int win;
936 
937         if (!s->mbusbridge_base)
938                 return -ENODEV;
939 
940         for (win = 0; win < s->soc->num_wins; win++) {
941                 void __iomem *addr = s->mbuswins_base +
942                         s->soc->win_cfg_offset(win);
943                 void __iomem *addr_rmp;
944 
945                 s->wins[win].base = readl(addr + WIN_BASE_OFF);
946                 s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF);
947 
948                 if (!mvebu_mbus_window_is_remappable(s, win))
949                         continue;
950 
951                 addr_rmp = s->mbuswins_base +
952                         s->soc->win_remap_offset(win);
953 
954                 s->wins[win].remap_lo = readl(addr_rmp + WIN_REMAP_LO_OFF);
955                 s->wins[win].remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);
956         }
957 
958         s->mbus_bridge_ctrl = readl(s->mbusbridge_base +
959                                     MBUS_BRIDGE_CTRL_OFF);
960         s->mbus_bridge_base = readl(s->mbusbridge_base +
961                                     MBUS_BRIDGE_BASE_OFF);
962 
963         return 0;
964 }
965 
966 static void mvebu_mbus_resume(void)
967 {
968         struct mvebu_mbus_state *s = &mbus_state;
969         int win;
970 
971         writel(s->mbus_bridge_ctrl,
972                s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF);
973         writel(s->mbus_bridge_base,
974                s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF);
975 
976         for (win = 0; win < s->soc->num_wins; win++) {
977                 void __iomem *addr = s->mbuswins_base +
978                         s->soc->win_cfg_offset(win);
979                 void __iomem *addr_rmp;
980 
981                 writel(s->wins[win].base, addr + WIN_BASE_OFF);
982                 writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);
983 
984                 if (!mvebu_mbus_window_is_remappable(s, win))
985                         continue;
986 
987                 addr_rmp = s->mbuswins_base +
988                         s->soc->win_remap_offset(win);
989 
990                 writel(s->wins[win].remap_lo, addr_rmp + WIN_REMAP_LO_OFF);
991                 writel(s->wins[win].remap_hi, addr_rmp + WIN_REMAP_HI_OFF);
992         }
993 }
994 
995 struct syscore_ops mvebu_mbus_syscore_ops = {
996         .suspend        = mvebu_mbus_suspend,
997         .resume         = mvebu_mbus_resume,
998 };
999 
1000 static int __init mvebu_mbus_common_init(struct mvebu_mbus_state *mbus,
1001                                          phys_addr_t mbuswins_phys_base,
1002                                          size_t mbuswins_size,
1003                                          phys_addr_t sdramwins_phys_base,
1004                                          size_t sdramwins_size,
1005                                          phys_addr_t mbusbridge_phys_base,
1006                                          size_t mbusbridge_size,
1007                                          bool is_coherent)
1008 {
1009         int win;
1010 
1011         mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);
1012         if (!mbus->mbuswins_base)
1013                 return -ENOMEM;
1014 
1015         mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);
1016         if (!mbus->sdramwins_base) {
1017                 iounmap(mbus_state.mbuswins_base);
1018                 return -ENOMEM;
1019         }
1020 
1021         mbus->sdramwins_phys_base = sdramwins_phys_base;
1022 
1023         if (mbusbridge_phys_base) {
1024                 mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,
1025                                                 mbusbridge_size);
1026                 if (!mbus->mbusbridge_base) {
1027                         iounmap(mbus->sdramwins_base);
1028                         iounmap(mbus->mbuswins_base);
1029                         return -ENOMEM;
1030                 }
1031         } else
1032                 mbus->mbusbridge_base = NULL;
1033 
1034         for (win = 0; win < mbus->soc->num_wins; win++)
1035                 mvebu_mbus_disable_window(mbus, win);
1036 
1037         mbus->soc->setup_cpu_target(mbus);
1038 
1039         if (is_coherent)
1040                 writel(UNIT_SYNC_BARRIER_ALL,
1041                        mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF);
1042 
1043         register_syscore_ops(&mvebu_mbus_syscore_ops);
1044 
1045         return 0;
1046 }
1047 
1048 int __init mvebu_mbus_init(const char *soc, phys_addr_t mbuswins_phys_base,
1049                            size_t mbuswins_size,
1050                            phys_addr_t sdramwins_phys_base,
1051                            size_t sdramwins_size)
1052 {
1053         const struct of_device_id *of_id;
1054 
1055         for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++)
1056                 if (!strcmp(of_id->compatible, soc))
1057                         break;
1058 
1059         if (!of_id->compatible[0]) {
1060                 pr_err("could not find a matching SoC family\n");
1061                 return -ENODEV;
1062         }
1063 
1064         mbus_state.soc = of_id->data;
1065 
1066         return mvebu_mbus_common_init(&mbus_state,
1067                         mbuswins_phys_base,
1068                         mbuswins_size,
1069                         sdramwins_phys_base,
1070                         sdramwins_size, 0, 0, false);
1071 }
1072 
1073 #ifdef CONFIG_OF
1074 /*
1075  * The window IDs in the ranges DT property have the following format:
1076  *  - bits 28 to 31: MBus custom field
1077  *  - bits 24 to 27: window target ID
1078  *  - bits 16 to 23: window attribute ID
1079  *  - bits  0 to 15: unused
1080  */
1081 #define CUSTOM(id) (((id) & 0xF0000000) >> 24)
1082 #define TARGET(id) (((id) & 0x0F000000) >> 24)
1083 #define ATTR(id)   (((id) & 0x00FF0000) >> 16)
1084 
1085 static int __init mbus_dt_setup_win(struct mvebu_mbus_state *mbus,
1086                                     u32 base, u32 size,
1087                                     u8 target, u8 attr)
1088 {
1089         if (!mvebu_mbus_window_conflicts(mbus, base, size, target, attr)) {
1090                 pr_err("cannot add window '%04x:%04x', conflicts with another window\n",
1091                        target, attr);
1092                 return -EBUSY;
1093         }
1094 
1095         if (mvebu_mbus_alloc_window(mbus, base, size, MVEBU_MBUS_NO_REMAP,
1096                                     target, attr)) {
1097                 pr_err("cannot add window '%04x:%04x', too many windows\n",
1098                        target, attr);
1099                 return -ENOMEM;
1100         }
1101         return 0;
1102 }
1103 
1104 static int __init
1105 mbus_parse_ranges(struct device_node *node,
1106                   int *addr_cells, int *c_addr_cells, int *c_size_cells,
1107                   int *cell_count, const __be32 **ranges_start,
1108                   const __be32 **ranges_end)
1109 {
1110         const __be32 *prop;
1111         int ranges_len, tuple_len;
1112 
1113         /* Allow a node with no 'ranges' property */
1114         *ranges_start = of_get_property(node, "ranges", &ranges_len);
1115         if (*ranges_start == NULL) {
1116                 *addr_cells = *c_addr_cells = *c_size_cells = *cell_count = 0;
1117                 *ranges_start = *ranges_end = NULL;
1118                 return 0;
1119         }
1120         *ranges_end = *ranges_start + ranges_len / sizeof(__be32);
1121 
1122         *addr_cells = of_n_addr_cells(node);
1123 
1124         prop = of_get_property(node, "#address-cells", NULL);
1125         *c_addr_cells = be32_to_cpup(prop);
1126 
1127         prop = of_get_property(node, "#size-cells", NULL);
1128         *c_size_cells = be32_to_cpup(prop);
1129 
1130         *cell_count = *addr_cells + *c_addr_cells + *c_size_cells;
1131         tuple_len = (*cell_count) * sizeof(__be32);
1132 
1133         if (ranges_len % tuple_len) {
1134                 pr_warn("malformed ranges entry '%s'\n", node->name);
1135                 return -EINVAL;
1136         }
1137         return 0;
1138 }
1139 
1140 static int __init mbus_dt_setup(struct mvebu_mbus_state *mbus,
1141                                 struct device_node *np)
1142 {
1143         int addr_cells, c_addr_cells, c_size_cells;
1144         int i, ret, cell_count;
1145         const __be32 *r, *ranges_start, *ranges_end;
1146 
1147         ret = mbus_parse_ranges(np, &addr_cells, &c_addr_cells,
1148                                 &c_size_cells, &cell_count,
1149                                 &ranges_start, &ranges_end);
1150         if (ret < 0)
1151                 return ret;
1152 
1153         for (i = 0, r = ranges_start; r < ranges_end; r += cell_count, i++) {
1154                 u32 windowid, base, size;
1155                 u8 target, attr;
1156 
1157                 /*
1158                  * An entry with a non-zero custom field do not
1159                  * correspond to a static window, so skip it.
1160                  */
1161                 windowid = of_read_number(r, 1);
1162                 if (CUSTOM(windowid))
1163                         continue;
1164 
1165                 target = TARGET(windowid);
1166                 attr = ATTR(windowid);
1167 
1168                 base = of_read_number(r + c_addr_cells, addr_cells);
1169                 size = of_read_number(r + c_addr_cells + addr_cells,
1170                                       c_size_cells);
1171                 ret = mbus_dt_setup_win(mbus, base, size, target, attr);
1172                 if (ret < 0)
1173                         return ret;
1174         }
1175         return 0;
1176 }
1177 
1178 static void __init mvebu_mbus_get_pcie_resources(struct device_node *np,
1179                                                  struct resource *mem,
1180                                                  struct resource *io)
1181 {
1182         u32 reg[2];
1183         int ret;
1184 
1185         /*
1186          * These are optional, so we make sure that resource_size(x) will
1187          * return 0.
1188          */
1189         memset(mem, 0, sizeof(struct resource));
1190         mem->end = -1;
1191         memset(io, 0, sizeof(struct resource));
1192         io->end = -1;
1193 
1194         ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));
1195         if (!ret) {
1196                 mem->start = reg[0];
1197                 mem->end = mem->start + reg[1] - 1;
1198                 mem->flags = IORESOURCE_MEM;
1199         }
1200 
1201         ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));
1202         if (!ret) {
1203                 io->start = reg[0];
1204                 io->end = io->start + reg[1] - 1;
1205                 io->flags = IORESOURCE_IO;
1206         }
1207 }
1208 
1209 int __init mvebu_mbus_dt_init(bool is_coherent)
1210 {
1211         struct resource mbuswins_res, sdramwins_res, mbusbridge_res;
1212         struct device_node *np, *controller;
1213         const struct of_device_id *of_id;
1214         const __be32 *prop;
1215         int ret;
1216 
1217         np = of_find_matching_node_and_match(NULL, of_mvebu_mbus_ids, &of_id);
1218         if (!np) {
1219                 pr_err("could not find a matching SoC family\n");
1220                 return -ENODEV;
1221         }
1222 
1223         mbus_state.soc = of_id->data;
1224 
1225         prop = of_get_property(np, "controller", NULL);
1226         if (!prop) {
1227                 pr_err("required 'controller' property missing\n");
1228                 return -EINVAL;
1229         }
1230 
1231         controller = of_find_node_by_phandle(be32_to_cpup(prop));
1232         if (!controller) {
1233                 pr_err("could not find an 'mbus-controller' node\n");
1234                 return -ENODEV;
1235         }
1236 
1237         if (of_address_to_resource(controller, 0, &mbuswins_res)) {
1238                 pr_err("cannot get MBUS register address\n");
1239                 return -EINVAL;
1240         }
1241 
1242         if (of_address_to_resource(controller, 1, &sdramwins_res)) {
1243                 pr_err("cannot get SDRAM register address\n");
1244                 return -EINVAL;
1245         }
1246 
1247         /*
1248          * Set the resource to 0 so that it can be left unmapped by
1249          * mvebu_mbus_common_init() if the DT doesn't carry the
1250          * necessary information. This is needed to preserve backward
1251          * compatibility.
1252          */
1253         memset(&mbusbridge_res, 0, sizeof(mbusbridge_res));
1254 
1255         if (mbus_state.soc->has_mbus_bridge) {
1256                 if (of_address_to_resource(controller, 2, &mbusbridge_res))
1257                         pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n");
1258         }
1259 
1260         mbus_state.hw_io_coherency = is_coherent;
1261 
1262         /* Get optional pcie-{mem,io}-aperture properties */
1263         mvebu_mbus_get_pcie_resources(np, &mbus_state.pcie_mem_aperture,
1264                                           &mbus_state.pcie_io_aperture);
1265 
1266         ret = mvebu_mbus_common_init(&mbus_state,
1267                                      mbuswins_res.start,
1268                                      resource_size(&mbuswins_res),
1269                                      sdramwins_res.start,
1270                                      resource_size(&sdramwins_res),
1271                                      mbusbridge_res.start,
1272                                      resource_size(&mbusbridge_res),
1273                                      is_coherent);
1274         if (ret)
1275                 return ret;
1276 
1277         /* Setup statically declared windows in the DT */
1278         return mbus_dt_setup(&mbus_state, np);
1279 }
1280 #endif
1281 

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