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Linux/drivers/ata/sata_vsc.c

  1 /*
  2  *  sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
  3  *
  4  *  Maintained by:  Jeremy Higdon @ SGI
  5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  6  *                  on emails.
  7  *
  8  *  Copyright 2004 SGI
  9  *
 10  *  Bits from Jeff Garzik, Copyright RedHat, Inc.
 11  *
 12  *
 13  *  This program is free software; you can redistribute it and/or modify
 14  *  it under the terms of the GNU General Public License as published by
 15  *  the Free Software Foundation; either version 2, or (at your option)
 16  *  any later version.
 17  *
 18  *  This program is distributed in the hope that it will be useful,
 19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 21  *  GNU General Public License for more details.
 22  *
 23  *  You should have received a copy of the GNU General Public License
 24  *  along with this program; see the file COPYING.  If not, write to
 25  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 26  *
 27  *
 28  *  libata documentation is available via 'make {ps|pdf}docs',
 29  *  as Documentation/DocBook/libata.*
 30  *
 31  *  Vitesse hardware documentation presumably available under NDA.
 32  *  Intel 31244 (same hardware interface) documentation presumably
 33  *  available from http://developer.intel.com/
 34  *
 35  */
 36 
 37 #include <linux/kernel.h>
 38 #include <linux/module.h>
 39 #include <linux/pci.h>
 40 #include <linux/blkdev.h>
 41 #include <linux/delay.h>
 42 #include <linux/interrupt.h>
 43 #include <linux/dma-mapping.h>
 44 #include <linux/device.h>
 45 #include <scsi/scsi_host.h>
 46 #include <linux/libata.h>
 47 
 48 #define DRV_NAME        "sata_vsc"
 49 #define DRV_VERSION     "2.3"
 50 
 51 enum {
 52         VSC_MMIO_BAR                    = 0,
 53 
 54         /* Interrupt register offsets (from chip base address) */
 55         VSC_SATA_INT_STAT_OFFSET        = 0x00,
 56         VSC_SATA_INT_MASK_OFFSET        = 0x04,
 57 
 58         /* Taskfile registers offsets */
 59         VSC_SATA_TF_CMD_OFFSET          = 0x00,
 60         VSC_SATA_TF_DATA_OFFSET         = 0x00,
 61         VSC_SATA_TF_ERROR_OFFSET        = 0x04,
 62         VSC_SATA_TF_FEATURE_OFFSET      = 0x06,
 63         VSC_SATA_TF_NSECT_OFFSET        = 0x08,
 64         VSC_SATA_TF_LBAL_OFFSET         = 0x0c,
 65         VSC_SATA_TF_LBAM_OFFSET         = 0x10,
 66         VSC_SATA_TF_LBAH_OFFSET         = 0x14,
 67         VSC_SATA_TF_DEVICE_OFFSET       = 0x18,
 68         VSC_SATA_TF_STATUS_OFFSET       = 0x1c,
 69         VSC_SATA_TF_COMMAND_OFFSET      = 0x1d,
 70         VSC_SATA_TF_ALTSTATUS_OFFSET    = 0x28,
 71         VSC_SATA_TF_CTL_OFFSET          = 0x29,
 72 
 73         /* DMA base */
 74         VSC_SATA_UP_DESCRIPTOR_OFFSET   = 0x64,
 75         VSC_SATA_UP_DATA_BUFFER_OFFSET  = 0x6C,
 76         VSC_SATA_DMA_CMD_OFFSET         = 0x70,
 77 
 78         /* SCRs base */
 79         VSC_SATA_SCR_STATUS_OFFSET      = 0x100,
 80         VSC_SATA_SCR_ERROR_OFFSET       = 0x104,
 81         VSC_SATA_SCR_CONTROL_OFFSET     = 0x108,
 82 
 83         /* Port stride */
 84         VSC_SATA_PORT_OFFSET            = 0x200,
 85 
 86         /* Error interrupt status bit offsets */
 87         VSC_SATA_INT_ERROR_CRC          = 0x40,
 88         VSC_SATA_INT_ERROR_T            = 0x20,
 89         VSC_SATA_INT_ERROR_P            = 0x10,
 90         VSC_SATA_INT_ERROR_R            = 0x8,
 91         VSC_SATA_INT_ERROR_E            = 0x4,
 92         VSC_SATA_INT_ERROR_M            = 0x2,
 93         VSC_SATA_INT_PHY_CHANGE         = 0x1,
 94         VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC  | VSC_SATA_INT_ERROR_T | \
 95                               VSC_SATA_INT_ERROR_P    | VSC_SATA_INT_ERROR_R | \
 96                               VSC_SATA_INT_ERROR_E    | VSC_SATA_INT_ERROR_M | \
 97                               VSC_SATA_INT_PHY_CHANGE),
 98 };
 99 
100 static int vsc_sata_scr_read(struct ata_link *link,
101                              unsigned int sc_reg, u32 *val)
102 {
103         if (sc_reg > SCR_CONTROL)
104                 return -EINVAL;
105         *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
106         return 0;
107 }
108 
109 
110 static int vsc_sata_scr_write(struct ata_link *link,
111                               unsigned int sc_reg, u32 val)
112 {
113         if (sc_reg > SCR_CONTROL)
114                 return -EINVAL;
115         writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
116         return 0;
117 }
118 
119 
120 static void vsc_freeze(struct ata_port *ap)
121 {
122         void __iomem *mask_addr;
123 
124         mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
125                 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
126 
127         writeb(0, mask_addr);
128 }
129 
130 
131 static void vsc_thaw(struct ata_port *ap)
132 {
133         void __iomem *mask_addr;
134 
135         mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
136                 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
137 
138         writeb(0xff, mask_addr);
139 }
140 
141 
142 static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
143 {
144         void __iomem *mask_addr;
145         u8 mask;
146 
147         mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
148                 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
149         mask = readb(mask_addr);
150         if (ctl & ATA_NIEN)
151                 mask |= 0x80;
152         else
153                 mask &= 0x7F;
154         writeb(mask, mask_addr);
155 }
156 
157 
158 static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
159 {
160         struct ata_ioports *ioaddr = &ap->ioaddr;
161         unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
162 
163         /*
164          * The only thing the ctl register is used for is SRST.
165          * That is not enabled or disabled via tf_load.
166          * However, if ATA_NIEN is changed, then we need to change
167          * the interrupt register.
168          */
169         if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
170                 ap->last_ctl = tf->ctl;
171                 vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
172         }
173         if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
174                 writew(tf->feature | (((u16)tf->hob_feature) << 8),
175                        ioaddr->feature_addr);
176                 writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
177                        ioaddr->nsect_addr);
178                 writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
179                        ioaddr->lbal_addr);
180                 writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
181                        ioaddr->lbam_addr);
182                 writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
183                        ioaddr->lbah_addr);
184         } else if (is_addr) {
185                 writew(tf->feature, ioaddr->feature_addr);
186                 writew(tf->nsect, ioaddr->nsect_addr);
187                 writew(tf->lbal, ioaddr->lbal_addr);
188                 writew(tf->lbam, ioaddr->lbam_addr);
189                 writew(tf->lbah, ioaddr->lbah_addr);
190         }
191 
192         if (tf->flags & ATA_TFLAG_DEVICE)
193                 writeb(tf->device, ioaddr->device_addr);
194 
195         ata_wait_idle(ap);
196 }
197 
198 
199 static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
200 {
201         struct ata_ioports *ioaddr = &ap->ioaddr;
202         u16 nsect, lbal, lbam, lbah, feature;
203 
204         tf->command = ata_sff_check_status(ap);
205         tf->device = readw(ioaddr->device_addr);
206         feature = readw(ioaddr->error_addr);
207         nsect = readw(ioaddr->nsect_addr);
208         lbal = readw(ioaddr->lbal_addr);
209         lbam = readw(ioaddr->lbam_addr);
210         lbah = readw(ioaddr->lbah_addr);
211 
212         tf->feature = feature;
213         tf->nsect = nsect;
214         tf->lbal = lbal;
215         tf->lbam = lbam;
216         tf->lbah = lbah;
217 
218         if (tf->flags & ATA_TFLAG_LBA48) {
219                 tf->hob_feature = feature >> 8;
220                 tf->hob_nsect = nsect >> 8;
221                 tf->hob_lbal = lbal >> 8;
222                 tf->hob_lbam = lbam >> 8;
223                 tf->hob_lbah = lbah >> 8;
224         }
225 }
226 
227 static inline void vsc_error_intr(u8 port_status, struct ata_port *ap)
228 {
229         if (port_status & (VSC_SATA_INT_PHY_CHANGE | VSC_SATA_INT_ERROR_M))
230                 ata_port_freeze(ap);
231         else
232                 ata_port_abort(ap);
233 }
234 
235 static void vsc_port_intr(u8 port_status, struct ata_port *ap)
236 {
237         struct ata_queued_cmd *qc;
238         int handled = 0;
239 
240         if (unlikely(port_status & VSC_SATA_INT_ERROR)) {
241                 vsc_error_intr(port_status, ap);
242                 return;
243         }
244 
245         qc = ata_qc_from_tag(ap, ap->link.active_tag);
246         if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING)))
247                 handled = ata_bmdma_port_intr(ap, qc);
248 
249         /* We received an interrupt during a polled command,
250          * or some other spurious condition.  Interrupt reporting
251          * with this hardware is fairly reliable so it is safe to
252          * simply clear the interrupt
253          */
254         if (unlikely(!handled))
255                 ap->ops->sff_check_status(ap);
256 }
257 
258 /*
259  * vsc_sata_interrupt
260  *
261  * Read the interrupt register and process for the devices that have
262  * them pending.
263  */
264 static irqreturn_t vsc_sata_interrupt(int irq, void *dev_instance)
265 {
266         struct ata_host *host = dev_instance;
267         unsigned int i;
268         unsigned int handled = 0;
269         u32 status;
270 
271         status = readl(host->iomap[VSC_MMIO_BAR] + VSC_SATA_INT_STAT_OFFSET);
272 
273         if (unlikely(status == 0xffffffff || status == 0)) {
274                 if (status)
275                         dev_err(host->dev,
276                                 ": IRQ status == 0xffffffff, PCI fault or device removal?\n");
277                 goto out;
278         }
279 
280         spin_lock(&host->lock);
281 
282         for (i = 0; i < host->n_ports; i++) {
283                 u8 port_status = (status >> (8 * i)) & 0xff;
284                 if (port_status) {
285                         vsc_port_intr(port_status, host->ports[i]);
286                         handled++;
287                 }
288         }
289 
290         spin_unlock(&host->lock);
291 out:
292         return IRQ_RETVAL(handled);
293 }
294 
295 
296 static struct scsi_host_template vsc_sata_sht = {
297         ATA_BMDMA_SHT(DRV_NAME),
298 };
299 
300 
301 static struct ata_port_operations vsc_sata_ops = {
302         .inherits               = &ata_bmdma_port_ops,
303         /* The IRQ handling is not quite standard SFF behaviour so we
304            cannot use the default lost interrupt handler */
305         .lost_interrupt         = ATA_OP_NULL,
306         .sff_tf_load            = vsc_sata_tf_load,
307         .sff_tf_read            = vsc_sata_tf_read,
308         .freeze                 = vsc_freeze,
309         .thaw                   = vsc_thaw,
310         .scr_read               = vsc_sata_scr_read,
311         .scr_write              = vsc_sata_scr_write,
312 };
313 
314 static void vsc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
315 {
316         port->cmd_addr          = base + VSC_SATA_TF_CMD_OFFSET;
317         port->data_addr         = base + VSC_SATA_TF_DATA_OFFSET;
318         port->error_addr        = base + VSC_SATA_TF_ERROR_OFFSET;
319         port->feature_addr      = base + VSC_SATA_TF_FEATURE_OFFSET;
320         port->nsect_addr        = base + VSC_SATA_TF_NSECT_OFFSET;
321         port->lbal_addr         = base + VSC_SATA_TF_LBAL_OFFSET;
322         port->lbam_addr         = base + VSC_SATA_TF_LBAM_OFFSET;
323         port->lbah_addr         = base + VSC_SATA_TF_LBAH_OFFSET;
324         port->device_addr       = base + VSC_SATA_TF_DEVICE_OFFSET;
325         port->status_addr       = base + VSC_SATA_TF_STATUS_OFFSET;
326         port->command_addr      = base + VSC_SATA_TF_COMMAND_OFFSET;
327         port->altstatus_addr    = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
328         port->ctl_addr          = base + VSC_SATA_TF_CTL_OFFSET;
329         port->bmdma_addr        = base + VSC_SATA_DMA_CMD_OFFSET;
330         port->scr_addr          = base + VSC_SATA_SCR_STATUS_OFFSET;
331         writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
332         writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
333 }
334 
335 
336 static int vsc_sata_init_one(struct pci_dev *pdev,
337                              const struct pci_device_id *ent)
338 {
339         static const struct ata_port_info pi = {
340                 .flags          = ATA_FLAG_SATA,
341                 .pio_mask       = ATA_PIO4,
342                 .mwdma_mask     = ATA_MWDMA2,
343                 .udma_mask      = ATA_UDMA6,
344                 .port_ops       = &vsc_sata_ops,
345         };
346         const struct ata_port_info *ppi[] = { &pi, NULL };
347         struct ata_host *host;
348         void __iomem *mmio_base;
349         int i, rc;
350         u8 cls;
351 
352         ata_print_version_once(&pdev->dev, DRV_VERSION);
353 
354         /* allocate host */
355         host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
356         if (!host)
357                 return -ENOMEM;
358 
359         rc = pcim_enable_device(pdev);
360         if (rc)
361                 return rc;
362 
363         /* check if we have needed resource mapped */
364         if (pci_resource_len(pdev, 0) == 0)
365                 return -ENODEV;
366 
367         /* map IO regions and initialize host accordingly */
368         rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
369         if (rc == -EBUSY)
370                 pcim_pin_device(pdev);
371         if (rc)
372                 return rc;
373         host->iomap = pcim_iomap_table(pdev);
374 
375         mmio_base = host->iomap[VSC_MMIO_BAR];
376 
377         for (i = 0; i < host->n_ports; i++) {
378                 struct ata_port *ap = host->ports[i];
379                 unsigned int offset = (i + 1) * VSC_SATA_PORT_OFFSET;
380 
381                 vsc_sata_setup_port(&ap->ioaddr, mmio_base + offset);
382 
383                 ata_port_pbar_desc(ap, VSC_MMIO_BAR, -1, "mmio");
384                 ata_port_pbar_desc(ap, VSC_MMIO_BAR, offset, "port");
385         }
386 
387         /*
388          * Use 32 bit DMA mask, because 64 bit address support is poor.
389          */
390         rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
391         if (rc)
392                 return rc;
393         rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
394         if (rc)
395                 return rc;
396 
397         /*
398          * Due to a bug in the chip, the default cache line size can't be
399          * used (unless the default is non-zero).
400          */
401         pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
402         if (cls == 0x00)
403                 pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
404 
405         if (pci_enable_msi(pdev) == 0)
406                 pci_intx(pdev, 0);
407 
408         /*
409          * Config offset 0x98 is "Extended Control and Status Register 0"
410          * Default value is (1 << 28).  All bits except bit 28 are reserved in
411          * DPA mode.  If bit 28 is set, LED 0 reflects all ports' activity.
412          * If bit 28 is clear, each port has its own LED.
413          */
414         pci_write_config_dword(pdev, 0x98, 0);
415 
416         pci_set_master(pdev);
417         return ata_host_activate(host, pdev->irq, vsc_sata_interrupt,
418                                  IRQF_SHARED, &vsc_sata_sht);
419 }
420 
421 static const struct pci_device_id vsc_sata_pci_tbl[] = {
422         { PCI_VENDOR_ID_VITESSE, 0x7174,
423           PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
424         { PCI_VENDOR_ID_INTEL, 0x3200,
425           PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
426 
427         { }     /* terminate list */
428 };
429 
430 static struct pci_driver vsc_sata_pci_driver = {
431         .name                   = DRV_NAME,
432         .id_table               = vsc_sata_pci_tbl,
433         .probe                  = vsc_sata_init_one,
434         .remove                 = ata_pci_remove_one,
435 };
436 
437 module_pci_driver(vsc_sata_pci_driver);
438 
439 MODULE_AUTHOR("Jeremy Higdon");
440 MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
441 MODULE_LICENSE("GPL");
442 MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
443 MODULE_VERSION(DRV_VERSION);
444 

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