Version:  2.0.40 2.2.26 2.4.37 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18

Linux/drivers/ata/sata_sil24.c

  1 /*
  2  * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
  3  *
  4  * Copyright 2005  Tejun Heo
  5  *
  6  * Based on preview driver from Silicon Image.
  7  *
  8  * This program is free software; you can redistribute it and/or modify it
  9  * under the terms of the GNU General Public License as published by the
 10  * Free Software Foundation; either version 2, or (at your option) any
 11  * later version.
 12  *
 13  * This program is distributed in the hope that it will be useful, but
 14  * WITHOUT ANY WARRANTY; without even the implied warranty of
 15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
 16  * General Public License for more details.
 17  *
 18  */
 19 
 20 #include <linux/kernel.h>
 21 #include <linux/module.h>
 22 #include <linux/gfp.h>
 23 #include <linux/pci.h>
 24 #include <linux/blkdev.h>
 25 #include <linux/delay.h>
 26 #include <linux/interrupt.h>
 27 #include <linux/dma-mapping.h>
 28 #include <linux/device.h>
 29 #include <scsi/scsi_host.h>
 30 #include <scsi/scsi_cmnd.h>
 31 #include <linux/libata.h>
 32 
 33 #define DRV_NAME        "sata_sil24"
 34 #define DRV_VERSION     "1.1"
 35 
 36 /*
 37  * Port request block (PRB) 32 bytes
 38  */
 39 struct sil24_prb {
 40         __le16  ctrl;
 41         __le16  prot;
 42         __le32  rx_cnt;
 43         u8      fis[6 * 4];
 44 };
 45 
 46 /*
 47  * Scatter gather entry (SGE) 16 bytes
 48  */
 49 struct sil24_sge {
 50         __le64  addr;
 51         __le32  cnt;
 52         __le32  flags;
 53 };
 54 
 55 
 56 enum {
 57         SIL24_HOST_BAR          = 0,
 58         SIL24_PORT_BAR          = 2,
 59 
 60         /* sil24 fetches in chunks of 64bytes.  The first block
 61          * contains the PRB and two SGEs.  From the second block, it's
 62          * consisted of four SGEs and called SGT.  Calculate the
 63          * number of SGTs that fit into one page.
 64          */
 65         SIL24_PRB_SZ            = sizeof(struct sil24_prb)
 66                                   + 2 * sizeof(struct sil24_sge),
 67         SIL24_MAX_SGT           = (PAGE_SIZE - SIL24_PRB_SZ)
 68                                   / (4 * sizeof(struct sil24_sge)),
 69 
 70         /* This will give us one unused SGEs for ATA.  This extra SGE
 71          * will be used to store CDB for ATAPI devices.
 72          */
 73         SIL24_MAX_SGE           = 4 * SIL24_MAX_SGT + 1,
 74 
 75         /*
 76          * Global controller registers (128 bytes @ BAR0)
 77          */
 78                 /* 32 bit regs */
 79         HOST_SLOT_STAT          = 0x00, /* 32 bit slot stat * 4 */
 80         HOST_CTRL               = 0x40,
 81         HOST_IRQ_STAT           = 0x44,
 82         HOST_PHY_CFG            = 0x48,
 83         HOST_BIST_CTRL          = 0x50,
 84         HOST_BIST_PTRN          = 0x54,
 85         HOST_BIST_STAT          = 0x58,
 86         HOST_MEM_BIST_STAT      = 0x5c,
 87         HOST_FLASH_CMD          = 0x70,
 88                 /* 8 bit regs */
 89         HOST_FLASH_DATA         = 0x74,
 90         HOST_TRANSITION_DETECT  = 0x75,
 91         HOST_GPIO_CTRL          = 0x76,
 92         HOST_I2C_ADDR           = 0x78, /* 32 bit */
 93         HOST_I2C_DATA           = 0x7c,
 94         HOST_I2C_XFER_CNT       = 0x7e,
 95         HOST_I2C_CTRL           = 0x7f,
 96 
 97         /* HOST_SLOT_STAT bits */
 98         HOST_SSTAT_ATTN         = (1 << 31),
 99 
100         /* HOST_CTRL bits */
101         HOST_CTRL_M66EN         = (1 << 16), /* M66EN PCI bus signal */
102         HOST_CTRL_TRDY          = (1 << 17), /* latched PCI TRDY */
103         HOST_CTRL_STOP          = (1 << 18), /* latched PCI STOP */
104         HOST_CTRL_DEVSEL        = (1 << 19), /* latched PCI DEVSEL */
105         HOST_CTRL_REQ64         = (1 << 20), /* latched PCI REQ64 */
106         HOST_CTRL_GLOBAL_RST    = (1 << 31), /* global reset */
107 
108         /*
109          * Port registers
110          * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2)
111          */
112         PORT_REGS_SIZE          = 0x2000,
113 
114         PORT_LRAM               = 0x0000, /* 31 LRAM slots and PMP regs */
115         PORT_LRAM_SLOT_SZ       = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */
116 
117         PORT_PMP                = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */
118         PORT_PMP_STATUS         = 0x0000, /* port device status offset */
119         PORT_PMP_QACTIVE        = 0x0004, /* port device QActive offset */
120         PORT_PMP_SIZE           = 0x0008, /* 8 bytes per PMP */
121 
122                 /* 32 bit regs */
123         PORT_CTRL_STAT          = 0x1000, /* write: ctrl-set, read: stat */
124         PORT_CTRL_CLR           = 0x1004, /* write: ctrl-clear */
125         PORT_IRQ_STAT           = 0x1008, /* high: status, low: interrupt */
126         PORT_IRQ_ENABLE_SET     = 0x1010, /* write: enable-set */
127         PORT_IRQ_ENABLE_CLR     = 0x1014, /* write: enable-clear */
128         PORT_ACTIVATE_UPPER_ADDR= 0x101c,
129         PORT_EXEC_FIFO          = 0x1020, /* command execution fifo */
130         PORT_CMD_ERR            = 0x1024, /* command error number */
131         PORT_FIS_CFG            = 0x1028,
132         PORT_FIFO_THRES         = 0x102c,
133                 /* 16 bit regs */
134         PORT_DECODE_ERR_CNT     = 0x1040,
135         PORT_DECODE_ERR_THRESH  = 0x1042,
136         PORT_CRC_ERR_CNT        = 0x1044,
137         PORT_CRC_ERR_THRESH     = 0x1046,
138         PORT_HSHK_ERR_CNT       = 0x1048,
139         PORT_HSHK_ERR_THRESH    = 0x104a,
140                 /* 32 bit regs */
141         PORT_PHY_CFG            = 0x1050,
142         PORT_SLOT_STAT          = 0x1800,
143         PORT_CMD_ACTIVATE       = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */
144         PORT_CONTEXT            = 0x1e04,
145         PORT_EXEC_DIAG          = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */
146         PORT_PSD_DIAG           = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */
147         PORT_SCONTROL           = 0x1f00,
148         PORT_SSTATUS            = 0x1f04,
149         PORT_SERROR             = 0x1f08,
150         PORT_SACTIVE            = 0x1f0c,
151 
152         /* PORT_CTRL_STAT bits */
153         PORT_CS_PORT_RST        = (1 << 0), /* port reset */
154         PORT_CS_DEV_RST         = (1 << 1), /* device reset */
155         PORT_CS_INIT            = (1 << 2), /* port initialize */
156         PORT_CS_IRQ_WOC         = (1 << 3), /* interrupt write one to clear */
157         PORT_CS_CDB16           = (1 << 5), /* 0=12b cdb, 1=16b cdb */
158         PORT_CS_PMP_RESUME      = (1 << 6), /* PMP resume */
159         PORT_CS_32BIT_ACTV      = (1 << 10), /* 32-bit activation */
160         PORT_CS_PMP_EN          = (1 << 13), /* port multiplier enable */
161         PORT_CS_RDY             = (1 << 31), /* port ready to accept commands */
162 
163         /* PORT_IRQ_STAT/ENABLE_SET/CLR */
164         /* bits[11:0] are masked */
165         PORT_IRQ_COMPLETE       = (1 << 0), /* command(s) completed */
166         PORT_IRQ_ERROR          = (1 << 1), /* command execution error */
167         PORT_IRQ_PORTRDY_CHG    = (1 << 2), /* port ready change */
168         PORT_IRQ_PWR_CHG        = (1 << 3), /* power management change */
169         PORT_IRQ_PHYRDY_CHG     = (1 << 4), /* PHY ready change */
170         PORT_IRQ_COMWAKE        = (1 << 5), /* COMWAKE received */
171         PORT_IRQ_UNK_FIS        = (1 << 6), /* unknown FIS received */
172         PORT_IRQ_DEV_XCHG       = (1 << 7), /* device exchanged */
173         PORT_IRQ_8B10B          = (1 << 8), /* 8b/10b decode error threshold */
174         PORT_IRQ_CRC            = (1 << 9), /* CRC error threshold */
175         PORT_IRQ_HANDSHAKE      = (1 << 10), /* handshake error threshold */
176         PORT_IRQ_SDB_NOTIFY     = (1 << 11), /* SDB notify received */
177 
178         DEF_PORT_IRQ            = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR |
179                                   PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG |
180                                   PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY,
181 
182         /* bits[27:16] are unmasked (raw) */
183         PORT_IRQ_RAW_SHIFT      = 16,
184         PORT_IRQ_MASKED_MASK    = 0x7ff,
185         PORT_IRQ_RAW_MASK       = (0x7ff << PORT_IRQ_RAW_SHIFT),
186 
187         /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
188         PORT_IRQ_STEER_SHIFT    = 30,
189         PORT_IRQ_STEER_MASK     = (3 << PORT_IRQ_STEER_SHIFT),
190 
191         /* PORT_CMD_ERR constants */
192         PORT_CERR_DEV           = 1, /* Error bit in D2H Register FIS */
193         PORT_CERR_SDB           = 2, /* Error bit in SDB FIS */
194         PORT_CERR_DATA          = 3, /* Error in data FIS not detected by dev */
195         PORT_CERR_SEND          = 4, /* Initial cmd FIS transmission failure */
196         PORT_CERR_INCONSISTENT  = 5, /* Protocol mismatch */
197         PORT_CERR_DIRECTION     = 6, /* Data direction mismatch */
198         PORT_CERR_UNDERRUN      = 7, /* Ran out of SGEs while writing */
199         PORT_CERR_OVERRUN       = 8, /* Ran out of SGEs while reading */
200         PORT_CERR_PKT_PROT      = 11, /* DIR invalid in 1st PIO setup of ATAPI */
201         PORT_CERR_SGT_BOUNDARY  = 16, /* PLD ecode 00 - SGT not on qword boundary */
202         PORT_CERR_SGT_TGTABRT   = 17, /* PLD ecode 01 - target abort */
203         PORT_CERR_SGT_MSTABRT   = 18, /* PLD ecode 10 - master abort */
204         PORT_CERR_SGT_PCIPERR   = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */
205         PORT_CERR_CMD_BOUNDARY  = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */
206         PORT_CERR_CMD_TGTABRT   = 25, /* ctrl[15:13] 010 - target abort */
207         PORT_CERR_CMD_MSTABRT   = 26, /* ctrl[15:13] 100 - master abort */
208         PORT_CERR_CMD_PCIPERR   = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */
209         PORT_CERR_XFR_UNDEF     = 32, /* PSD ecode 00 - undefined */
210         PORT_CERR_XFR_TGTABRT   = 33, /* PSD ecode 01 - target abort */
211         PORT_CERR_XFR_MSTABRT   = 34, /* PSD ecode 10 - master abort */
212         PORT_CERR_XFR_PCIPERR   = 35, /* PSD ecode 11 - PCI prity err during transfer */
213         PORT_CERR_SENDSERVICE   = 36, /* FIS received while sending service */
214 
215         /* bits of PRB control field */
216         PRB_CTRL_PROTOCOL       = (1 << 0), /* override def. ATA protocol */
217         PRB_CTRL_PACKET_READ    = (1 << 4), /* PACKET cmd read */
218         PRB_CTRL_PACKET_WRITE   = (1 << 5), /* PACKET cmd write */
219         PRB_CTRL_NIEN           = (1 << 6), /* Mask completion irq */
220         PRB_CTRL_SRST           = (1 << 7), /* Soft reset request (ign BSY?) */
221 
222         /* PRB protocol field */
223         PRB_PROT_PACKET         = (1 << 0),
224         PRB_PROT_TCQ            = (1 << 1),
225         PRB_PROT_NCQ            = (1 << 2),
226         PRB_PROT_READ           = (1 << 3),
227         PRB_PROT_WRITE          = (1 << 4),
228         PRB_PROT_TRANSPARENT    = (1 << 5),
229 
230         /*
231          * Other constants
232          */
233         SGE_TRM                 = (1 << 31), /* Last SGE in chain */
234         SGE_LNK                 = (1 << 30), /* linked list
235                                                 Points to SGT, not SGE */
236         SGE_DRD                 = (1 << 29), /* discard data read (/dev/null)
237                                                 data address ignored */
238 
239         SIL24_MAX_CMDS          = 31,
240 
241         /* board id */
242         BID_SIL3124             = 0,
243         BID_SIL3132             = 1,
244         BID_SIL3131             = 2,
245 
246         /* host flags */
247         SIL24_COMMON_FLAGS      = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
248                                   ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA |
249                                   ATA_FLAG_AN | ATA_FLAG_PMP,
250         SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */
251 
252         IRQ_STAT_4PORTS         = 0xf,
253 };
254 
255 struct sil24_ata_block {
256         struct sil24_prb prb;
257         struct sil24_sge sge[SIL24_MAX_SGE];
258 };
259 
260 struct sil24_atapi_block {
261         struct sil24_prb prb;
262         u8 cdb[16];
263         struct sil24_sge sge[SIL24_MAX_SGE];
264 };
265 
266 union sil24_cmd_block {
267         struct sil24_ata_block ata;
268         struct sil24_atapi_block atapi;
269 };
270 
271 static const struct sil24_cerr_info {
272         unsigned int err_mask, action;
273         const char *desc;
274 } sil24_cerr_db[] = {
275         [0]                     = { AC_ERR_DEV, 0,
276                                     "device error" },
277         [PORT_CERR_DEV]         = { AC_ERR_DEV, 0,
278                                     "device error via D2H FIS" },
279         [PORT_CERR_SDB]         = { AC_ERR_DEV, 0,
280                                     "device error via SDB FIS" },
281         [PORT_CERR_DATA]        = { AC_ERR_ATA_BUS, ATA_EH_RESET,
282                                     "error in data FIS" },
283         [PORT_CERR_SEND]        = { AC_ERR_ATA_BUS, ATA_EH_RESET,
284                                     "failed to transmit command FIS" },
285         [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET,
286                                      "protocol mismatch" },
287         [PORT_CERR_DIRECTION]   = { AC_ERR_HSM, ATA_EH_RESET,
288                                     "data directon mismatch" },
289         [PORT_CERR_UNDERRUN]    = { AC_ERR_HSM, ATA_EH_RESET,
290                                     "ran out of SGEs while writing" },
291         [PORT_CERR_OVERRUN]     = { AC_ERR_HSM, ATA_EH_RESET,
292                                     "ran out of SGEs while reading" },
293         [PORT_CERR_PKT_PROT]    = { AC_ERR_HSM, ATA_EH_RESET,
294                                     "invalid data directon for ATAPI CDB" },
295         [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
296                                      "SGT not on qword boundary" },
297         [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
298                                     "PCI target abort while fetching SGT" },
299         [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
300                                     "PCI master abort while fetching SGT" },
301         [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
302                                     "PCI parity error while fetching SGT" },
303         [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET,
304                                      "PRB not on qword boundary" },
305         [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
306                                     "PCI target abort while fetching PRB" },
307         [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
308                                     "PCI master abort while fetching PRB" },
309         [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
310                                     "PCI parity error while fetching PRB" },
311         [PORT_CERR_XFR_UNDEF]   = { AC_ERR_HOST_BUS, ATA_EH_RESET,
312                                     "undefined error while transferring data" },
313         [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
314                                     "PCI target abort while transferring data" },
315         [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
316                                     "PCI master abort while transferring data" },
317         [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET,
318                                     "PCI parity error while transferring data" },
319         [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET,
320                                     "FIS received while sending service FIS" },
321 };
322 
323 /*
324  * ap->private_data
325  *
326  * The preview driver always returned 0 for status.  We emulate it
327  * here from the previous interrupt.
328  */
329 struct sil24_port_priv {
330         union sil24_cmd_block *cmd_block;       /* 32 cmd blocks */
331         dma_addr_t cmd_block_dma;               /* DMA base addr for them */
332         int do_port_rst;
333 };
334 
335 static void sil24_dev_config(struct ata_device *dev);
336 static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val);
337 static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val);
338 static int sil24_qc_defer(struct ata_queued_cmd *qc);
339 static void sil24_qc_prep(struct ata_queued_cmd *qc);
340 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc);
341 static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc);
342 static void sil24_pmp_attach(struct ata_port *ap);
343 static void sil24_pmp_detach(struct ata_port *ap);
344 static void sil24_freeze(struct ata_port *ap);
345 static void sil24_thaw(struct ata_port *ap);
346 static int sil24_softreset(struct ata_link *link, unsigned int *class,
347                            unsigned long deadline);
348 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
349                            unsigned long deadline);
350 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
351                                unsigned long deadline);
352 static void sil24_error_handler(struct ata_port *ap);
353 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc);
354 static int sil24_port_start(struct ata_port *ap);
355 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
356 #ifdef CONFIG_PM_SLEEP
357 static int sil24_pci_device_resume(struct pci_dev *pdev);
358 #endif
359 #ifdef CONFIG_PM
360 static int sil24_port_resume(struct ata_port *ap);
361 #endif
362 
363 static const struct pci_device_id sil24_pci_tbl[] = {
364         { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 },
365         { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 },
366         { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 },
367         { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 },
368         { PCI_VDEVICE(CMD, 0x0244), BID_SIL3132 },
369         { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 },
370         { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 },
371 
372         { } /* terminate list */
373 };
374 
375 static struct pci_driver sil24_pci_driver = {
376         .name                   = DRV_NAME,
377         .id_table               = sil24_pci_tbl,
378         .probe                  = sil24_init_one,
379         .remove                 = ata_pci_remove_one,
380 #ifdef CONFIG_PM_SLEEP
381         .suspend                = ata_pci_device_suspend,
382         .resume                 = sil24_pci_device_resume,
383 #endif
384 };
385 
386 static struct scsi_host_template sil24_sht = {
387         ATA_NCQ_SHT(DRV_NAME),
388         .can_queue              = SIL24_MAX_CMDS,
389         .sg_tablesize           = SIL24_MAX_SGE,
390         .dma_boundary           = ATA_DMA_BOUNDARY,
391 };
392 
393 static struct ata_port_operations sil24_ops = {
394         .inherits               = &sata_pmp_port_ops,
395 
396         .qc_defer               = sil24_qc_defer,
397         .qc_prep                = sil24_qc_prep,
398         .qc_issue               = sil24_qc_issue,
399         .qc_fill_rtf            = sil24_qc_fill_rtf,
400 
401         .freeze                 = sil24_freeze,
402         .thaw                   = sil24_thaw,
403         .softreset              = sil24_softreset,
404         .hardreset              = sil24_hardreset,
405         .pmp_softreset          = sil24_softreset,
406         .pmp_hardreset          = sil24_pmp_hardreset,
407         .error_handler          = sil24_error_handler,
408         .post_internal_cmd      = sil24_post_internal_cmd,
409         .dev_config             = sil24_dev_config,
410 
411         .scr_read               = sil24_scr_read,
412         .scr_write              = sil24_scr_write,
413         .pmp_attach             = sil24_pmp_attach,
414         .pmp_detach             = sil24_pmp_detach,
415 
416         .port_start             = sil24_port_start,
417 #ifdef CONFIG_PM
418         .port_resume            = sil24_port_resume,
419 #endif
420 };
421 
422 static bool sata_sil24_msi;    /* Disable MSI */
423 module_param_named(msi, sata_sil24_msi, bool, S_IRUGO);
424 MODULE_PARM_DESC(msi, "Enable MSI (Default: false)");
425 
426 /*
427  * Use bits 30-31 of port_flags to encode available port numbers.
428  * Current maxium is 4.
429  */
430 #define SIL24_NPORTS2FLAG(nports)       ((((unsigned)(nports) - 1) & 0x3) << 30)
431 #define SIL24_FLAG2NPORTS(flag)         ((((flag) >> 30) & 0x3) + 1)
432 
433 static const struct ata_port_info sil24_port_info[] = {
434         /* sil_3124 */
435         {
436                 .flags          = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) |
437                                   SIL24_FLAG_PCIX_IRQ_WOC,
438                 .pio_mask       = ATA_PIO4,
439                 .mwdma_mask     = ATA_MWDMA2,
440                 .udma_mask      = ATA_UDMA5,
441                 .port_ops       = &sil24_ops,
442         },
443         /* sil_3132 */
444         {
445                 .flags          = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2),
446                 .pio_mask       = ATA_PIO4,
447                 .mwdma_mask     = ATA_MWDMA2,
448                 .udma_mask      = ATA_UDMA5,
449                 .port_ops       = &sil24_ops,
450         },
451         /* sil_3131/sil_3531 */
452         {
453                 .flags          = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1),
454                 .pio_mask       = ATA_PIO4,
455                 .mwdma_mask     = ATA_MWDMA2,
456                 .udma_mask      = ATA_UDMA5,
457                 .port_ops       = &sil24_ops,
458         },
459 };
460 
461 static int sil24_tag(int tag)
462 {
463         if (unlikely(ata_tag_internal(tag)))
464                 return 0;
465         return tag;
466 }
467 
468 static unsigned long sil24_port_offset(struct ata_port *ap)
469 {
470         return ap->port_no * PORT_REGS_SIZE;
471 }
472 
473 static void __iomem *sil24_port_base(struct ata_port *ap)
474 {
475         return ap->host->iomap[SIL24_PORT_BAR] + sil24_port_offset(ap);
476 }
477 
478 static void sil24_dev_config(struct ata_device *dev)
479 {
480         void __iomem *port = sil24_port_base(dev->link->ap);
481 
482         if (dev->cdb_len == 16)
483                 writel(PORT_CS_CDB16, port + PORT_CTRL_STAT);
484         else
485                 writel(PORT_CS_CDB16, port + PORT_CTRL_CLR);
486 }
487 
488 static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf)
489 {
490         void __iomem *port = sil24_port_base(ap);
491         struct sil24_prb __iomem *prb;
492         u8 fis[6 * 4];
493 
494         prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ;
495         memcpy_fromio(fis, prb->fis, sizeof(fis));
496         ata_tf_from_fis(fis, tf);
497 }
498 
499 static int sil24_scr_map[] = {
500         [SCR_CONTROL]   = 0,
501         [SCR_STATUS]    = 1,
502         [SCR_ERROR]     = 2,
503         [SCR_ACTIVE]    = 3,
504 };
505 
506 static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
507 {
508         void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL;
509 
510         if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
511                 *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4);
512                 return 0;
513         }
514         return -EINVAL;
515 }
516 
517 static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
518 {
519         void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL;
520 
521         if (sc_reg < ARRAY_SIZE(sil24_scr_map)) {
522                 writel(val, scr_addr + sil24_scr_map[sc_reg] * 4);
523                 return 0;
524         }
525         return -EINVAL;
526 }
527 
528 static void sil24_config_port(struct ata_port *ap)
529 {
530         void __iomem *port = sil24_port_base(ap);
531 
532         /* configure IRQ WoC */
533         if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
534                 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT);
535         else
536                 writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR);
537 
538         /* zero error counters. */
539         writew(0x8000, port + PORT_DECODE_ERR_THRESH);
540         writew(0x8000, port + PORT_CRC_ERR_THRESH);
541         writew(0x8000, port + PORT_HSHK_ERR_THRESH);
542         writew(0x0000, port + PORT_DECODE_ERR_CNT);
543         writew(0x0000, port + PORT_CRC_ERR_CNT);
544         writew(0x0000, port + PORT_HSHK_ERR_CNT);
545 
546         /* always use 64bit activation */
547         writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR);
548 
549         /* clear port multiplier enable and resume bits */
550         writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
551 }
552 
553 static void sil24_config_pmp(struct ata_port *ap, int attached)
554 {
555         void __iomem *port = sil24_port_base(ap);
556 
557         if (attached)
558                 writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT);
559         else
560                 writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR);
561 }
562 
563 static void sil24_clear_pmp(struct ata_port *ap)
564 {
565         void __iomem *port = sil24_port_base(ap);
566         int i;
567 
568         writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR);
569 
570         for (i = 0; i < SATA_PMP_MAX_PORTS; i++) {
571                 void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE;
572 
573                 writel(0, pmp_base + PORT_PMP_STATUS);
574                 writel(0, pmp_base + PORT_PMP_QACTIVE);
575         }
576 }
577 
578 static int sil24_init_port(struct ata_port *ap)
579 {
580         void __iomem *port = sil24_port_base(ap);
581         struct sil24_port_priv *pp = ap->private_data;
582         u32 tmp;
583 
584         /* clear PMP error status */
585         if (sata_pmp_attached(ap))
586                 sil24_clear_pmp(ap);
587 
588         writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
589         ata_wait_register(ap, port + PORT_CTRL_STAT,
590                           PORT_CS_INIT, PORT_CS_INIT, 10, 100);
591         tmp = ata_wait_register(ap, port + PORT_CTRL_STAT,
592                                 PORT_CS_RDY, 0, 10, 100);
593 
594         if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
595                 pp->do_port_rst = 1;
596                 ap->link.eh_context.i.action |= ATA_EH_RESET;
597                 return -EIO;
598         }
599 
600         return 0;
601 }
602 
603 static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp,
604                                  const struct ata_taskfile *tf,
605                                  int is_cmd, u32 ctrl,
606                                  unsigned long timeout_msec)
607 {
608         void __iomem *port = sil24_port_base(ap);
609         struct sil24_port_priv *pp = ap->private_data;
610         struct sil24_prb *prb = &pp->cmd_block[0].ata.prb;
611         dma_addr_t paddr = pp->cmd_block_dma;
612         u32 irq_enabled, irq_mask, irq_stat;
613         int rc;
614 
615         prb->ctrl = cpu_to_le16(ctrl);
616         ata_tf_to_fis(tf, pmp, is_cmd, prb->fis);
617 
618         /* temporarily plug completion and error interrupts */
619         irq_enabled = readl(port + PORT_IRQ_ENABLE_SET);
620         writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR);
621 
622         /*
623          * The barrier is required to ensure that writes to cmd_block reach
624          * the memory before the write to PORT_CMD_ACTIVATE.
625          */
626         wmb();
627         writel((u32)paddr, port + PORT_CMD_ACTIVATE);
628         writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
629 
630         irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
631         irq_stat = ata_wait_register(ap, port + PORT_IRQ_STAT, irq_mask, 0x0,
632                                      10, timeout_msec);
633 
634         writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
635         irq_stat >>= PORT_IRQ_RAW_SHIFT;
636 
637         if (irq_stat & PORT_IRQ_COMPLETE)
638                 rc = 0;
639         else {
640                 /* force port into known state */
641                 sil24_init_port(ap);
642 
643                 if (irq_stat & PORT_IRQ_ERROR)
644                         rc = -EIO;
645                 else
646                         rc = -EBUSY;
647         }
648 
649         /* restore IRQ enabled */
650         writel(irq_enabled, port + PORT_IRQ_ENABLE_SET);
651 
652         return rc;
653 }
654 
655 static int sil24_softreset(struct ata_link *link, unsigned int *class,
656                            unsigned long deadline)
657 {
658         struct ata_port *ap = link->ap;
659         int pmp = sata_srst_pmp(link);
660         unsigned long timeout_msec = 0;
661         struct ata_taskfile tf;
662         const char *reason;
663         int rc;
664 
665         DPRINTK("ENTER\n");
666 
667         /* put the port into known state */
668         if (sil24_init_port(ap)) {
669                 reason = "port not ready";
670                 goto err;
671         }
672 
673         /* do SRST */
674         if (time_after(deadline, jiffies))
675                 timeout_msec = jiffies_to_msecs(deadline - jiffies);
676 
677         ata_tf_init(link->device, &tf); /* doesn't really matter */
678         rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST,
679                                    timeout_msec);
680         if (rc == -EBUSY) {
681                 reason = "timeout";
682                 goto err;
683         } else if (rc) {
684                 reason = "SRST command error";
685                 goto err;
686         }
687 
688         sil24_read_tf(ap, 0, &tf);
689         *class = ata_dev_classify(&tf);
690 
691         DPRINTK("EXIT, class=%u\n", *class);
692         return 0;
693 
694  err:
695         ata_link_err(link, "softreset failed (%s)\n", reason);
696         return -EIO;
697 }
698 
699 static int sil24_hardreset(struct ata_link *link, unsigned int *class,
700                            unsigned long deadline)
701 {
702         struct ata_port *ap = link->ap;
703         void __iomem *port = sil24_port_base(ap);
704         struct sil24_port_priv *pp = ap->private_data;
705         int did_port_rst = 0;
706         const char *reason;
707         int tout_msec, rc;
708         u32 tmp;
709 
710  retry:
711         /* Sometimes, DEV_RST is not enough to recover the controller.
712          * This happens often after PM DMA CS errata.
713          */
714         if (pp->do_port_rst) {
715                 ata_port_warn(ap,
716                               "controller in dubious state, performing PORT_RST\n");
717 
718                 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
719                 ata_msleep(ap, 10);
720                 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
721                 ata_wait_register(ap, port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
722                                   10, 5000);
723 
724                 /* restore port configuration */
725                 sil24_config_port(ap);
726                 sil24_config_pmp(ap, ap->nr_pmp_links);
727 
728                 pp->do_port_rst = 0;
729                 did_port_rst = 1;
730         }
731 
732         /* sil24 does the right thing(tm) without any protection */
733         sata_set_spd(link);
734 
735         tout_msec = 100;
736         if (ata_link_online(link))
737                 tout_msec = 5000;
738 
739         writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
740         tmp = ata_wait_register(ap, port + PORT_CTRL_STAT,
741                                 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
742                                 tout_msec);
743 
744         /* SStatus oscillates between zero and valid status after
745          * DEV_RST, debounce it.
746          */
747         rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
748         if (rc) {
749                 reason = "PHY debouncing failed";
750                 goto err;
751         }
752 
753         if (tmp & PORT_CS_DEV_RST) {
754                 if (ata_link_offline(link))
755                         return 0;
756                 reason = "link not ready";
757                 goto err;
758         }
759 
760         /* Sil24 doesn't store signature FIS after hardreset, so we
761          * can't wait for BSY to clear.  Some devices take a long time
762          * to get ready and those devices will choke if we don't wait
763          * for BSY clearance here.  Tell libata to perform follow-up
764          * softreset.
765          */
766         return -EAGAIN;
767 
768  err:
769         if (!did_port_rst) {
770                 pp->do_port_rst = 1;
771                 goto retry;
772         }
773 
774         ata_link_err(link, "hardreset failed (%s)\n", reason);
775         return -EIO;
776 }
777 
778 static inline void sil24_fill_sg(struct ata_queued_cmd *qc,
779                                  struct sil24_sge *sge)
780 {
781         struct scatterlist *sg;
782         struct sil24_sge *last_sge = NULL;
783         unsigned int si;
784 
785         for_each_sg(qc->sg, sg, qc->n_elem, si) {
786                 sge->addr = cpu_to_le64(sg_dma_address(sg));
787                 sge->cnt = cpu_to_le32(sg_dma_len(sg));
788                 sge->flags = 0;
789 
790                 last_sge = sge;
791                 sge++;
792         }
793 
794         last_sge->flags = cpu_to_le32(SGE_TRM);
795 }
796 
797 static int sil24_qc_defer(struct ata_queued_cmd *qc)
798 {
799         struct ata_link *link = qc->dev->link;
800         struct ata_port *ap = link->ap;
801         u8 prot = qc->tf.protocol;
802 
803         /*
804          * There is a bug in the chip:
805          * Port LRAM Causes the PRB/SGT Data to be Corrupted
806          * If the host issues a read request for LRAM and SActive registers
807          * while active commands are available in the port, PRB/SGT data in
808          * the LRAM can become corrupted. This issue applies only when
809          * reading from, but not writing to, the LRAM.
810          *
811          * Therefore, reading LRAM when there is no particular error [and
812          * other commands may be outstanding] is prohibited.
813          *
814          * To avoid this bug there are two situations where a command must run
815          * exclusive of any other commands on the port:
816          *
817          * - ATAPI commands which check the sense data
818          * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF
819          *   set.
820          *
821          */
822         int is_excl = (ata_is_atapi(prot) ||
823                        (qc->flags & ATA_QCFLAG_RESULT_TF));
824 
825         if (unlikely(ap->excl_link)) {
826                 if (link == ap->excl_link) {
827                         if (ap->nr_active_links)
828                                 return ATA_DEFER_PORT;
829                         qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
830                 } else
831                         return ATA_DEFER_PORT;
832         } else if (unlikely(is_excl)) {
833                 ap->excl_link = link;
834                 if (ap->nr_active_links)
835                         return ATA_DEFER_PORT;
836                 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
837         }
838 
839         return ata_std_qc_defer(qc);
840 }
841 
842 static void sil24_qc_prep(struct ata_queued_cmd *qc)
843 {
844         struct ata_port *ap = qc->ap;
845         struct sil24_port_priv *pp = ap->private_data;
846         union sil24_cmd_block *cb;
847         struct sil24_prb *prb;
848         struct sil24_sge *sge;
849         u16 ctrl = 0;
850 
851         cb = &pp->cmd_block[sil24_tag(qc->tag)];
852 
853         if (!ata_is_atapi(qc->tf.protocol)) {
854                 prb = &cb->ata.prb;
855                 sge = cb->ata.sge;
856                 if (ata_is_data(qc->tf.protocol)) {
857                         u16 prot = 0;
858                         ctrl = PRB_CTRL_PROTOCOL;
859                         if (ata_is_ncq(qc->tf.protocol))
860                                 prot |= PRB_PROT_NCQ;
861                         if (qc->tf.flags & ATA_TFLAG_WRITE)
862                                 prot |= PRB_PROT_WRITE;
863                         else
864                                 prot |= PRB_PROT_READ;
865                         prb->prot = cpu_to_le16(prot);
866                 }
867         } else {
868                 prb = &cb->atapi.prb;
869                 sge = cb->atapi.sge;
870                 memset(cb->atapi.cdb, 0, sizeof(cb->atapi.cdb));
871                 memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len);
872 
873                 if (ata_is_data(qc->tf.protocol)) {
874                         if (qc->tf.flags & ATA_TFLAG_WRITE)
875                                 ctrl = PRB_CTRL_PACKET_WRITE;
876                         else
877                                 ctrl = PRB_CTRL_PACKET_READ;
878                 }
879         }
880 
881         prb->ctrl = cpu_to_le16(ctrl);
882         ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis);
883 
884         if (qc->flags & ATA_QCFLAG_DMAMAP)
885                 sil24_fill_sg(qc, sge);
886 }
887 
888 static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc)
889 {
890         struct ata_port *ap = qc->ap;
891         struct sil24_port_priv *pp = ap->private_data;
892         void __iomem *port = sil24_port_base(ap);
893         unsigned int tag = sil24_tag(qc->tag);
894         dma_addr_t paddr;
895         void __iomem *activate;
896 
897         paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block);
898         activate = port + PORT_CMD_ACTIVATE + tag * 8;
899 
900         /*
901          * The barrier is required to ensure that writes to cmd_block reach
902          * the memory before the write to PORT_CMD_ACTIVATE.
903          */
904         wmb();
905         writel((u32)paddr, activate);
906         writel((u64)paddr >> 32, activate + 4);
907 
908         return 0;
909 }
910 
911 static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc)
912 {
913         sil24_read_tf(qc->ap, qc->tag, &qc->result_tf);
914         return true;
915 }
916 
917 static void sil24_pmp_attach(struct ata_port *ap)
918 {
919         u32 *gscr = ap->link.device->gscr;
920 
921         sil24_config_pmp(ap, 1);
922         sil24_init_port(ap);
923 
924         if (sata_pmp_gscr_vendor(gscr) == 0x11ab &&
925             sata_pmp_gscr_devid(gscr) == 0x4140) {
926                 ata_port_info(ap,
927                         "disabling NCQ support due to sil24-mv4140 quirk\n");
928                 ap->flags &= ~ATA_FLAG_NCQ;
929         }
930 }
931 
932 static void sil24_pmp_detach(struct ata_port *ap)
933 {
934         sil24_init_port(ap);
935         sil24_config_pmp(ap, 0);
936 
937         ap->flags |= ATA_FLAG_NCQ;
938 }
939 
940 static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class,
941                                unsigned long deadline)
942 {
943         int rc;
944 
945         rc = sil24_init_port(link->ap);
946         if (rc) {
947                 ata_link_err(link, "hardreset failed (port not ready)\n");
948                 return rc;
949         }
950 
951         return sata_std_hardreset(link, class, deadline);
952 }
953 
954 static void sil24_freeze(struct ata_port *ap)
955 {
956         void __iomem *port = sil24_port_base(ap);
957 
958         /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear
959          * PORT_IRQ_ENABLE instead.
960          */
961         writel(0xffff, port + PORT_IRQ_ENABLE_CLR);
962 }
963 
964 static void sil24_thaw(struct ata_port *ap)
965 {
966         void __iomem *port = sil24_port_base(ap);
967         u32 tmp;
968 
969         /* clear IRQ */
970         tmp = readl(port + PORT_IRQ_STAT);
971         writel(tmp, port + PORT_IRQ_STAT);
972 
973         /* turn IRQ back on */
974         writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET);
975 }
976 
977 static void sil24_error_intr(struct ata_port *ap)
978 {
979         void __iomem *port = sil24_port_base(ap);
980         struct sil24_port_priv *pp = ap->private_data;
981         struct ata_queued_cmd *qc = NULL;
982         struct ata_link *link;
983         struct ata_eh_info *ehi;
984         int abort = 0, freeze = 0;
985         u32 irq_stat;
986 
987         /* on error, we need to clear IRQ explicitly */
988         irq_stat = readl(port + PORT_IRQ_STAT);
989         writel(irq_stat, port + PORT_IRQ_STAT);
990 
991         /* first, analyze and record host port events */
992         link = &ap->link;
993         ehi = &link->eh_info;
994         ata_ehi_clear_desc(ehi);
995 
996         ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat);
997 
998         if (irq_stat & PORT_IRQ_SDB_NOTIFY) {
999                 ata_ehi_push_desc(ehi, "SDB notify");
1000                 sata_async_notification(ap);
1001         }
1002 
1003         if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) {
1004                 ata_ehi_hotplugged(ehi);
1005                 ata_ehi_push_desc(ehi, "%s",
1006                                   irq_stat & PORT_IRQ_PHYRDY_CHG ?
1007                                   "PHY RDY changed" : "device exchanged");
1008                 freeze = 1;
1009         }
1010 
1011         if (irq_stat & PORT_IRQ_UNK_FIS) {
1012                 ehi->err_mask |= AC_ERR_HSM;
1013                 ehi->action |= ATA_EH_RESET;
1014                 ata_ehi_push_desc(ehi, "unknown FIS");
1015                 freeze = 1;
1016         }
1017 
1018         /* deal with command error */
1019         if (irq_stat & PORT_IRQ_ERROR) {
1020                 const struct sil24_cerr_info *ci = NULL;
1021                 unsigned int err_mask = 0, action = 0;
1022                 u32 context, cerr;
1023                 int pmp;
1024 
1025                 abort = 1;
1026 
1027                 /* DMA Context Switch Failure in Port Multiplier Mode
1028                  * errata.  If we have active commands to 3 or more
1029                  * devices, any error condition on active devices can
1030                  * corrupt DMA context switching.
1031                  */
1032                 if (ap->nr_active_links >= 3) {
1033                         ehi->err_mask |= AC_ERR_OTHER;
1034                         ehi->action |= ATA_EH_RESET;
1035                         ata_ehi_push_desc(ehi, "PMP DMA CS errata");
1036                         pp->do_port_rst = 1;
1037                         freeze = 1;
1038                 }
1039 
1040                 /* find out the offending link and qc */
1041                 if (sata_pmp_attached(ap)) {
1042                         context = readl(port + PORT_CONTEXT);
1043                         pmp = (context >> 5) & 0xf;
1044 
1045                         if (pmp < ap->nr_pmp_links) {
1046                                 link = &ap->pmp_link[pmp];
1047                                 ehi = &link->eh_info;
1048                                 qc = ata_qc_from_tag(ap, link->active_tag);
1049 
1050                                 ata_ehi_clear_desc(ehi);
1051                                 ata_ehi_push_desc(ehi, "irq_stat 0x%08x",
1052                                                   irq_stat);
1053                         } else {
1054                                 err_mask |= AC_ERR_HSM;
1055                                 action |= ATA_EH_RESET;
1056                                 freeze = 1;
1057                         }
1058                 } else
1059                         qc = ata_qc_from_tag(ap, link->active_tag);
1060 
1061                 /* analyze CMD_ERR */
1062                 cerr = readl(port + PORT_CMD_ERR);
1063                 if (cerr < ARRAY_SIZE(sil24_cerr_db))
1064                         ci = &sil24_cerr_db[cerr];
1065 
1066                 if (ci && ci->desc) {
1067                         err_mask |= ci->err_mask;
1068                         action |= ci->action;
1069                         if (action & ATA_EH_RESET)
1070                                 freeze = 1;
1071                         ata_ehi_push_desc(ehi, "%s", ci->desc);
1072                 } else {
1073                         err_mask |= AC_ERR_OTHER;
1074                         action |= ATA_EH_RESET;
1075                         freeze = 1;
1076                         ata_ehi_push_desc(ehi, "unknown command error %d",
1077                                           cerr);
1078                 }
1079 
1080                 /* record error info */
1081                 if (qc)
1082                         qc->err_mask |= err_mask;
1083                 else
1084                         ehi->err_mask |= err_mask;
1085 
1086                 ehi->action |= action;
1087 
1088                 /* if PMP, resume */
1089                 if (sata_pmp_attached(ap))
1090                         writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT);
1091         }
1092 
1093         /* freeze or abort */
1094         if (freeze)
1095                 ata_port_freeze(ap);
1096         else if (abort) {
1097                 if (qc)
1098                         ata_link_abort(qc->dev->link);
1099                 else
1100                         ata_port_abort(ap);
1101         }
1102 }
1103 
1104 static inline void sil24_host_intr(struct ata_port *ap)
1105 {
1106         void __iomem *port = sil24_port_base(ap);
1107         u32 slot_stat, qc_active;
1108         int rc;
1109 
1110         /* If PCIX_IRQ_WOC, there's an inherent race window between
1111          * clearing IRQ pending status and reading PORT_SLOT_STAT
1112          * which may cause spurious interrupts afterwards.  This is
1113          * unavoidable and much better than losing interrupts which
1114          * happens if IRQ pending is cleared after reading
1115          * PORT_SLOT_STAT.
1116          */
1117         if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC)
1118                 writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT);
1119 
1120         slot_stat = readl(port + PORT_SLOT_STAT);
1121 
1122         if (unlikely(slot_stat & HOST_SSTAT_ATTN)) {
1123                 sil24_error_intr(ap);
1124                 return;
1125         }
1126 
1127         qc_active = slot_stat & ~HOST_SSTAT_ATTN;
1128         rc = ata_qc_complete_multiple(ap, qc_active);
1129         if (rc > 0)
1130                 return;
1131         if (rc < 0) {
1132                 struct ata_eh_info *ehi = &ap->link.eh_info;
1133                 ehi->err_mask |= AC_ERR_HSM;
1134                 ehi->action |= ATA_EH_RESET;
1135                 ata_port_freeze(ap);
1136                 return;
1137         }
1138 
1139         /* spurious interrupts are expected if PCIX_IRQ_WOC */
1140         if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit())
1141                 ata_port_info(ap,
1142                         "spurious interrupt (slot_stat 0x%x active_tag %d sactive 0x%x)\n",
1143                         slot_stat, ap->link.active_tag, ap->link.sactive);
1144 }
1145 
1146 static irqreturn_t sil24_interrupt(int irq, void *dev_instance)
1147 {
1148         struct ata_host *host = dev_instance;
1149         void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1150         unsigned handled = 0;
1151         u32 status;
1152         int i;
1153 
1154         status = readl(host_base + HOST_IRQ_STAT);
1155 
1156         if (status == 0xffffffff) {
1157                 dev_err(host->dev, "IRQ status == 0xffffffff, "
1158                         "PCI fault or device removal?\n");
1159                 goto out;
1160         }
1161 
1162         if (!(status & IRQ_STAT_4PORTS))
1163                 goto out;
1164 
1165         spin_lock(&host->lock);
1166 
1167         for (i = 0; i < host->n_ports; i++)
1168                 if (status & (1 << i)) {
1169                         sil24_host_intr(host->ports[i]);
1170                         handled++;
1171                 }
1172 
1173         spin_unlock(&host->lock);
1174  out:
1175         return IRQ_RETVAL(handled);
1176 }
1177 
1178 static void sil24_error_handler(struct ata_port *ap)
1179 {
1180         struct sil24_port_priv *pp = ap->private_data;
1181 
1182         if (sil24_init_port(ap))
1183                 ata_eh_freeze_port(ap);
1184 
1185         sata_pmp_error_handler(ap);
1186 
1187         pp->do_port_rst = 0;
1188 }
1189 
1190 static void sil24_post_internal_cmd(struct ata_queued_cmd *qc)
1191 {
1192         struct ata_port *ap = qc->ap;
1193 
1194         /* make DMA engine forget about the failed command */
1195         if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap))
1196                 ata_eh_freeze_port(ap);
1197 }
1198 
1199 static int sil24_port_start(struct ata_port *ap)
1200 {
1201         struct device *dev = ap->host->dev;
1202         struct sil24_port_priv *pp;
1203         union sil24_cmd_block *cb;
1204         size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS;
1205         dma_addr_t cb_dma;
1206 
1207         pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
1208         if (!pp)
1209                 return -ENOMEM;
1210 
1211         cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL);
1212         if (!cb)
1213                 return -ENOMEM;
1214         memset(cb, 0, cb_size);
1215 
1216         pp->cmd_block = cb;
1217         pp->cmd_block_dma = cb_dma;
1218 
1219         ap->private_data = pp;
1220 
1221         ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host");
1222         ata_port_pbar_desc(ap, SIL24_PORT_BAR, sil24_port_offset(ap), "port");
1223 
1224         return 0;
1225 }
1226 
1227 static void sil24_init_controller(struct ata_host *host)
1228 {
1229         void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1230         u32 tmp;
1231         int i;
1232 
1233         /* GPIO off */
1234         writel(0, host_base + HOST_FLASH_CMD);
1235 
1236         /* clear global reset & mask interrupts during initialization */
1237         writel(0, host_base + HOST_CTRL);
1238 
1239         /* init ports */
1240         for (i = 0; i < host->n_ports; i++) {
1241                 struct ata_port *ap = host->ports[i];
1242                 void __iomem *port = sil24_port_base(ap);
1243 
1244 
1245                 /* Initial PHY setting */
1246                 writel(0x20c, port + PORT_PHY_CFG);
1247 
1248                 /* Clear port RST */
1249                 tmp = readl(port + PORT_CTRL_STAT);
1250                 if (tmp & PORT_CS_PORT_RST) {
1251                         writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1252                         tmp = ata_wait_register(NULL, port + PORT_CTRL_STAT,
1253                                                 PORT_CS_PORT_RST,
1254                                                 PORT_CS_PORT_RST, 10, 100);
1255                         if (tmp & PORT_CS_PORT_RST)
1256                                 dev_err(host->dev,
1257                                         "failed to clear port RST\n");
1258                 }
1259 
1260                 /* configure port */
1261                 sil24_config_port(ap);
1262         }
1263 
1264         /* Turn on interrupts */
1265         writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL);
1266 }
1267 
1268 static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1269 {
1270         extern int __MARKER__sil24_cmd_block_is_sized_wrongly;
1271         struct ata_port_info pi = sil24_port_info[ent->driver_data];
1272         const struct ata_port_info *ppi[] = { &pi, NULL };
1273         void __iomem * const *iomap;
1274         struct ata_host *host;
1275         int rc;
1276         u32 tmp;
1277 
1278         /* cause link error if sil24_cmd_block is sized wrongly */
1279         if (sizeof(union sil24_cmd_block) != PAGE_SIZE)
1280                 __MARKER__sil24_cmd_block_is_sized_wrongly = 1;
1281 
1282         ata_print_version_once(&pdev->dev, DRV_VERSION);
1283 
1284         /* acquire resources */
1285         rc = pcim_enable_device(pdev);
1286         if (rc)
1287                 return rc;
1288 
1289         rc = pcim_iomap_regions(pdev,
1290                                 (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR),
1291                                 DRV_NAME);
1292         if (rc)
1293                 return rc;
1294         iomap = pcim_iomap_table(pdev);
1295 
1296         /* apply workaround for completion IRQ loss on PCI-X errata */
1297         if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) {
1298                 tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL);
1299                 if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL))
1300                         dev_info(&pdev->dev,
1301                                  "Applying completion IRQ loss on PCI-X errata fix\n");
1302                 else
1303                         pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC;
1304         }
1305 
1306         /* allocate and fill host */
1307         host = ata_host_alloc_pinfo(&pdev->dev, ppi,
1308                                     SIL24_FLAG2NPORTS(ppi[0]->flags));
1309         if (!host)
1310                 return -ENOMEM;
1311         host->iomap = iomap;
1312 
1313         /* configure and activate the device */
1314         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1315                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
1316                 if (rc) {
1317                         rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1318                         if (rc) {
1319                                 dev_err(&pdev->dev,
1320                                         "64-bit DMA enable failed\n");
1321                                 return rc;
1322                         }
1323                 }
1324         } else {
1325                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
1326                 if (rc) {
1327                         dev_err(&pdev->dev, "32-bit DMA enable failed\n");
1328                         return rc;
1329                 }
1330                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
1331                 if (rc) {
1332                         dev_err(&pdev->dev,
1333                                 "32-bit consistent DMA enable failed\n");
1334                         return rc;
1335                 }
1336         }
1337 
1338         /* Set max read request size to 4096.  This slightly increases
1339          * write throughput for pci-e variants.
1340          */
1341         pcie_set_readrq(pdev, 4096);
1342 
1343         sil24_init_controller(host);
1344 
1345         if (sata_sil24_msi && !pci_enable_msi(pdev)) {
1346                 dev_info(&pdev->dev, "Using MSI\n");
1347                 pci_intx(pdev, 0);
1348         }
1349 
1350         pci_set_master(pdev);
1351         return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED,
1352                                  &sil24_sht);
1353 }
1354 
1355 #ifdef CONFIG_PM_SLEEP
1356 static int sil24_pci_device_resume(struct pci_dev *pdev)
1357 {
1358         struct ata_host *host = pci_get_drvdata(pdev);
1359         void __iomem *host_base = host->iomap[SIL24_HOST_BAR];
1360         int rc;
1361 
1362         rc = ata_pci_device_do_resume(pdev);
1363         if (rc)
1364                 return rc;
1365 
1366         if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
1367                 writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL);
1368 
1369         sil24_init_controller(host);
1370 
1371         ata_host_resume(host);
1372 
1373         return 0;
1374 }
1375 #endif
1376 
1377 #ifdef CONFIG_PM
1378 static int sil24_port_resume(struct ata_port *ap)
1379 {
1380         sil24_config_pmp(ap, ap->nr_pmp_links);
1381         return 0;
1382 }
1383 #endif
1384 
1385 module_pci_driver(sil24_pci_driver);
1386 
1387 MODULE_AUTHOR("Tejun Heo");
1388 MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver");
1389 MODULE_LICENSE("GPL");
1390 MODULE_DEVICE_TABLE(pci, sil24_pci_tbl);
1391 

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