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Linux/drivers/ata/sata_rcar.c

  1 /*
  2  * Renesas R-Car SATA driver
  3  *
  4  * Author: Vladimir Barinov <source@cogentembedded.com>
  5  * Copyright (C) 2013 Cogent Embedded, Inc.
  6  * Copyright (C) 2013 Renesas Solutions Corp.
  7  *
  8  * This program is free software; you can redistribute  it and/or modify it
  9  * under  the terms of  the GNU General  Public License as published by the
 10  * Free Software Foundation;  either version 2 of the  License, or (at your
 11  * option) any later version.
 12  */
 13 
 14 #include <linux/kernel.h>
 15 #include <linux/module.h>
 16 #include <linux/ata.h>
 17 #include <linux/libata.h>
 18 #include <linux/of_device.h>
 19 #include <linux/platform_device.h>
 20 #include <linux/clk.h>
 21 #include <linux/err.h>
 22 
 23 #define DRV_NAME "sata_rcar"
 24 
 25 /* SH-Navi2G/ATAPI-ATA compatible task registers */
 26 #define DATA_REG                        0x100
 27 #define SDEVCON_REG                     0x138
 28 
 29 /* SH-Navi2G/ATAPI module compatible control registers */
 30 #define ATAPI_CONTROL1_REG              0x180
 31 #define ATAPI_STATUS_REG                0x184
 32 #define ATAPI_INT_ENABLE_REG            0x188
 33 #define ATAPI_DTB_ADR_REG               0x198
 34 #define ATAPI_DMA_START_ADR_REG         0x19C
 35 #define ATAPI_DMA_TRANS_CNT_REG         0x1A0
 36 #define ATAPI_CONTROL2_REG              0x1A4
 37 #define ATAPI_SIG_ST_REG                0x1B0
 38 #define ATAPI_BYTE_SWAP_REG             0x1BC
 39 
 40 /* ATAPI control 1 register (ATAPI_CONTROL1) bits */
 41 #define ATAPI_CONTROL1_ISM              BIT(16)
 42 #define ATAPI_CONTROL1_DTA32M           BIT(11)
 43 #define ATAPI_CONTROL1_RESET            BIT(7)
 44 #define ATAPI_CONTROL1_DESE             BIT(3)
 45 #define ATAPI_CONTROL1_RW               BIT(2)
 46 #define ATAPI_CONTROL1_STOP             BIT(1)
 47 #define ATAPI_CONTROL1_START            BIT(0)
 48 
 49 /* ATAPI status register (ATAPI_STATUS) bits */
 50 #define ATAPI_STATUS_SATAINT            BIT(11)
 51 #define ATAPI_STATUS_DNEND              BIT(6)
 52 #define ATAPI_STATUS_DEVTRM             BIT(5)
 53 #define ATAPI_STATUS_DEVINT             BIT(4)
 54 #define ATAPI_STATUS_ERR                BIT(2)
 55 #define ATAPI_STATUS_NEND               BIT(1)
 56 #define ATAPI_STATUS_ACT                BIT(0)
 57 
 58 /* Interrupt enable register (ATAPI_INT_ENABLE) bits */
 59 #define ATAPI_INT_ENABLE_SATAINT        BIT(11)
 60 #define ATAPI_INT_ENABLE_DNEND          BIT(6)
 61 #define ATAPI_INT_ENABLE_DEVTRM         BIT(5)
 62 #define ATAPI_INT_ENABLE_DEVINT         BIT(4)
 63 #define ATAPI_INT_ENABLE_ERR            BIT(2)
 64 #define ATAPI_INT_ENABLE_NEND           BIT(1)
 65 #define ATAPI_INT_ENABLE_ACT            BIT(0)
 66 
 67 /* Access control registers for physical layer control register */
 68 #define SATAPHYADDR_REG                 0x200
 69 #define SATAPHYWDATA_REG                0x204
 70 #define SATAPHYACCEN_REG                0x208
 71 #define SATAPHYRESET_REG                0x20C
 72 #define SATAPHYRDATA_REG                0x210
 73 #define SATAPHYACK_REG                  0x214
 74 
 75 /* Physical layer control address command register (SATAPHYADDR) bits */
 76 #define SATAPHYADDR_PHYRATEMODE         BIT(10)
 77 #define SATAPHYADDR_PHYCMD_READ         BIT(9)
 78 #define SATAPHYADDR_PHYCMD_WRITE        BIT(8)
 79 
 80 /* Physical layer control enable register (SATAPHYACCEN) bits */
 81 #define SATAPHYACCEN_PHYLANE            BIT(0)
 82 
 83 /* Physical layer control reset register (SATAPHYRESET) bits */
 84 #define SATAPHYRESET_PHYRST             BIT(1)
 85 #define SATAPHYRESET_PHYSRES            BIT(0)
 86 
 87 /* Physical layer control acknowledge register (SATAPHYACK) bits */
 88 #define SATAPHYACK_PHYACK               BIT(0)
 89 
 90 /* Serial-ATA HOST control registers */
 91 #define BISTCONF_REG                    0x102C
 92 #define SDATA_REG                       0x1100
 93 #define SSDEVCON_REG                    0x1204
 94 
 95 #define SCRSSTS_REG                     0x1400
 96 #define SCRSERR_REG                     0x1404
 97 #define SCRSCON_REG                     0x1408
 98 #define SCRSACT_REG                     0x140C
 99 
100 #define SATAINTSTAT_REG                 0x1508
101 #define SATAINTMASK_REG                 0x150C
102 
103 /* SATA INT status register (SATAINTSTAT) bits */
104 #define SATAINTSTAT_SERR                BIT(3)
105 #define SATAINTSTAT_ATA                 BIT(0)
106 
107 /* SATA INT mask register (SATAINTSTAT) bits */
108 #define SATAINTMASK_SERRMSK             BIT(3)
109 #define SATAINTMASK_ERRMSK              BIT(2)
110 #define SATAINTMASK_ERRCRTMSK           BIT(1)
111 #define SATAINTMASK_ATAMSK              BIT(0)
112 
113 #define SATA_RCAR_INT_MASK              (SATAINTMASK_SERRMSK | \
114                                          SATAINTMASK_ATAMSK)
115 
116 /* Physical Layer Control Registers */
117 #define SATAPCTLR1_REG                  0x43
118 #define SATAPCTLR2_REG                  0x52
119 #define SATAPCTLR3_REG                  0x5A
120 #define SATAPCTLR4_REG                  0x60
121 
122 /* Descriptor table word 0 bit (when DTA32M = 1) */
123 #define SATA_RCAR_DTEND                 BIT(0)
124 
125 #define SATA_RCAR_DMA_BOUNDARY          0x1FFFFFFEUL
126 
127 /* Gen2 Physical Layer Control Registers */
128 #define RCAR_GEN2_PHY_CTL1_REG          0x1704
129 #define RCAR_GEN2_PHY_CTL1              0x34180002
130 #define RCAR_GEN2_PHY_CTL1_SS           0xC180  /* Spread Spectrum */
131 
132 #define RCAR_GEN2_PHY_CTL2_REG          0x170C
133 #define RCAR_GEN2_PHY_CTL2              0x00002303
134 
135 #define RCAR_GEN2_PHY_CTL3_REG          0x171C
136 #define RCAR_GEN2_PHY_CTL3              0x000B0194
137 
138 #define RCAR_GEN2_PHY_CTL4_REG          0x1724
139 #define RCAR_GEN2_PHY_CTL4              0x00030994
140 
141 #define RCAR_GEN2_PHY_CTL5_REG          0x1740
142 #define RCAR_GEN2_PHY_CTL5              0x03004001
143 #define RCAR_GEN2_PHY_CTL5_DC           BIT(1)  /* DC connection */
144 #define RCAR_GEN2_PHY_CTL5_TR           BIT(2)  /* Termination Resistor */
145 
146 enum sata_rcar_type {
147         RCAR_GEN1_SATA,
148         RCAR_GEN2_SATA,
149         RCAR_R8A7790_ES1_SATA,
150 };
151 
152 struct sata_rcar_priv {
153         void __iomem *base;
154         struct clk *clk;
155         enum sata_rcar_type type;
156 };
157 
158 static void sata_rcar_gen1_phy_preinit(struct sata_rcar_priv *priv)
159 {
160         void __iomem *base = priv->base;
161 
162         /* idle state */
163         iowrite32(0, base + SATAPHYADDR_REG);
164         /* reset */
165         iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG);
166         udelay(10);
167         /* deassert reset */
168         iowrite32(0, base + SATAPHYRESET_REG);
169 }
170 
171 static void sata_rcar_gen1_phy_write(struct sata_rcar_priv *priv, u16 reg,
172                                      u32 val, int group)
173 {
174         void __iomem *base = priv->base;
175         int timeout;
176 
177         /* deassert reset */
178         iowrite32(0, base + SATAPHYRESET_REG);
179         /* lane 1 */
180         iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG);
181         /* write phy register value */
182         iowrite32(val, base + SATAPHYWDATA_REG);
183         /* set register group */
184         if (group)
185                 reg |= SATAPHYADDR_PHYRATEMODE;
186         /* write command */
187         iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG);
188         /* wait for ack */
189         for (timeout = 0; timeout < 100; timeout++) {
190                 val = ioread32(base + SATAPHYACK_REG);
191                 if (val & SATAPHYACK_PHYACK)
192                         break;
193         }
194         if (timeout >= 100)
195                 pr_err("%s timeout\n", __func__);
196         /* idle state */
197         iowrite32(0, base + SATAPHYADDR_REG);
198 }
199 
200 static void sata_rcar_gen1_phy_init(struct sata_rcar_priv *priv)
201 {
202         sata_rcar_gen1_phy_preinit(priv);
203         sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0);
204         sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1);
205         sata_rcar_gen1_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0);
206         sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0);
207         sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1);
208         sata_rcar_gen1_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0);
209 }
210 
211 static void sata_rcar_gen2_phy_init(struct sata_rcar_priv *priv)
212 {
213         void __iomem *base = priv->base;
214 
215         iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG);
216         iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG);
217         iowrite32(RCAR_GEN2_PHY_CTL3, base + RCAR_GEN2_PHY_CTL3_REG);
218         iowrite32(RCAR_GEN2_PHY_CTL4, base + RCAR_GEN2_PHY_CTL4_REG);
219         iowrite32(RCAR_GEN2_PHY_CTL5 | RCAR_GEN2_PHY_CTL5_DC |
220                   RCAR_GEN2_PHY_CTL5_TR, base + RCAR_GEN2_PHY_CTL5_REG);
221 }
222 
223 static void sata_rcar_freeze(struct ata_port *ap)
224 {
225         struct sata_rcar_priv *priv = ap->host->private_data;
226 
227         /* mask */
228         iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
229 
230         ata_sff_freeze(ap);
231 }
232 
233 static void sata_rcar_thaw(struct ata_port *ap)
234 {
235         struct sata_rcar_priv *priv = ap->host->private_data;
236         void __iomem *base = priv->base;
237 
238         /* ack */
239         iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG);
240 
241         ata_sff_thaw(ap);
242 
243         /* unmask */
244         iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG);
245 }
246 
247 static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count)
248 {
249         u16 *ptr = buffer;
250 
251         while (count--) {
252                 u16 data = ioread32(reg);
253 
254                 *ptr++ = data;
255         }
256 }
257 
258 static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count)
259 {
260         const u16 *ptr = buffer;
261 
262         while (count--)
263                 iowrite32(*ptr++, reg);
264 }
265 
266 static u8 sata_rcar_check_status(struct ata_port *ap)
267 {
268         return ioread32(ap->ioaddr.status_addr);
269 }
270 
271 static u8 sata_rcar_check_altstatus(struct ata_port *ap)
272 {
273         return ioread32(ap->ioaddr.altstatus_addr);
274 }
275 
276 static void sata_rcar_set_devctl(struct ata_port *ap, u8 ctl)
277 {
278         iowrite32(ctl, ap->ioaddr.ctl_addr);
279 }
280 
281 static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device)
282 {
283         iowrite32(ATA_DEVICE_OBS, ap->ioaddr.device_addr);
284         ata_sff_pause(ap);      /* needed; also flushes, for mmio */
285 }
286 
287 static unsigned int sata_rcar_ata_devchk(struct ata_port *ap,
288                                          unsigned int device)
289 {
290         struct ata_ioports *ioaddr = &ap->ioaddr;
291         u8 nsect, lbal;
292 
293         sata_rcar_dev_select(ap, device);
294 
295         iowrite32(0x55, ioaddr->nsect_addr);
296         iowrite32(0xaa, ioaddr->lbal_addr);
297 
298         iowrite32(0xaa, ioaddr->nsect_addr);
299         iowrite32(0x55, ioaddr->lbal_addr);
300 
301         iowrite32(0x55, ioaddr->nsect_addr);
302         iowrite32(0xaa, ioaddr->lbal_addr);
303 
304         nsect = ioread32(ioaddr->nsect_addr);
305         lbal  = ioread32(ioaddr->lbal_addr);
306 
307         if (nsect == 0x55 && lbal == 0xaa)
308                 return 1;       /* found a device */
309 
310         return 0;               /* nothing found */
311 }
312 
313 static int sata_rcar_wait_after_reset(struct ata_link *link,
314                                       unsigned long deadline)
315 {
316         struct ata_port *ap = link->ap;
317 
318         ata_msleep(ap, ATA_WAIT_AFTER_RESET);
319 
320         return ata_sff_wait_ready(link, deadline);
321 }
322 
323 static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline)
324 {
325         struct ata_ioports *ioaddr = &ap->ioaddr;
326 
327         DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
328 
329         /* software reset.  causes dev0 to be selected */
330         iowrite32(ap->ctl, ioaddr->ctl_addr);
331         udelay(20);
332         iowrite32(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
333         udelay(20);
334         iowrite32(ap->ctl, ioaddr->ctl_addr);
335         ap->last_ctl = ap->ctl;
336 
337         /* wait the port to become ready */
338         return sata_rcar_wait_after_reset(&ap->link, deadline);
339 }
340 
341 static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes,
342                                unsigned long deadline)
343 {
344         struct ata_port *ap = link->ap;
345         unsigned int devmask = 0;
346         int rc;
347         u8 err;
348 
349         /* determine if device 0 is present */
350         if (sata_rcar_ata_devchk(ap, 0))
351                 devmask |= 1 << 0;
352 
353         /* issue bus reset */
354         DPRINTK("about to softreset, devmask=%x\n", devmask);
355         rc = sata_rcar_bus_softreset(ap, deadline);
356         /* if link is occupied, -ENODEV too is an error */
357         if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
358                 ata_link_err(link, "SRST failed (errno=%d)\n", rc);
359                 return rc;
360         }
361 
362         /* determine by signature whether we have ATA or ATAPI devices */
363         classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err);
364 
365         DPRINTK("classes[0]=%u\n", classes[0]);
366         return 0;
367 }
368 
369 static void sata_rcar_tf_load(struct ata_port *ap,
370                               const struct ata_taskfile *tf)
371 {
372         struct ata_ioports *ioaddr = &ap->ioaddr;
373         unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
374 
375         if (tf->ctl != ap->last_ctl) {
376                 iowrite32(tf->ctl, ioaddr->ctl_addr);
377                 ap->last_ctl = tf->ctl;
378                 ata_wait_idle(ap);
379         }
380 
381         if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
382                 iowrite32(tf->hob_feature, ioaddr->feature_addr);
383                 iowrite32(tf->hob_nsect, ioaddr->nsect_addr);
384                 iowrite32(tf->hob_lbal, ioaddr->lbal_addr);
385                 iowrite32(tf->hob_lbam, ioaddr->lbam_addr);
386                 iowrite32(tf->hob_lbah, ioaddr->lbah_addr);
387                 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
388                         tf->hob_feature,
389                         tf->hob_nsect,
390                         tf->hob_lbal,
391                         tf->hob_lbam,
392                         tf->hob_lbah);
393         }
394 
395         if (is_addr) {
396                 iowrite32(tf->feature, ioaddr->feature_addr);
397                 iowrite32(tf->nsect, ioaddr->nsect_addr);
398                 iowrite32(tf->lbal, ioaddr->lbal_addr);
399                 iowrite32(tf->lbam, ioaddr->lbam_addr);
400                 iowrite32(tf->lbah, ioaddr->lbah_addr);
401                 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
402                         tf->feature,
403                         tf->nsect,
404                         tf->lbal,
405                         tf->lbam,
406                         tf->lbah);
407         }
408 
409         if (tf->flags & ATA_TFLAG_DEVICE) {
410                 iowrite32(tf->device, ioaddr->device_addr);
411                 VPRINTK("device 0x%X\n", tf->device);
412         }
413 
414         ata_wait_idle(ap);
415 }
416 
417 static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
418 {
419         struct ata_ioports *ioaddr = &ap->ioaddr;
420 
421         tf->command = sata_rcar_check_status(ap);
422         tf->feature = ioread32(ioaddr->error_addr);
423         tf->nsect = ioread32(ioaddr->nsect_addr);
424         tf->lbal = ioread32(ioaddr->lbal_addr);
425         tf->lbam = ioread32(ioaddr->lbam_addr);
426         tf->lbah = ioread32(ioaddr->lbah_addr);
427         tf->device = ioread32(ioaddr->device_addr);
428 
429         if (tf->flags & ATA_TFLAG_LBA48) {
430                 iowrite32(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
431                 tf->hob_feature = ioread32(ioaddr->error_addr);
432                 tf->hob_nsect = ioread32(ioaddr->nsect_addr);
433                 tf->hob_lbal = ioread32(ioaddr->lbal_addr);
434                 tf->hob_lbam = ioread32(ioaddr->lbam_addr);
435                 tf->hob_lbah = ioread32(ioaddr->lbah_addr);
436                 iowrite32(tf->ctl, ioaddr->ctl_addr);
437                 ap->last_ctl = tf->ctl;
438         }
439 }
440 
441 static void sata_rcar_exec_command(struct ata_port *ap,
442                                    const struct ata_taskfile *tf)
443 {
444         DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
445 
446         iowrite32(tf->command, ap->ioaddr.command_addr);
447         ata_sff_pause(ap);
448 }
449 
450 static unsigned int sata_rcar_data_xfer(struct ata_device *dev,
451                                               unsigned char *buf,
452                                               unsigned int buflen, int rw)
453 {
454         struct ata_port *ap = dev->link->ap;
455         void __iomem *data_addr = ap->ioaddr.data_addr;
456         unsigned int words = buflen >> 1;
457 
458         /* Transfer multiple of 2 bytes */
459         if (rw == READ)
460                 sata_rcar_ioread16_rep(data_addr, buf, words);
461         else
462                 sata_rcar_iowrite16_rep(data_addr, buf, words);
463 
464         /* Transfer trailing byte, if any. */
465         if (unlikely(buflen & 0x01)) {
466                 unsigned char pad[2] = { };
467 
468                 /* Point buf to the tail of buffer */
469                 buf += buflen - 1;
470 
471                 /*
472                  * Use io*16_rep() accessors here as well to avoid pointlessly
473                  * swapping bytes to and from on the big endian machines...
474                  */
475                 if (rw == READ) {
476                         sata_rcar_ioread16_rep(data_addr, pad, 1);
477                         *buf = pad[0];
478                 } else {
479                         pad[0] = *buf;
480                         sata_rcar_iowrite16_rep(data_addr, pad, 1);
481                 }
482                 words++;
483         }
484 
485         return words << 1;
486 }
487 
488 static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc)
489 {
490         int count;
491         struct ata_port *ap;
492 
493         /* We only need to flush incoming data when a command was running */
494         if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
495                 return;
496 
497         ap = qc->ap;
498         /* Drain up to 64K of data before we give up this recovery method */
499         for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) &&
500                         count < 65536; count += 2)
501                 ioread32(ap->ioaddr.data_addr);
502 
503         /* Can become DEBUG later */
504         if (count)
505                 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
506 }
507 
508 static int sata_rcar_scr_read(struct ata_link *link, unsigned int sc_reg,
509                               u32 *val)
510 {
511         if (sc_reg > SCR_ACTIVE)
512                 return -EINVAL;
513 
514         *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2));
515         return 0;
516 }
517 
518 static int sata_rcar_scr_write(struct ata_link *link, unsigned int sc_reg,
519                                u32 val)
520 {
521         if (sc_reg > SCR_ACTIVE)
522                 return -EINVAL;
523 
524         iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2));
525         return 0;
526 }
527 
528 static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc)
529 {
530         struct ata_port *ap = qc->ap;
531         struct ata_bmdma_prd *prd = ap->bmdma_prd;
532         struct scatterlist *sg;
533         unsigned int si;
534 
535         for_each_sg(qc->sg, sg, qc->n_elem, si) {
536                 u32 addr, sg_len;
537 
538                 /*
539                  * Note: h/w doesn't support 64-bit, so we unconditionally
540                  * truncate dma_addr_t to u32.
541                  */
542                 addr = (u32)sg_dma_address(sg);
543                 sg_len = sg_dma_len(sg);
544 
545                 prd[si].addr = cpu_to_le32(addr);
546                 prd[si].flags_len = cpu_to_le32(sg_len);
547                 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len);
548         }
549 
550         /* end-of-table flag */
551         prd[si - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND);
552 }
553 
554 static void sata_rcar_qc_prep(struct ata_queued_cmd *qc)
555 {
556         if (!(qc->flags & ATA_QCFLAG_DMAMAP))
557                 return;
558 
559         sata_rcar_bmdma_fill_sg(qc);
560 }
561 
562 static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc)
563 {
564         struct ata_port *ap = qc->ap;
565         unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE;
566         struct sata_rcar_priv *priv = ap->host->private_data;
567         void __iomem *base = priv->base;
568         u32 dmactl;
569 
570         /* load PRD table addr. */
571         mb();   /* make sure PRD table writes are visible to controller */
572         iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG);
573 
574         /* specify data direction, triple-check start bit is clear */
575         dmactl = ioread32(base + ATAPI_CONTROL1_REG);
576         dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP);
577         if (dmactl & ATAPI_CONTROL1_START) {
578                 dmactl &= ~ATAPI_CONTROL1_START;
579                 dmactl |= ATAPI_CONTROL1_STOP;
580         }
581         if (!rw)
582                 dmactl |= ATAPI_CONTROL1_RW;
583         iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
584 
585         /* issue r/w command */
586         ap->ops->sff_exec_command(ap, &qc->tf);
587 }
588 
589 static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc)
590 {
591         struct ata_port *ap = qc->ap;
592         struct sata_rcar_priv *priv = ap->host->private_data;
593         void __iomem *base = priv->base;
594         u32 dmactl;
595 
596         /* start host DMA transaction */
597         dmactl = ioread32(base + ATAPI_CONTROL1_REG);
598         dmactl &= ~ATAPI_CONTROL1_STOP;
599         dmactl |= ATAPI_CONTROL1_START;
600         iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
601 }
602 
603 static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc)
604 {
605         struct ata_port *ap = qc->ap;
606         struct sata_rcar_priv *priv = ap->host->private_data;
607         void __iomem *base = priv->base;
608         u32 dmactl;
609 
610         /* force termination of DMA transfer if active */
611         dmactl = ioread32(base + ATAPI_CONTROL1_REG);
612         if (dmactl & ATAPI_CONTROL1_START) {
613                 dmactl &= ~ATAPI_CONTROL1_START;
614                 dmactl |= ATAPI_CONTROL1_STOP;
615                 iowrite32(dmactl, base + ATAPI_CONTROL1_REG);
616         }
617 
618         /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
619         ata_sff_dma_pause(ap);
620 }
621 
622 static u8 sata_rcar_bmdma_status(struct ata_port *ap)
623 {
624         struct sata_rcar_priv *priv = ap->host->private_data;
625         u8 host_stat = 0;
626         u32 status;
627 
628         status = ioread32(priv->base + ATAPI_STATUS_REG);
629         if (status & ATAPI_STATUS_DEVINT)
630                 host_stat |= ATA_DMA_INTR;
631         if (status & ATAPI_STATUS_ACT)
632                 host_stat |= ATA_DMA_ACTIVE;
633 
634         return host_stat;
635 }
636 
637 static struct scsi_host_template sata_rcar_sht = {
638         ATA_BASE_SHT(DRV_NAME),
639         /*
640          * This controller allows transfer chunks up to 512MB which cross 64KB
641          * boundaries, therefore the DMA limits are more relaxed than standard
642          * ATA SFF.
643          */
644         .sg_tablesize           = ATA_MAX_PRD,
645         .dma_boundary           = SATA_RCAR_DMA_BOUNDARY,
646 };
647 
648 static struct ata_port_operations sata_rcar_port_ops = {
649         .inherits               = &ata_bmdma_port_ops,
650 
651         .freeze                 = sata_rcar_freeze,
652         .thaw                   = sata_rcar_thaw,
653         .softreset              = sata_rcar_softreset,
654 
655         .scr_read               = sata_rcar_scr_read,
656         .scr_write              = sata_rcar_scr_write,
657 
658         .sff_dev_select         = sata_rcar_dev_select,
659         .sff_set_devctl         = sata_rcar_set_devctl,
660         .sff_check_status       = sata_rcar_check_status,
661         .sff_check_altstatus    = sata_rcar_check_altstatus,
662         .sff_tf_load            = sata_rcar_tf_load,
663         .sff_tf_read            = sata_rcar_tf_read,
664         .sff_exec_command       = sata_rcar_exec_command,
665         .sff_data_xfer          = sata_rcar_data_xfer,
666         .sff_drain_fifo         = sata_rcar_drain_fifo,
667 
668         .qc_prep                = sata_rcar_qc_prep,
669 
670         .bmdma_setup            = sata_rcar_bmdma_setup,
671         .bmdma_start            = sata_rcar_bmdma_start,
672         .bmdma_stop             = sata_rcar_bmdma_stop,
673         .bmdma_status           = sata_rcar_bmdma_status,
674 };
675 
676 static void sata_rcar_serr_interrupt(struct ata_port *ap)
677 {
678         struct sata_rcar_priv *priv = ap->host->private_data;
679         struct ata_eh_info *ehi = &ap->link.eh_info;
680         int freeze = 0;
681         u32 serror;
682 
683         serror = ioread32(priv->base + SCRSERR_REG);
684         if (!serror)
685                 return;
686 
687         DPRINTK("SError @host_intr: 0x%x\n", serror);
688 
689         /* first, analyze and record host port events */
690         ata_ehi_clear_desc(ehi);
691 
692         if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
693                 /* Setup a soft-reset EH action */
694                 ata_ehi_hotplugged(ehi);
695                 ata_ehi_push_desc(ehi, "%s", "hotplug");
696 
697                 freeze = serror & SERR_COMM_WAKE ? 0 : 1;
698         }
699 
700         /* freeze or abort */
701         if (freeze)
702                 ata_port_freeze(ap);
703         else
704                 ata_port_abort(ap);
705 }
706 
707 static void sata_rcar_ata_interrupt(struct ata_port *ap)
708 {
709         struct ata_queued_cmd *qc;
710         int handled = 0;
711 
712         qc = ata_qc_from_tag(ap, ap->link.active_tag);
713         if (qc)
714                 handled |= ata_bmdma_port_intr(ap, qc);
715 
716         /* be sure to clear ATA interrupt */
717         if (!handled)
718                 sata_rcar_check_status(ap);
719 }
720 
721 static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance)
722 {
723         struct ata_host *host = dev_instance;
724         struct sata_rcar_priv *priv = host->private_data;
725         void __iomem *base = priv->base;
726         unsigned int handled = 0;
727         struct ata_port *ap;
728         u32 sataintstat;
729         unsigned long flags;
730 
731         spin_lock_irqsave(&host->lock, flags);
732 
733         sataintstat = ioread32(base + SATAINTSTAT_REG);
734         sataintstat &= SATA_RCAR_INT_MASK;
735         if (!sataintstat)
736                 goto done;
737         /* ack */
738         iowrite32(~sataintstat & 0x7ff, base + SATAINTSTAT_REG);
739 
740         ap = host->ports[0];
741 
742         if (sataintstat & SATAINTSTAT_ATA)
743                 sata_rcar_ata_interrupt(ap);
744 
745         if (sataintstat & SATAINTSTAT_SERR)
746                 sata_rcar_serr_interrupt(ap);
747 
748         handled = 1;
749 done:
750         spin_unlock_irqrestore(&host->lock, flags);
751 
752         return IRQ_RETVAL(handled);
753 }
754 
755 static void sata_rcar_setup_port(struct ata_host *host)
756 {
757         struct ata_port *ap = host->ports[0];
758         struct ata_ioports *ioaddr = &ap->ioaddr;
759         struct sata_rcar_priv *priv = host->private_data;
760         void __iomem *base = priv->base;
761 
762         ap->ops         = &sata_rcar_port_ops;
763         ap->pio_mask    = ATA_PIO4;
764         ap->udma_mask   = ATA_UDMA6;
765         ap->flags       |= ATA_FLAG_SATA;
766 
767         if (priv->type == RCAR_R8A7790_ES1_SATA)
768                 ap->flags       |= ATA_FLAG_NO_DIPM;
769 
770         ioaddr->cmd_addr = base + SDATA_REG;
771         ioaddr->ctl_addr = base + SSDEVCON_REG;
772         ioaddr->scr_addr = base + SCRSSTS_REG;
773         ioaddr->altstatus_addr = ioaddr->ctl_addr;
774 
775         ioaddr->data_addr       = ioaddr->cmd_addr + (ATA_REG_DATA << 2);
776         ioaddr->error_addr      = ioaddr->cmd_addr + (ATA_REG_ERR << 2);
777         ioaddr->feature_addr    = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2);
778         ioaddr->nsect_addr      = ioaddr->cmd_addr + (ATA_REG_NSECT << 2);
779         ioaddr->lbal_addr       = ioaddr->cmd_addr + (ATA_REG_LBAL << 2);
780         ioaddr->lbam_addr       = ioaddr->cmd_addr + (ATA_REG_LBAM << 2);
781         ioaddr->lbah_addr       = ioaddr->cmd_addr + (ATA_REG_LBAH << 2);
782         ioaddr->device_addr     = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2);
783         ioaddr->status_addr     = ioaddr->cmd_addr + (ATA_REG_STATUS << 2);
784         ioaddr->command_addr    = ioaddr->cmd_addr + (ATA_REG_CMD << 2);
785 }
786 
787 static void sata_rcar_init_controller(struct ata_host *host)
788 {
789         struct sata_rcar_priv *priv = host->private_data;
790         void __iomem *base = priv->base;
791         u32 val;
792 
793         /* reset and setup phy */
794         switch (priv->type) {
795         case RCAR_GEN1_SATA:
796                 sata_rcar_gen1_phy_init(priv);
797                 break;
798         case RCAR_GEN2_SATA:
799         case RCAR_R8A7790_ES1_SATA:
800                 sata_rcar_gen2_phy_init(priv);
801                 break;
802         default:
803                 dev_warn(host->dev, "SATA phy is not initialized\n");
804                 break;
805         }
806 
807         /* SATA-IP reset state */
808         val = ioread32(base + ATAPI_CONTROL1_REG);
809         val |= ATAPI_CONTROL1_RESET;
810         iowrite32(val, base + ATAPI_CONTROL1_REG);
811 
812         /* ISM mode, PRD mode, DTEND flag at bit 0 */
813         val = ioread32(base + ATAPI_CONTROL1_REG);
814         val |= ATAPI_CONTROL1_ISM;
815         val |= ATAPI_CONTROL1_DESE;
816         val |= ATAPI_CONTROL1_DTA32M;
817         iowrite32(val, base + ATAPI_CONTROL1_REG);
818 
819         /* Release the SATA-IP from the reset state */
820         val = ioread32(base + ATAPI_CONTROL1_REG);
821         val &= ~ATAPI_CONTROL1_RESET;
822         iowrite32(val, base + ATAPI_CONTROL1_REG);
823 
824         /* ack and mask */
825         iowrite32(0, base + SATAINTSTAT_REG);
826         iowrite32(0x7ff, base + SATAINTMASK_REG);
827         /* enable interrupts */
828         iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
829 }
830 
831 static struct of_device_id sata_rcar_match[] = {
832         {
833                 /* Deprecated by "renesas,sata-r8a7779" */
834                 .compatible = "renesas,rcar-sata",
835                 .data = (void *)RCAR_GEN1_SATA,
836         },
837         {
838                 .compatible = "renesas,sata-r8a7779",
839                 .data = (void *)RCAR_GEN1_SATA,
840         },
841         {
842                 .compatible = "renesas,sata-r8a7790",
843                 .data = (void *)RCAR_GEN2_SATA
844         },
845         {
846                 .compatible = "renesas,sata-r8a7790-es1",
847                 .data = (void *)RCAR_R8A7790_ES1_SATA
848         },
849         {
850                 .compatible = "renesas,sata-r8a7791",
851                 .data = (void *)RCAR_GEN2_SATA
852         },
853         {
854                 .compatible = "renesas,sata-r8a7793",
855                 .data = (void *)RCAR_GEN2_SATA
856         },
857         { },
858 };
859 MODULE_DEVICE_TABLE(of, sata_rcar_match);
860 
861 static const struct platform_device_id sata_rcar_id_table[] = {
862         { "sata_rcar", RCAR_GEN1_SATA }, /* Deprecated by "sata-r8a7779" */
863         { "sata-r8a7779", RCAR_GEN1_SATA },
864         { "sata-r8a7790", RCAR_GEN2_SATA },
865         { "sata-r8a7790-es1", RCAR_R8A7790_ES1_SATA },
866         { "sata-r8a7791", RCAR_GEN2_SATA },
867         { "sata-r8a7793", RCAR_GEN2_SATA },
868         { },
869 };
870 MODULE_DEVICE_TABLE(platform, sata_rcar_id_table);
871 
872 static int sata_rcar_probe(struct platform_device *pdev)
873 {
874         const struct of_device_id *of_id;
875         struct ata_host *host;
876         struct sata_rcar_priv *priv;
877         struct resource *mem;
878         int irq;
879         int ret = 0;
880 
881         irq = platform_get_irq(pdev, 0);
882         if (irq <= 0)
883                 return -EINVAL;
884 
885         priv = devm_kzalloc(&pdev->dev, sizeof(struct sata_rcar_priv),
886                            GFP_KERNEL);
887         if (!priv)
888                 return -ENOMEM;
889 
890         of_id = of_match_device(sata_rcar_match, &pdev->dev);
891         if (of_id)
892                 priv->type = (enum sata_rcar_type)of_id->data;
893         else
894                 priv->type = platform_get_device_id(pdev)->driver_data;
895 
896         priv->clk = devm_clk_get(&pdev->dev, NULL);
897         if (IS_ERR(priv->clk)) {
898                 dev_err(&pdev->dev, "failed to get access to sata clock\n");
899                 return PTR_ERR(priv->clk);
900         }
901         clk_prepare_enable(priv->clk);
902 
903         host = ata_host_alloc(&pdev->dev, 1);
904         if (!host) {
905                 dev_err(&pdev->dev, "ata_host_alloc failed\n");
906                 ret = -ENOMEM;
907                 goto cleanup;
908         }
909 
910         host->private_data = priv;
911 
912         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
913         priv->base = devm_ioremap_resource(&pdev->dev, mem);
914         if (IS_ERR(priv->base)) {
915                 ret = PTR_ERR(priv->base);
916                 goto cleanup;
917         }
918 
919         /* setup port */
920         sata_rcar_setup_port(host);
921 
922         /* initialize host controller */
923         sata_rcar_init_controller(host);
924 
925         ret = ata_host_activate(host, irq, sata_rcar_interrupt, 0,
926                                 &sata_rcar_sht);
927         if (!ret)
928                 return 0;
929 
930 cleanup:
931         clk_disable_unprepare(priv->clk);
932 
933         return ret;
934 }
935 
936 static int sata_rcar_remove(struct platform_device *pdev)
937 {
938         struct ata_host *host = platform_get_drvdata(pdev);
939         struct sata_rcar_priv *priv = host->private_data;
940         void __iomem *base = priv->base;
941 
942         ata_host_detach(host);
943 
944         /* disable interrupts */
945         iowrite32(0, base + ATAPI_INT_ENABLE_REG);
946         /* ack and mask */
947         iowrite32(0, base + SATAINTSTAT_REG);
948         iowrite32(0x7ff, base + SATAINTMASK_REG);
949 
950         clk_disable_unprepare(priv->clk);
951 
952         return 0;
953 }
954 
955 #ifdef CONFIG_PM_SLEEP
956 static int sata_rcar_suspend(struct device *dev)
957 {
958         struct ata_host *host = dev_get_drvdata(dev);
959         struct sata_rcar_priv *priv = host->private_data;
960         void __iomem *base = priv->base;
961         int ret;
962 
963         ret = ata_host_suspend(host, PMSG_SUSPEND);
964         if (!ret) {
965                 /* disable interrupts */
966                 iowrite32(0, base + ATAPI_INT_ENABLE_REG);
967                 /* mask */
968                 iowrite32(0x7ff, base + SATAINTMASK_REG);
969 
970                 clk_disable_unprepare(priv->clk);
971         }
972 
973         return ret;
974 }
975 
976 static int sata_rcar_resume(struct device *dev)
977 {
978         struct ata_host *host = dev_get_drvdata(dev);
979         struct sata_rcar_priv *priv = host->private_data;
980         void __iomem *base = priv->base;
981 
982         clk_prepare_enable(priv->clk);
983 
984         /* ack and mask */
985         iowrite32(0, base + SATAINTSTAT_REG);
986         iowrite32(0x7ff, base + SATAINTMASK_REG);
987         /* enable interrupts */
988         iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG);
989 
990         ata_host_resume(host);
991 
992         return 0;
993 }
994 
995 static const struct dev_pm_ops sata_rcar_pm_ops = {
996         .suspend        = sata_rcar_suspend,
997         .resume         = sata_rcar_resume,
998 };
999 #endif
1000 
1001 static struct platform_driver sata_rcar_driver = {
1002         .probe          = sata_rcar_probe,
1003         .remove         = sata_rcar_remove,
1004         .id_table       = sata_rcar_id_table,
1005         .driver = {
1006                 .name           = DRV_NAME,
1007                 .owner          = THIS_MODULE,
1008                 .of_match_table = sata_rcar_match,
1009 #ifdef CONFIG_PM_SLEEP
1010                 .pm             = &sata_rcar_pm_ops,
1011 #endif
1012         },
1013 };
1014 
1015 module_platform_driver(sata_rcar_driver);
1016 
1017 MODULE_LICENSE("GPL");
1018 MODULE_AUTHOR("Vladimir Barinov");
1019 MODULE_DESCRIPTION("Renesas R-Car SATA controller low level driver");
1020 

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