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Linux/drivers/ata/sata_promise.c

  1 /*
  2  *  sata_promise.c - Promise SATA
  3  *
  4  *  Maintained by:  Tejun Heo <tj@kernel.org>
  5  *                  Mikael Pettersson
  6  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  7  *                  on emails.
  8  *
  9  *  Copyright 2003-2004 Red Hat, Inc.
 10  *
 11  *
 12  *  This program is free software; you can redistribute it and/or modify
 13  *  it under the terms of the GNU General Public License as published by
 14  *  the Free Software Foundation; either version 2, or (at your option)
 15  *  any later version.
 16  *
 17  *  This program is distributed in the hope that it will be useful,
 18  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 19  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 20  *  GNU General Public License for more details.
 21  *
 22  *  You should have received a copy of the GNU General Public License
 23  *  along with this program; see the file COPYING.  If not, write to
 24  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 25  *
 26  *
 27  *  libata documentation is available via 'make {ps|pdf}docs',
 28  *  as Documentation/DocBook/libata.*
 29  *
 30  *  Hardware information only available under NDA.
 31  *
 32  */
 33 
 34 #include <linux/kernel.h>
 35 #include <linux/module.h>
 36 #include <linux/gfp.h>
 37 #include <linux/pci.h>
 38 #include <linux/init.h>
 39 #include <linux/blkdev.h>
 40 #include <linux/delay.h>
 41 #include <linux/interrupt.h>
 42 #include <linux/device.h>
 43 #include <scsi/scsi.h>
 44 #include <scsi/scsi_host.h>
 45 #include <scsi/scsi_cmnd.h>
 46 #include <linux/libata.h>
 47 #include "sata_promise.h"
 48 
 49 #define DRV_NAME        "sata_promise"
 50 #define DRV_VERSION     "2.12"
 51 
 52 enum {
 53         PDC_MAX_PORTS           = 4,
 54         PDC_MMIO_BAR            = 3,
 55         PDC_MAX_PRD             = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */
 56 
 57         /* host register offsets (from host->iomap[PDC_MMIO_BAR]) */
 58         PDC_INT_SEQMASK         = 0x40, /* Mask of asserted SEQ INTs */
 59         PDC_FLASH_CTL           = 0x44, /* Flash control register */
 60         PDC_PCI_CTL             = 0x48, /* PCI control/status reg */
 61         PDC_SATA_PLUG_CSR       = 0x6C, /* SATA Plug control/status reg */
 62         PDC2_SATA_PLUG_CSR      = 0x60, /* SATAII Plug control/status reg */
 63         PDC_TBG_MODE            = 0x41C, /* TBG mode (not SATAII) */
 64         PDC_SLEW_CTL            = 0x470, /* slew rate control reg (not SATAII) */
 65 
 66         /* per-port ATA register offsets (from ap->ioaddr.cmd_addr) */
 67         PDC_FEATURE             = 0x04, /* Feature/Error reg (per port) */
 68         PDC_SECTOR_COUNT        = 0x08, /* Sector count reg (per port) */
 69         PDC_SECTOR_NUMBER       = 0x0C, /* Sector number reg (per port) */
 70         PDC_CYLINDER_LOW        = 0x10, /* Cylinder low reg (per port) */
 71         PDC_CYLINDER_HIGH       = 0x14, /* Cylinder high reg (per port) */
 72         PDC_DEVICE              = 0x18, /* Device/Head reg (per port) */
 73         PDC_COMMAND             = 0x1C, /* Command/status reg (per port) */
 74         PDC_ALTSTATUS           = 0x38, /* Alternate-status/device-control reg (per port) */
 75         PDC_PKT_SUBMIT          = 0x40, /* Command packet pointer addr */
 76         PDC_GLOBAL_CTL          = 0x48, /* Global control/status (per port) */
 77         PDC_CTLSTAT             = 0x60, /* IDE control and status (per port) */
 78 
 79         /* per-port SATA register offsets (from ap->ioaddr.scr_addr) */
 80         PDC_SATA_ERROR          = 0x04,
 81         PDC_PHYMODE4            = 0x14,
 82         PDC_LINK_LAYER_ERRORS   = 0x6C,
 83         PDC_FPDMA_CTLSTAT       = 0xD8,
 84         PDC_INTERNAL_DEBUG_1    = 0xF8, /* also used for PATA */
 85         PDC_INTERNAL_DEBUG_2    = 0xFC, /* also used for PATA */
 86 
 87         /* PDC_FPDMA_CTLSTAT bit definitions */
 88         PDC_FPDMA_CTLSTAT_RESET                 = 1 << 3,
 89         PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG     = 1 << 10,
 90         PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG        = 1 << 11,
 91 
 92         /* PDC_GLOBAL_CTL bit definitions */
 93         PDC_PH_ERR              = (1 <<  8), /* PCI error while loading packet */
 94         PDC_SH_ERR              = (1 <<  9), /* PCI error while loading S/G table */
 95         PDC_DH_ERR              = (1 << 10), /* PCI error while loading data */
 96         PDC2_HTO_ERR            = (1 << 12), /* host bus timeout */
 97         PDC2_ATA_HBA_ERR        = (1 << 13), /* error during SATA DATA FIS transmission */
 98         PDC2_ATA_DMA_CNT_ERR    = (1 << 14), /* DMA DATA FIS size differs from S/G count */
 99         PDC_OVERRUN_ERR         = (1 << 19), /* S/G byte count larger than HD requires */
100         PDC_UNDERRUN_ERR        = (1 << 20), /* S/G byte count less than HD requires */
101         PDC_DRIVE_ERR           = (1 << 21), /* drive error */
102         PDC_PCI_SYS_ERR         = (1 << 22), /* PCI system error */
103         PDC1_PCI_PARITY_ERR     = (1 << 23), /* PCI parity error (from SATA150 driver) */
104         PDC1_ERR_MASK           = PDC1_PCI_PARITY_ERR,
105         PDC2_ERR_MASK           = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR |
106                                   PDC2_ATA_DMA_CNT_ERR,
107         PDC_ERR_MASK            = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR |
108                                   PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR |
109                                   PDC_DRIVE_ERR | PDC_PCI_SYS_ERR |
110                                   PDC1_ERR_MASK | PDC2_ERR_MASK,
111 
112         board_2037x             = 0,    /* FastTrak S150 TX2plus */
113         board_2037x_pata        = 1,    /* FastTrak S150 TX2plus PATA port */
114         board_20319             = 2,    /* FastTrak S150 TX4 */
115         board_20619             = 3,    /* FastTrak TX4000 */
116         board_2057x             = 4,    /* SATAII150 Tx2plus */
117         board_2057x_pata        = 5,    /* SATAII150 Tx2plus PATA port */
118         board_40518             = 6,    /* SATAII150 Tx4 */
119 
120         PDC_HAS_PATA            = (1 << 1), /* PDC20375/20575 has PATA */
121 
122         /* Sequence counter control registers bit definitions */
123         PDC_SEQCNTRL_INT_MASK   = (1 << 5), /* Sequence Interrupt Mask */
124 
125         /* Feature register values */
126         PDC_FEATURE_ATAPI_PIO   = 0x00, /* ATAPI data xfer by PIO */
127         PDC_FEATURE_ATAPI_DMA   = 0x01, /* ATAPI data xfer by DMA */
128 
129         /* Device/Head register values */
130         PDC_DEVICE_SATA         = 0xE0, /* Device/Head value for SATA devices */
131 
132         /* PDC_CTLSTAT bit definitions */
133         PDC_DMA_ENABLE          = (1 << 7),
134         PDC_IRQ_DISABLE         = (1 << 10),
135         PDC_RESET               = (1 << 11), /* HDMA reset */
136 
137         PDC_COMMON_FLAGS        = ATA_FLAG_PIO_POLLING,
138 
139         /* ap->flags bits */
140         PDC_FLAG_GEN_II         = (1 << 24),
141         PDC_FLAG_SATA_PATA      = (1 << 25), /* supports SATA + PATA */
142         PDC_FLAG_4_PORTS        = (1 << 26), /* 4 ports */
143 };
144 
145 struct pdc_port_priv {
146         u8                      *pkt;
147         dma_addr_t              pkt_dma;
148 };
149 
150 struct pdc_host_priv {
151         spinlock_t hard_reset_lock;
152 };
153 
154 static int pdc_sata_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
155 static int pdc_sata_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
156 static int pdc_ata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
157 static int pdc_common_port_start(struct ata_port *ap);
158 static int pdc_sata_port_start(struct ata_port *ap);
159 static void pdc_qc_prep(struct ata_queued_cmd *qc);
160 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
161 static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
162 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
163 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc);
164 static void pdc_irq_clear(struct ata_port *ap);
165 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc);
166 static void pdc_freeze(struct ata_port *ap);
167 static void pdc_sata_freeze(struct ata_port *ap);
168 static void pdc_thaw(struct ata_port *ap);
169 static void pdc_sata_thaw(struct ata_port *ap);
170 static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
171                               unsigned long deadline);
172 static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
173                               unsigned long deadline);
174 static void pdc_error_handler(struct ata_port *ap);
175 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
176 static int pdc_pata_cable_detect(struct ata_port *ap);
177 static int pdc_sata_cable_detect(struct ata_port *ap);
178 
179 static struct scsi_host_template pdc_ata_sht = {
180         ATA_BASE_SHT(DRV_NAME),
181         .sg_tablesize           = PDC_MAX_PRD,
182         .dma_boundary           = ATA_DMA_BOUNDARY,
183 };
184 
185 static const struct ata_port_operations pdc_common_ops = {
186         .inherits               = &ata_sff_port_ops,
187 
188         .sff_tf_load            = pdc_tf_load_mmio,
189         .sff_exec_command       = pdc_exec_command_mmio,
190         .check_atapi_dma        = pdc_check_atapi_dma,
191         .qc_prep                = pdc_qc_prep,
192         .qc_issue               = pdc_qc_issue,
193 
194         .sff_irq_clear          = pdc_irq_clear,
195         .lost_interrupt         = ATA_OP_NULL,
196 
197         .post_internal_cmd      = pdc_post_internal_cmd,
198         .error_handler          = pdc_error_handler,
199 };
200 
201 static struct ata_port_operations pdc_sata_ops = {
202         .inherits               = &pdc_common_ops,
203         .cable_detect           = pdc_sata_cable_detect,
204         .freeze                 = pdc_sata_freeze,
205         .thaw                   = pdc_sata_thaw,
206         .scr_read               = pdc_sata_scr_read,
207         .scr_write              = pdc_sata_scr_write,
208         .port_start             = pdc_sata_port_start,
209         .hardreset              = pdc_sata_hardreset,
210 };
211 
212 /* First-generation chips need a more restrictive ->check_atapi_dma op,
213    and ->freeze/thaw that ignore the hotplug controls. */
214 static struct ata_port_operations pdc_old_sata_ops = {
215         .inherits               = &pdc_sata_ops,
216         .freeze                 = pdc_freeze,
217         .thaw                   = pdc_thaw,
218         .check_atapi_dma        = pdc_old_sata_check_atapi_dma,
219 };
220 
221 static struct ata_port_operations pdc_pata_ops = {
222         .inherits               = &pdc_common_ops,
223         .cable_detect           = pdc_pata_cable_detect,
224         .freeze                 = pdc_freeze,
225         .thaw                   = pdc_thaw,
226         .port_start             = pdc_common_port_start,
227         .softreset              = pdc_pata_softreset,
228 };
229 
230 static const struct ata_port_info pdc_port_info[] = {
231         [board_2037x] =
232         {
233                 .flags          = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
234                                   PDC_FLAG_SATA_PATA,
235                 .pio_mask       = ATA_PIO4,
236                 .mwdma_mask     = ATA_MWDMA2,
237                 .udma_mask      = ATA_UDMA6,
238                 .port_ops       = &pdc_old_sata_ops,
239         },
240 
241         [board_2037x_pata] =
242         {
243                 .flags          = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS,
244                 .pio_mask       = ATA_PIO4,
245                 .mwdma_mask     = ATA_MWDMA2,
246                 .udma_mask      = ATA_UDMA6,
247                 .port_ops       = &pdc_pata_ops,
248         },
249 
250         [board_20319] =
251         {
252                 .flags          = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
253                                   PDC_FLAG_4_PORTS,
254                 .pio_mask       = ATA_PIO4,
255                 .mwdma_mask     = ATA_MWDMA2,
256                 .udma_mask      = ATA_UDMA6,
257                 .port_ops       = &pdc_old_sata_ops,
258         },
259 
260         [board_20619] =
261         {
262                 .flags          = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
263                                   PDC_FLAG_4_PORTS,
264                 .pio_mask       = ATA_PIO4,
265                 .mwdma_mask     = ATA_MWDMA2,
266                 .udma_mask      = ATA_UDMA6,
267                 .port_ops       = &pdc_pata_ops,
268         },
269 
270         [board_2057x] =
271         {
272                 .flags          = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
273                                   PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA,
274                 .pio_mask       = ATA_PIO4,
275                 .mwdma_mask     = ATA_MWDMA2,
276                 .udma_mask      = ATA_UDMA6,
277                 .port_ops       = &pdc_sata_ops,
278         },
279 
280         [board_2057x_pata] =
281         {
282                 .flags          = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS |
283                                   PDC_FLAG_GEN_II,
284                 .pio_mask       = ATA_PIO4,
285                 .mwdma_mask     = ATA_MWDMA2,
286                 .udma_mask      = ATA_UDMA6,
287                 .port_ops       = &pdc_pata_ops,
288         },
289 
290         [board_40518] =
291         {
292                 .flags          = PDC_COMMON_FLAGS | ATA_FLAG_SATA |
293                                   PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS,
294                 .pio_mask       = ATA_PIO4,
295                 .mwdma_mask     = ATA_MWDMA2,
296                 .udma_mask      = ATA_UDMA6,
297                 .port_ops       = &pdc_sata_ops,
298         },
299 };
300 
301 static const struct pci_device_id pdc_ata_pci_tbl[] = {
302         { PCI_VDEVICE(PROMISE, 0x3371), board_2037x },
303         { PCI_VDEVICE(PROMISE, 0x3373), board_2037x },
304         { PCI_VDEVICE(PROMISE, 0x3375), board_2037x },
305         { PCI_VDEVICE(PROMISE, 0x3376), board_2037x },
306         { PCI_VDEVICE(PROMISE, 0x3570), board_2057x },
307         { PCI_VDEVICE(PROMISE, 0x3571), board_2057x },
308         { PCI_VDEVICE(PROMISE, 0x3574), board_2057x },
309         { PCI_VDEVICE(PROMISE, 0x3577), board_2057x },
310         { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x },
311         { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x },
312 
313         { PCI_VDEVICE(PROMISE, 0x3318), board_20319 },
314         { PCI_VDEVICE(PROMISE, 0x3319), board_20319 },
315         { PCI_VDEVICE(PROMISE, 0x3515), board_40518 },
316         { PCI_VDEVICE(PROMISE, 0x3519), board_40518 },
317         { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 },
318         { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 },
319 
320         { PCI_VDEVICE(PROMISE, 0x6629), board_20619 },
321 
322         { }     /* terminate list */
323 };
324 
325 static struct pci_driver pdc_ata_pci_driver = {
326         .name                   = DRV_NAME,
327         .id_table               = pdc_ata_pci_tbl,
328         .probe                  = pdc_ata_init_one,
329         .remove                 = ata_pci_remove_one,
330 };
331 
332 static int pdc_common_port_start(struct ata_port *ap)
333 {
334         struct device *dev = ap->host->dev;
335         struct pdc_port_priv *pp;
336         int rc;
337 
338         /* we use the same prd table as bmdma, allocate it */
339         rc = ata_bmdma_port_start(ap);
340         if (rc)
341                 return rc;
342 
343         pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
344         if (!pp)
345                 return -ENOMEM;
346 
347         pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
348         if (!pp->pkt)
349                 return -ENOMEM;
350 
351         ap->private_data = pp;
352 
353         return 0;
354 }
355 
356 static int pdc_sata_port_start(struct ata_port *ap)
357 {
358         int rc;
359 
360         rc = pdc_common_port_start(ap);
361         if (rc)
362                 return rc;
363 
364         /* fix up PHYMODE4 align timing */
365         if (ap->flags & PDC_FLAG_GEN_II) {
366                 void __iomem *sata_mmio = ap->ioaddr.scr_addr;
367                 unsigned int tmp;
368 
369                 tmp = readl(sata_mmio + PDC_PHYMODE4);
370                 tmp = (tmp & ~3) | 1;   /* set bits 1:0 = 0:1 */
371                 writel(tmp, sata_mmio + PDC_PHYMODE4);
372         }
373 
374         return 0;
375 }
376 
377 static void pdc_fpdma_clear_interrupt_flag(struct ata_port *ap)
378 {
379         void __iomem *sata_mmio = ap->ioaddr.scr_addr;
380         u32 tmp;
381 
382         tmp = readl(sata_mmio + PDC_FPDMA_CTLSTAT);
383         tmp |= PDC_FPDMA_CTLSTAT_DMASETUP_INT_FLAG;
384         tmp |= PDC_FPDMA_CTLSTAT_SETDB_INT_FLAG;
385 
386         /* It's not allowed to write to the entire FPDMA_CTLSTAT register
387            when NCQ is running. So do a byte-sized write to bits 10 and 11. */
388         writeb(tmp >> 8, sata_mmio + PDC_FPDMA_CTLSTAT + 1);
389         readb(sata_mmio + PDC_FPDMA_CTLSTAT + 1); /* flush */
390 }
391 
392 static void pdc_fpdma_reset(struct ata_port *ap)
393 {
394         void __iomem *sata_mmio = ap->ioaddr.scr_addr;
395         u8 tmp;
396 
397         tmp = (u8)readl(sata_mmio + PDC_FPDMA_CTLSTAT);
398         tmp &= 0x7F;
399         tmp |= PDC_FPDMA_CTLSTAT_RESET;
400         writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
401         readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
402         udelay(100);
403         tmp &= ~PDC_FPDMA_CTLSTAT_RESET;
404         writeb(tmp, sata_mmio + PDC_FPDMA_CTLSTAT);
405         readl(sata_mmio + PDC_FPDMA_CTLSTAT); /* flush */
406 
407         pdc_fpdma_clear_interrupt_flag(ap);
408 }
409 
410 static void pdc_not_at_command_packet_phase(struct ata_port *ap)
411 {
412         void __iomem *sata_mmio = ap->ioaddr.scr_addr;
413         unsigned int i;
414         u32 tmp;
415 
416         /* check not at ASIC packet command phase */
417         for (i = 0; i < 100; ++i) {
418                 writel(0, sata_mmio + PDC_INTERNAL_DEBUG_1);
419                 tmp = readl(sata_mmio + PDC_INTERNAL_DEBUG_2);
420                 if ((tmp & 0xF) != 1)
421                         break;
422                 udelay(100);
423         }
424 }
425 
426 static void pdc_clear_internal_debug_record_error_register(struct ata_port *ap)
427 {
428         void __iomem *sata_mmio = ap->ioaddr.scr_addr;
429 
430         writel(0xffffffff, sata_mmio + PDC_SATA_ERROR);
431         writel(0xffff0000, sata_mmio + PDC_LINK_LAYER_ERRORS);
432 }
433 
434 static void pdc_reset_port(struct ata_port *ap)
435 {
436         void __iomem *ata_ctlstat_mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
437         unsigned int i;
438         u32 tmp;
439 
440         if (ap->flags & PDC_FLAG_GEN_II)
441                 pdc_not_at_command_packet_phase(ap);
442 
443         tmp = readl(ata_ctlstat_mmio);
444         tmp |= PDC_RESET;
445         writel(tmp, ata_ctlstat_mmio);
446 
447         for (i = 11; i > 0; i--) {
448                 tmp = readl(ata_ctlstat_mmio);
449                 if (tmp & PDC_RESET)
450                         break;
451 
452                 udelay(100);
453 
454                 tmp |= PDC_RESET;
455                 writel(tmp, ata_ctlstat_mmio);
456         }
457 
458         tmp &= ~PDC_RESET;
459         writel(tmp, ata_ctlstat_mmio);
460         readl(ata_ctlstat_mmio);        /* flush */
461 
462         if (sata_scr_valid(&ap->link) && (ap->flags & PDC_FLAG_GEN_II)) {
463                 pdc_fpdma_reset(ap);
464                 pdc_clear_internal_debug_record_error_register(ap);
465         }
466 }
467 
468 static int pdc_pata_cable_detect(struct ata_port *ap)
469 {
470         u8 tmp;
471         void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
472 
473         tmp = readb(ata_mmio + PDC_CTLSTAT + 3);
474         if (tmp & 0x01)
475                 return ATA_CBL_PATA40;
476         return ATA_CBL_PATA80;
477 }
478 
479 static int pdc_sata_cable_detect(struct ata_port *ap)
480 {
481         return ATA_CBL_SATA;
482 }
483 
484 static int pdc_sata_scr_read(struct ata_link *link,
485                              unsigned int sc_reg, u32 *val)
486 {
487         if (sc_reg > SCR_CONTROL)
488                 return -EINVAL;
489         *val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
490         return 0;
491 }
492 
493 static int pdc_sata_scr_write(struct ata_link *link,
494                               unsigned int sc_reg, u32 val)
495 {
496         if (sc_reg > SCR_CONTROL)
497                 return -EINVAL;
498         writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
499         return 0;
500 }
501 
502 static void pdc_atapi_pkt(struct ata_queued_cmd *qc)
503 {
504         struct ata_port *ap = qc->ap;
505         dma_addr_t sg_table = ap->bmdma_prd_dma;
506         unsigned int cdb_len = qc->dev->cdb_len;
507         u8 *cdb = qc->cdb;
508         struct pdc_port_priv *pp = ap->private_data;
509         u8 *buf = pp->pkt;
510         __le32 *buf32 = (__le32 *) buf;
511         unsigned int dev_sel, feature;
512 
513         /* set control bits (byte 0), zero delay seq id (byte 3),
514          * and seq id (byte 2)
515          */
516         switch (qc->tf.protocol) {
517         case ATAPI_PROT_DMA:
518                 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
519                         buf32[0] = cpu_to_le32(PDC_PKT_READ);
520                 else
521                         buf32[0] = 0;
522                 break;
523         case ATAPI_PROT_NODATA:
524                 buf32[0] = cpu_to_le32(PDC_PKT_NODATA);
525                 break;
526         default:
527                 BUG();
528                 break;
529         }
530         buf32[1] = cpu_to_le32(sg_table);       /* S/G table addr */
531         buf32[2] = 0;                           /* no next-packet */
532 
533         /* select drive */
534         if (sata_scr_valid(&ap->link))
535                 dev_sel = PDC_DEVICE_SATA;
536         else
537                 dev_sel = qc->tf.device;
538 
539         buf[12] = (1 << 5) | ATA_REG_DEVICE;
540         buf[13] = dev_sel;
541         buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY;
542         buf[15] = dev_sel; /* once more, waiting for BSY to clear */
543 
544         buf[16] = (1 << 5) | ATA_REG_NSECT;
545         buf[17] = qc->tf.nsect;
546         buf[18] = (1 << 5) | ATA_REG_LBAL;
547         buf[19] = qc->tf.lbal;
548 
549         /* set feature and byte counter registers */
550         if (qc->tf.protocol != ATAPI_PROT_DMA)
551                 feature = PDC_FEATURE_ATAPI_PIO;
552         else
553                 feature = PDC_FEATURE_ATAPI_DMA;
554 
555         buf[20] = (1 << 5) | ATA_REG_FEATURE;
556         buf[21] = feature;
557         buf[22] = (1 << 5) | ATA_REG_BYTEL;
558         buf[23] = qc->tf.lbam;
559         buf[24] = (1 << 5) | ATA_REG_BYTEH;
560         buf[25] = qc->tf.lbah;
561 
562         /* send ATAPI packet command 0xA0 */
563         buf[26] = (1 << 5) | ATA_REG_CMD;
564         buf[27] = qc->tf.command;
565 
566         /* select drive and check DRQ */
567         buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY;
568         buf[29] = dev_sel;
569 
570         /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */
571         BUG_ON(cdb_len & ~0x1E);
572 
573         /* append the CDB as the final part */
574         buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG;
575         memcpy(buf+31, cdb, cdb_len);
576 }
577 
578 /**
579  *      pdc_fill_sg - Fill PCI IDE PRD table
580  *      @qc: Metadata associated with taskfile to be transferred
581  *
582  *      Fill PCI IDE PRD (scatter-gather) table with segments
583  *      associated with the current disk command.
584  *      Make sure hardware does not choke on it.
585  *
586  *      LOCKING:
587  *      spin_lock_irqsave(host lock)
588  *
589  */
590 static void pdc_fill_sg(struct ata_queued_cmd *qc)
591 {
592         struct ata_port *ap = qc->ap;
593         struct ata_bmdma_prd *prd = ap->bmdma_prd;
594         struct scatterlist *sg;
595         const u32 SG_COUNT_ASIC_BUG = 41*4;
596         unsigned int si, idx;
597         u32 len;
598 
599         if (!(qc->flags & ATA_QCFLAG_DMAMAP))
600                 return;
601 
602         idx = 0;
603         for_each_sg(qc->sg, sg, qc->n_elem, si) {
604                 u32 addr, offset;
605                 u32 sg_len;
606 
607                 /* determine if physical DMA addr spans 64K boundary.
608                  * Note h/w doesn't support 64-bit, so we unconditionally
609                  * truncate dma_addr_t to u32.
610                  */
611                 addr = (u32) sg_dma_address(sg);
612                 sg_len = sg_dma_len(sg);
613 
614                 while (sg_len) {
615                         offset = addr & 0xffff;
616                         len = sg_len;
617                         if ((offset + sg_len) > 0x10000)
618                                 len = 0x10000 - offset;
619 
620                         prd[idx].addr = cpu_to_le32(addr);
621                         prd[idx].flags_len = cpu_to_le32(len & 0xffff);
622                         VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
623 
624                         idx++;
625                         sg_len -= len;
626                         addr += len;
627                 }
628         }
629 
630         len = le32_to_cpu(prd[idx - 1].flags_len);
631 
632         if (len > SG_COUNT_ASIC_BUG) {
633                 u32 addr;
634 
635                 VPRINTK("Splitting last PRD.\n");
636 
637                 addr = le32_to_cpu(prd[idx - 1].addr);
638                 prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG);
639                 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG);
640 
641                 addr = addr + len - SG_COUNT_ASIC_BUG;
642                 len = SG_COUNT_ASIC_BUG;
643                 prd[idx].addr = cpu_to_le32(addr);
644                 prd[idx].flags_len = cpu_to_le32(len);
645                 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len);
646 
647                 idx++;
648         }
649 
650         prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT);
651 }
652 
653 static void pdc_qc_prep(struct ata_queued_cmd *qc)
654 {
655         struct pdc_port_priv *pp = qc->ap->private_data;
656         unsigned int i;
657 
658         VPRINTK("ENTER\n");
659 
660         switch (qc->tf.protocol) {
661         case ATA_PROT_DMA:
662                 pdc_fill_sg(qc);
663                 /*FALLTHROUGH*/
664         case ATA_PROT_NODATA:
665                 i = pdc_pkt_header(&qc->tf, qc->ap->bmdma_prd_dma,
666                                    qc->dev->devno, pp->pkt);
667                 if (qc->tf.flags & ATA_TFLAG_LBA48)
668                         i = pdc_prep_lba48(&qc->tf, pp->pkt, i);
669                 else
670                         i = pdc_prep_lba28(&qc->tf, pp->pkt, i);
671                 pdc_pkt_footer(&qc->tf, pp->pkt, i);
672                 break;
673         case ATAPI_PROT_PIO:
674                 pdc_fill_sg(qc);
675                 break;
676         case ATAPI_PROT_DMA:
677                 pdc_fill_sg(qc);
678                 /*FALLTHROUGH*/
679         case ATAPI_PROT_NODATA:
680                 pdc_atapi_pkt(qc);
681                 break;
682         default:
683                 break;
684         }
685 }
686 
687 static int pdc_is_sataii_tx4(unsigned long flags)
688 {
689         const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS;
690         return (flags & mask) == mask;
691 }
692 
693 static unsigned int pdc_port_no_to_ata_no(unsigned int port_no,
694                                           int is_sataii_tx4)
695 {
696         static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2};
697         return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no;
698 }
699 
700 static unsigned int pdc_sata_nr_ports(const struct ata_port *ap)
701 {
702         return (ap->flags & PDC_FLAG_4_PORTS) ? 4 : 2;
703 }
704 
705 static unsigned int pdc_sata_ata_port_to_ata_no(const struct ata_port *ap)
706 {
707         const struct ata_host *host = ap->host;
708         unsigned int nr_ports = pdc_sata_nr_ports(ap);
709         unsigned int i;
710 
711         for (i = 0; i < nr_ports && host->ports[i] != ap; ++i)
712                 ;
713         BUG_ON(i >= nr_ports);
714         return pdc_port_no_to_ata_no(i, pdc_is_sataii_tx4(ap->flags));
715 }
716 
717 static void pdc_freeze(struct ata_port *ap)
718 {
719         void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
720         u32 tmp;
721 
722         tmp = readl(ata_mmio + PDC_CTLSTAT);
723         tmp |= PDC_IRQ_DISABLE;
724         tmp &= ~PDC_DMA_ENABLE;
725         writel(tmp, ata_mmio + PDC_CTLSTAT);
726         readl(ata_mmio + PDC_CTLSTAT); /* flush */
727 }
728 
729 static void pdc_sata_freeze(struct ata_port *ap)
730 {
731         struct ata_host *host = ap->host;
732         void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
733         unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
734         unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
735         u32 hotplug_status;
736 
737         /* Disable hotplug events on this port.
738          *
739          * Locking:
740          * 1) hotplug register accesses must be serialised via host->lock
741          * 2) ap->lock == &ap->host->lock
742          * 3) ->freeze() and ->thaw() are called with ap->lock held
743          */
744         hotplug_status = readl(host_mmio + hotplug_offset);
745         hotplug_status |= 0x11 << (ata_no + 16);
746         writel(hotplug_status, host_mmio + hotplug_offset);
747         readl(host_mmio + hotplug_offset); /* flush */
748 
749         pdc_freeze(ap);
750 }
751 
752 static void pdc_thaw(struct ata_port *ap)
753 {
754         void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
755         u32 tmp;
756 
757         /* clear IRQ */
758         readl(ata_mmio + PDC_COMMAND);
759 
760         /* turn IRQ back on */
761         tmp = readl(ata_mmio + PDC_CTLSTAT);
762         tmp &= ~PDC_IRQ_DISABLE;
763         writel(tmp, ata_mmio + PDC_CTLSTAT);
764         readl(ata_mmio + PDC_CTLSTAT); /* flush */
765 }
766 
767 static void pdc_sata_thaw(struct ata_port *ap)
768 {
769         struct ata_host *host = ap->host;
770         void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
771         unsigned int hotplug_offset = PDC2_SATA_PLUG_CSR;
772         unsigned int ata_no = pdc_sata_ata_port_to_ata_no(ap);
773         u32 hotplug_status;
774 
775         pdc_thaw(ap);
776 
777         /* Enable hotplug events on this port.
778          * Locking: see pdc_sata_freeze().
779          */
780         hotplug_status = readl(host_mmio + hotplug_offset);
781         hotplug_status |= 0x11 << ata_no;
782         hotplug_status &= ~(0x11 << (ata_no + 16));
783         writel(hotplug_status, host_mmio + hotplug_offset);
784         readl(host_mmio + hotplug_offset); /* flush */
785 }
786 
787 static int pdc_pata_softreset(struct ata_link *link, unsigned int *class,
788                               unsigned long deadline)
789 {
790         pdc_reset_port(link->ap);
791         return ata_sff_softreset(link, class, deadline);
792 }
793 
794 static unsigned int pdc_ata_port_to_ata_no(const struct ata_port *ap)
795 {
796         void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
797         void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
798 
799         /* ata_mmio == host_mmio + 0x200 + ata_no * 0x80 */
800         return (ata_mmio - host_mmio - 0x200) / 0x80;
801 }
802 
803 static void pdc_hard_reset_port(struct ata_port *ap)
804 {
805         void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
806         void __iomem *pcictl_b1_mmio = host_mmio + PDC_PCI_CTL + 1;
807         unsigned int ata_no = pdc_ata_port_to_ata_no(ap);
808         struct pdc_host_priv *hpriv = ap->host->private_data;
809         u8 tmp;
810 
811         spin_lock(&hpriv->hard_reset_lock);
812 
813         tmp = readb(pcictl_b1_mmio);
814         tmp &= ~(0x10 << ata_no);
815         writeb(tmp, pcictl_b1_mmio);
816         readb(pcictl_b1_mmio); /* flush */
817         udelay(100);
818         tmp |= (0x10 << ata_no);
819         writeb(tmp, pcictl_b1_mmio);
820         readb(pcictl_b1_mmio); /* flush */
821 
822         spin_unlock(&hpriv->hard_reset_lock);
823 }
824 
825 static int pdc_sata_hardreset(struct ata_link *link, unsigned int *class,
826                               unsigned long deadline)
827 {
828         if (link->ap->flags & PDC_FLAG_GEN_II)
829                 pdc_not_at_command_packet_phase(link->ap);
830         /* hotplug IRQs should have been masked by pdc_sata_freeze() */
831         pdc_hard_reset_port(link->ap);
832         pdc_reset_port(link->ap);
833 
834         /* sata_promise can't reliably acquire the first D2H Reg FIS
835          * after hardreset.  Do non-waiting hardreset and request
836          * follow-up SRST.
837          */
838         return sata_std_hardreset(link, class, deadline);
839 }
840 
841 static void pdc_error_handler(struct ata_port *ap)
842 {
843         if (!(ap->pflags & ATA_PFLAG_FROZEN))
844                 pdc_reset_port(ap);
845 
846         ata_sff_error_handler(ap);
847 }
848 
849 static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
850 {
851         struct ata_port *ap = qc->ap;
852 
853         /* make DMA engine forget about the failed command */
854         if (qc->flags & ATA_QCFLAG_FAILED)
855                 pdc_reset_port(ap);
856 }
857 
858 static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc,
859                            u32 port_status, u32 err_mask)
860 {
861         struct ata_eh_info *ehi = &ap->link.eh_info;
862         unsigned int ac_err_mask = 0;
863 
864         ata_ehi_clear_desc(ehi);
865         ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status);
866         port_status &= err_mask;
867 
868         if (port_status & PDC_DRIVE_ERR)
869                 ac_err_mask |= AC_ERR_DEV;
870         if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR))
871                 ac_err_mask |= AC_ERR_OTHER;
872         if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR))
873                 ac_err_mask |= AC_ERR_ATA_BUS;
874         if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR
875                            | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR))
876                 ac_err_mask |= AC_ERR_HOST_BUS;
877 
878         if (sata_scr_valid(&ap->link)) {
879                 u32 serror;
880 
881                 pdc_sata_scr_read(&ap->link, SCR_ERROR, &serror);
882                 ehi->serror |= serror;
883         }
884 
885         qc->err_mask |= ac_err_mask;
886 
887         pdc_reset_port(ap);
888 
889         ata_port_abort(ap);
890 }
891 
892 static unsigned int pdc_host_intr(struct ata_port *ap,
893                                   struct ata_queued_cmd *qc)
894 {
895         unsigned int handled = 0;
896         void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
897         u32 port_status, err_mask;
898 
899         err_mask = PDC_ERR_MASK;
900         if (ap->flags & PDC_FLAG_GEN_II)
901                 err_mask &= ~PDC1_ERR_MASK;
902         else
903                 err_mask &= ~PDC2_ERR_MASK;
904         port_status = readl(ata_mmio + PDC_GLOBAL_CTL);
905         if (unlikely(port_status & err_mask)) {
906                 pdc_error_intr(ap, qc, port_status, err_mask);
907                 return 1;
908         }
909 
910         switch (qc->tf.protocol) {
911         case ATA_PROT_DMA:
912         case ATA_PROT_NODATA:
913         case ATAPI_PROT_DMA:
914         case ATAPI_PROT_NODATA:
915                 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
916                 ata_qc_complete(qc);
917                 handled = 1;
918                 break;
919         default:
920                 ap->stats.idle_irq++;
921                 break;
922         }
923 
924         return handled;
925 }
926 
927 static void pdc_irq_clear(struct ata_port *ap)
928 {
929         void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
930 
931         readl(ata_mmio + PDC_COMMAND);
932 }
933 
934 static irqreturn_t pdc_interrupt(int irq, void *dev_instance)
935 {
936         struct ata_host *host = dev_instance;
937         struct ata_port *ap;
938         u32 mask = 0;
939         unsigned int i, tmp;
940         unsigned int handled = 0;
941         void __iomem *host_mmio;
942         unsigned int hotplug_offset, ata_no;
943         u32 hotplug_status;
944         int is_sataii_tx4;
945 
946         VPRINTK("ENTER\n");
947 
948         if (!host || !host->iomap[PDC_MMIO_BAR]) {
949                 VPRINTK("QUICK EXIT\n");
950                 return IRQ_NONE;
951         }
952 
953         host_mmio = host->iomap[PDC_MMIO_BAR];
954 
955         spin_lock(&host->lock);
956 
957         /* read and clear hotplug flags for all ports */
958         if (host->ports[0]->flags & PDC_FLAG_GEN_II) {
959                 hotplug_offset = PDC2_SATA_PLUG_CSR;
960                 hotplug_status = readl(host_mmio + hotplug_offset);
961                 if (hotplug_status & 0xff)
962                         writel(hotplug_status | 0xff, host_mmio + hotplug_offset);
963                 hotplug_status &= 0xff; /* clear uninteresting bits */
964         } else
965                 hotplug_status = 0;
966 
967         /* reading should also clear interrupts */
968         mask = readl(host_mmio + PDC_INT_SEQMASK);
969 
970         if (mask == 0xffffffff && hotplug_status == 0) {
971                 VPRINTK("QUICK EXIT 2\n");
972                 goto done_irq;
973         }
974 
975         mask &= 0xffff;         /* only 16 SEQIDs possible */
976         if (mask == 0 && hotplug_status == 0) {
977                 VPRINTK("QUICK EXIT 3\n");
978                 goto done_irq;
979         }
980 
981         writel(mask, host_mmio + PDC_INT_SEQMASK);
982 
983         is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags);
984 
985         for (i = 0; i < host->n_ports; i++) {
986                 VPRINTK("port %u\n", i);
987                 ap = host->ports[i];
988 
989                 /* check for a plug or unplug event */
990                 ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
991                 tmp = hotplug_status & (0x11 << ata_no);
992                 if (tmp) {
993                         struct ata_eh_info *ehi = &ap->link.eh_info;
994                         ata_ehi_clear_desc(ehi);
995                         ata_ehi_hotplugged(ehi);
996                         ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp);
997                         ata_port_freeze(ap);
998                         ++handled;
999                         continue;
1000                 }
1001 
1002                 /* check for a packet interrupt */
1003                 tmp = mask & (1 << (i + 1));
1004                 if (tmp) {
1005                         struct ata_queued_cmd *qc;
1006 
1007                         qc = ata_qc_from_tag(ap, ap->link.active_tag);
1008                         if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1009                                 handled += pdc_host_intr(ap, qc);
1010                 }
1011         }
1012 
1013         VPRINTK("EXIT\n");
1014 
1015 done_irq:
1016         spin_unlock(&host->lock);
1017         return IRQ_RETVAL(handled);
1018 }
1019 
1020 static void pdc_packet_start(struct ata_queued_cmd *qc)
1021 {
1022         struct ata_port *ap = qc->ap;
1023         struct pdc_port_priv *pp = ap->private_data;
1024         void __iomem *host_mmio = ap->host->iomap[PDC_MMIO_BAR];
1025         void __iomem *ata_mmio = ap->ioaddr.cmd_addr;
1026         unsigned int port_no = ap->port_no;
1027         u8 seq = (u8) (port_no + 1);
1028 
1029         VPRINTK("ENTER, ap %p\n", ap);
1030 
1031         writel(0x00000001, host_mmio + (seq * 4));
1032         readl(host_mmio + (seq * 4));   /* flush */
1033 
1034         pp->pkt[2] = seq;
1035         wmb();                  /* flush PRD, pkt writes */
1036         writel(pp->pkt_dma, ata_mmio + PDC_PKT_SUBMIT);
1037         readl(ata_mmio + PDC_PKT_SUBMIT); /* flush */
1038 }
1039 
1040 static unsigned int pdc_qc_issue(struct ata_queued_cmd *qc)
1041 {
1042         switch (qc->tf.protocol) {
1043         case ATAPI_PROT_NODATA:
1044                 if (qc->dev->flags & ATA_DFLAG_CDB_INTR)
1045                         break;
1046                 /*FALLTHROUGH*/
1047         case ATA_PROT_NODATA:
1048                 if (qc->tf.flags & ATA_TFLAG_POLLING)
1049                         break;
1050                 /*FALLTHROUGH*/
1051         case ATAPI_PROT_DMA:
1052         case ATA_PROT_DMA:
1053                 pdc_packet_start(qc);
1054                 return 0;
1055         default:
1056                 break;
1057         }
1058         return ata_sff_qc_issue(qc);
1059 }
1060 
1061 static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1062 {
1063         WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
1064         ata_sff_tf_load(ap, tf);
1065 }
1066 
1067 static void pdc_exec_command_mmio(struct ata_port *ap,
1068                                   const struct ata_taskfile *tf)
1069 {
1070         WARN_ON(tf->protocol == ATA_PROT_DMA || tf->protocol == ATAPI_PROT_DMA);
1071         ata_sff_exec_command(ap, tf);
1072 }
1073 
1074 static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
1075 {
1076         u8 *scsicmd = qc->scsicmd->cmnd;
1077         int pio = 1; /* atapi dma off by default */
1078 
1079         /* Whitelist commands that may use DMA. */
1080         switch (scsicmd[0]) {
1081         case WRITE_12:
1082         case WRITE_10:
1083         case WRITE_6:
1084         case READ_12:
1085         case READ_10:
1086         case READ_6:
1087         case 0xad: /* READ_DVD_STRUCTURE */
1088         case 0xbe: /* READ_CD */
1089                 pio = 0;
1090         }
1091         /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
1092         if (scsicmd[0] == WRITE_10) {
1093                 unsigned int lba =
1094                         (scsicmd[2] << 24) |
1095                         (scsicmd[3] << 16) |
1096                         (scsicmd[4] << 8) |
1097                         scsicmd[5];
1098                 if (lba >= 0xFFFF4FA2)
1099                         pio = 1;
1100         }
1101         return pio;
1102 }
1103 
1104 static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc)
1105 {
1106         /* First generation chips cannot use ATAPI DMA on SATA ports */
1107         return 1;
1108 }
1109 
1110 static void pdc_ata_setup_port(struct ata_port *ap,
1111                                void __iomem *base, void __iomem *scr_addr)
1112 {
1113         ap->ioaddr.cmd_addr             = base;
1114         ap->ioaddr.data_addr            = base;
1115         ap->ioaddr.feature_addr         =
1116         ap->ioaddr.error_addr           = base + 0x4;
1117         ap->ioaddr.nsect_addr           = base + 0x8;
1118         ap->ioaddr.lbal_addr            = base + 0xc;
1119         ap->ioaddr.lbam_addr            = base + 0x10;
1120         ap->ioaddr.lbah_addr            = base + 0x14;
1121         ap->ioaddr.device_addr          = base + 0x18;
1122         ap->ioaddr.command_addr         =
1123         ap->ioaddr.status_addr          = base + 0x1c;
1124         ap->ioaddr.altstatus_addr       =
1125         ap->ioaddr.ctl_addr             = base + 0x38;
1126         ap->ioaddr.scr_addr             = scr_addr;
1127 }
1128 
1129 static void pdc_host_init(struct ata_host *host)
1130 {
1131         void __iomem *host_mmio = host->iomap[PDC_MMIO_BAR];
1132         int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II;
1133         int hotplug_offset;
1134         u32 tmp;
1135 
1136         if (is_gen2)
1137                 hotplug_offset = PDC2_SATA_PLUG_CSR;
1138         else
1139                 hotplug_offset = PDC_SATA_PLUG_CSR;
1140 
1141         /*
1142          * Except for the hotplug stuff, this is voodoo from the
1143          * Promise driver.  Label this entire section
1144          * "TODO: figure out why we do this"
1145          */
1146 
1147         /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */
1148         tmp = readl(host_mmio + PDC_FLASH_CTL);
1149         tmp |= 0x02000; /* bit 13 (enable bmr burst) */
1150         if (!is_gen2)
1151                 tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */
1152         writel(tmp, host_mmio + PDC_FLASH_CTL);
1153 
1154         /* clear plug/unplug flags for all ports */
1155         tmp = readl(host_mmio + hotplug_offset);
1156         writel(tmp | 0xff, host_mmio + hotplug_offset);
1157 
1158         tmp = readl(host_mmio + hotplug_offset);
1159         if (is_gen2)    /* unmask plug/unplug ints */
1160                 writel(tmp & ~0xff0000, host_mmio + hotplug_offset);
1161         else            /* mask plug/unplug ints */
1162                 writel(tmp | 0xff0000, host_mmio + hotplug_offset);
1163 
1164         /* don't initialise TBG or SLEW on 2nd generation chips */
1165         if (is_gen2)
1166                 return;
1167 
1168         /* reduce TBG clock to 133 Mhz. */
1169         tmp = readl(host_mmio + PDC_TBG_MODE);
1170         tmp &= ~0x30000; /* clear bit 17, 16*/
1171         tmp |= 0x10000;  /* set bit 17:16 = 0:1 */
1172         writel(tmp, host_mmio + PDC_TBG_MODE);
1173 
1174         readl(host_mmio + PDC_TBG_MODE);        /* flush */
1175         msleep(10);
1176 
1177         /* adjust slew rate control register. */
1178         tmp = readl(host_mmio + PDC_SLEW_CTL);
1179         tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */
1180         tmp  |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */
1181         writel(tmp, host_mmio + PDC_SLEW_CTL);
1182 }
1183 
1184 static int pdc_ata_init_one(struct pci_dev *pdev,
1185                             const struct pci_device_id *ent)
1186 {
1187         const struct ata_port_info *pi = &pdc_port_info[ent->driver_data];
1188         const struct ata_port_info *ppi[PDC_MAX_PORTS];
1189         struct ata_host *host;
1190         struct pdc_host_priv *hpriv;
1191         void __iomem *host_mmio;
1192         int n_ports, i, rc;
1193         int is_sataii_tx4;
1194 
1195         ata_print_version_once(&pdev->dev, DRV_VERSION);
1196 
1197         /* enable and acquire resources */
1198         rc = pcim_enable_device(pdev);
1199         if (rc)
1200                 return rc;
1201 
1202         rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
1203         if (rc == -EBUSY)
1204                 pcim_pin_device(pdev);
1205         if (rc)
1206                 return rc;
1207         host_mmio = pcim_iomap_table(pdev)[PDC_MMIO_BAR];
1208 
1209         /* determine port configuration and setup host */
1210         n_ports = 2;
1211         if (pi->flags & PDC_FLAG_4_PORTS)
1212                 n_ports = 4;
1213         for (i = 0; i < n_ports; i++)
1214                 ppi[i] = pi;
1215 
1216         if (pi->flags & PDC_FLAG_SATA_PATA) {
1217                 u8 tmp = readb(host_mmio + PDC_FLASH_CTL + 1);
1218                 if (!(tmp & 0x80))
1219                         ppi[n_ports++] = pi + 1;
1220         }
1221 
1222         host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1223         if (!host) {
1224                 dev_err(&pdev->dev, "failed to allocate host\n");
1225                 return -ENOMEM;
1226         }
1227         hpriv = devm_kzalloc(&pdev->dev, sizeof *hpriv, GFP_KERNEL);
1228         if (!hpriv)
1229                 return -ENOMEM;
1230         spin_lock_init(&hpriv->hard_reset_lock);
1231         host->private_data = hpriv;
1232         host->iomap = pcim_iomap_table(pdev);
1233 
1234         is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags);
1235         for (i = 0; i < host->n_ports; i++) {
1236                 struct ata_port *ap = host->ports[i];
1237                 unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4);
1238                 unsigned int ata_offset = 0x200 + ata_no * 0x80;
1239                 unsigned int scr_offset = 0x400 + ata_no * 0x100;
1240 
1241                 pdc_ata_setup_port(ap, host_mmio + ata_offset, host_mmio + scr_offset);
1242 
1243                 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1244                 ata_port_pbar_desc(ap, PDC_MMIO_BAR, ata_offset, "ata");
1245         }
1246 
1247         /* initialize adapter */
1248         pdc_host_init(host);
1249 
1250         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1251         if (rc)
1252                 return rc;
1253         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1254         if (rc)
1255                 return rc;
1256 
1257         /* start host, request IRQ and attach */
1258         pci_set_master(pdev);
1259         return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED,
1260                                  &pdc_ata_sht);
1261 }
1262 
1263 module_pci_driver(pdc_ata_pci_driver);
1264 
1265 MODULE_AUTHOR("Jeff Garzik");
1266 MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver");
1267 MODULE_LICENSE("GPL");
1268 MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl);
1269 MODULE_VERSION(DRV_VERSION);
1270 

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