Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/drivers/ata/sata_inic162x.c

  1 /*
  2  * sata_inic162x.c - Driver for Initio 162x SATA controllers
  3  *
  4  * Copyright 2006  SUSE Linux Products GmbH
  5  * Copyright 2006  Tejun Heo <teheo@novell.com>
  6  *
  7  * This file is released under GPL v2.
  8  *
  9  * **** WARNING ****
 10  *
 11  * This driver never worked properly and unfortunately data corruption is
 12  * relatively common.  There isn't anyone working on the driver and there's
 13  * no support from the vendor.  Do not use this driver in any production
 14  * environment.
 15  *
 16  * http://thread.gmane.org/gmane.linux.debian.devel.bugs.rc/378525/focus=54491
 17  * https://bugzilla.kernel.org/show_bug.cgi?id=60565
 18  *
 19  * *****************
 20  *
 21  * This controller is eccentric and easily locks up if something isn't
 22  * right.  Documentation is available at initio's website but it only
 23  * documents registers (not programming model).
 24  *
 25  * This driver has interesting history.  The first version was written
 26  * from the documentation and a 2.4 IDE driver posted on a Taiwan
 27  * company, which didn't use any IDMA features and couldn't handle
 28  * LBA48.  The resulting driver couldn't handle LBA48 devices either
 29  * making it pretty useless.
 30  *
 31  * After a while, initio picked the driver up, renamed it to
 32  * sata_initio162x, updated it to use IDMA for ATA DMA commands and
 33  * posted it on their website.  It only used ATA_PROT_DMA for IDMA and
 34  * attaching both devices and issuing IDMA and !IDMA commands
 35  * simultaneously broke it due to PIRQ masking interaction but it did
 36  * show how to use the IDMA (ADMA + some initio specific twists)
 37  * engine.
 38  *
 39  * Then, I picked up their changes again and here's the usable driver
 40  * which uses IDMA for everything.  Everything works now including
 41  * LBA48, CD/DVD burning, suspend/resume and hotplug.  There are some
 42  * issues tho.  Result Tf is not resported properly, NCQ isn't
 43  * supported yet and CD/DVD writing works with DMA assisted PIO
 44  * protocol (which, for native SATA devices, shouldn't cause any
 45  * noticeable difference).
 46  *
 47  * Anyways, so, here's finally a working driver for inic162x.  Enjoy!
 48  *
 49  * initio: If you guys wanna improve the driver regarding result TF
 50  * access and other stuff, please feel free to contact me.  I'll be
 51  * happy to assist.
 52  */
 53 
 54 #include <linux/gfp.h>
 55 #include <linux/kernel.h>
 56 #include <linux/module.h>
 57 #include <linux/pci.h>
 58 #include <scsi/scsi_host.h>
 59 #include <linux/libata.h>
 60 #include <linux/blkdev.h>
 61 #include <scsi/scsi_device.h>
 62 
 63 #define DRV_NAME        "sata_inic162x"
 64 #define DRV_VERSION     "0.4"
 65 
 66 enum {
 67         MMIO_BAR_PCI            = 5,
 68         MMIO_BAR_CARDBUS        = 1,
 69 
 70         NR_PORTS                = 2,
 71 
 72         IDMA_CPB_TBL_SIZE       = 4 * 32,
 73 
 74         INIC_DMA_BOUNDARY       = 0xffffff,
 75 
 76         HOST_ACTRL              = 0x08,
 77         HOST_CTL                = 0x7c,
 78         HOST_STAT               = 0x7e,
 79         HOST_IRQ_STAT           = 0xbc,
 80         HOST_IRQ_MASK           = 0xbe,
 81 
 82         PORT_SIZE               = 0x40,
 83 
 84         /* registers for ATA TF operation */
 85         PORT_TF_DATA            = 0x00,
 86         PORT_TF_FEATURE         = 0x01,
 87         PORT_TF_NSECT           = 0x02,
 88         PORT_TF_LBAL            = 0x03,
 89         PORT_TF_LBAM            = 0x04,
 90         PORT_TF_LBAH            = 0x05,
 91         PORT_TF_DEVICE          = 0x06,
 92         PORT_TF_COMMAND         = 0x07,
 93         PORT_TF_ALT_STAT        = 0x08,
 94         PORT_IRQ_STAT           = 0x09,
 95         PORT_IRQ_MASK           = 0x0a,
 96         PORT_PRD_CTL            = 0x0b,
 97         PORT_PRD_ADDR           = 0x0c,
 98         PORT_PRD_XFERLEN        = 0x10,
 99         PORT_CPB_CPBLAR         = 0x18,
100         PORT_CPB_PTQFIFO        = 0x1c,
101 
102         /* IDMA register */
103         PORT_IDMA_CTL           = 0x14,
104         PORT_IDMA_STAT          = 0x16,
105 
106         PORT_RPQ_FIFO           = 0x1e,
107         PORT_RPQ_CNT            = 0x1f,
108 
109         PORT_SCR                = 0x20,
110 
111         /* HOST_CTL bits */
112         HCTL_LEDEN              = (1 << 3),  /* enable LED operation */
113         HCTL_IRQOFF             = (1 << 8),  /* global IRQ off */
114         HCTL_FTHD0              = (1 << 10), /* fifo threshold 0 */
115         HCTL_FTHD1              = (1 << 11), /* fifo threshold 1*/
116         HCTL_PWRDWN             = (1 << 12), /* power down PHYs */
117         HCTL_SOFTRST            = (1 << 13), /* global reset (no phy reset) */
118         HCTL_RPGSEL             = (1 << 15), /* register page select */
119 
120         HCTL_KNOWN_BITS         = HCTL_IRQOFF | HCTL_PWRDWN | HCTL_SOFTRST |
121                                   HCTL_RPGSEL,
122 
123         /* HOST_IRQ_(STAT|MASK) bits */
124         HIRQ_PORT0              = (1 << 0),
125         HIRQ_PORT1              = (1 << 1),
126         HIRQ_SOFT               = (1 << 14),
127         HIRQ_GLOBAL             = (1 << 15), /* STAT only */
128 
129         /* PORT_IRQ_(STAT|MASK) bits */
130         PIRQ_OFFLINE            = (1 << 0),  /* device unplugged */
131         PIRQ_ONLINE             = (1 << 1),  /* device plugged */
132         PIRQ_COMPLETE           = (1 << 2),  /* completion interrupt */
133         PIRQ_FATAL              = (1 << 3),  /* fatal error */
134         PIRQ_ATA                = (1 << 4),  /* ATA interrupt */
135         PIRQ_REPLY              = (1 << 5),  /* reply FIFO not empty */
136         PIRQ_PENDING            = (1 << 7),  /* port IRQ pending (STAT only) */
137 
138         PIRQ_ERR                = PIRQ_OFFLINE | PIRQ_ONLINE | PIRQ_FATAL,
139         PIRQ_MASK_DEFAULT       = PIRQ_REPLY | PIRQ_ATA,
140         PIRQ_MASK_FREEZE        = 0xff,
141 
142         /* PORT_PRD_CTL bits */
143         PRD_CTL_START           = (1 << 0),
144         PRD_CTL_WR              = (1 << 3),
145         PRD_CTL_DMAEN           = (1 << 7),  /* DMA enable */
146 
147         /* PORT_IDMA_CTL bits */
148         IDMA_CTL_RST_ATA        = (1 << 2),  /* hardreset ATA bus */
149         IDMA_CTL_RST_IDMA       = (1 << 5),  /* reset IDMA machinary */
150         IDMA_CTL_GO             = (1 << 7),  /* IDMA mode go */
151         IDMA_CTL_ATA_NIEN       = (1 << 8),  /* ATA IRQ disable */
152 
153         /* PORT_IDMA_STAT bits */
154         IDMA_STAT_PERR          = (1 << 0),  /* PCI ERROR MODE */
155         IDMA_STAT_CPBERR        = (1 << 1),  /* ADMA CPB error */
156         IDMA_STAT_LGCY          = (1 << 3),  /* ADMA legacy */
157         IDMA_STAT_UIRQ          = (1 << 4),  /* ADMA unsolicited irq */
158         IDMA_STAT_STPD          = (1 << 5),  /* ADMA stopped */
159         IDMA_STAT_PSD           = (1 << 6),  /* ADMA pause */
160         IDMA_STAT_DONE          = (1 << 7),  /* ADMA done */
161 
162         IDMA_STAT_ERR           = IDMA_STAT_PERR | IDMA_STAT_CPBERR,
163 
164         /* CPB Control Flags*/
165         CPB_CTL_VALID           = (1 << 0),  /* CPB valid */
166         CPB_CTL_QUEUED          = (1 << 1),  /* queued command */
167         CPB_CTL_DATA            = (1 << 2),  /* data, rsvd in datasheet */
168         CPB_CTL_IEN             = (1 << 3),  /* PCI interrupt enable */
169         CPB_CTL_DEVDIR          = (1 << 4),  /* device direction control */
170 
171         /* CPB Response Flags */
172         CPB_RESP_DONE           = (1 << 0),  /* ATA command complete */
173         CPB_RESP_REL            = (1 << 1),  /* ATA release */
174         CPB_RESP_IGNORED        = (1 << 2),  /* CPB ignored */
175         CPB_RESP_ATA_ERR        = (1 << 3),  /* ATA command error */
176         CPB_RESP_SPURIOUS       = (1 << 4),  /* ATA spurious interrupt error */
177         CPB_RESP_UNDERFLOW      = (1 << 5),  /* APRD deficiency length error */
178         CPB_RESP_OVERFLOW       = (1 << 6),  /* APRD exccess length error */
179         CPB_RESP_CPB_ERR        = (1 << 7),  /* CPB error flag */
180 
181         /* PRD Control Flags */
182         PRD_DRAIN               = (1 << 1),  /* ignore data excess */
183         PRD_CDB                 = (1 << 2),  /* atapi packet command pointer */
184         PRD_DIRECT_INTR         = (1 << 3),  /* direct interrupt */
185         PRD_DMA                 = (1 << 4),  /* data transfer method */
186         PRD_WRITE               = (1 << 5),  /* data dir, rsvd in datasheet */
187         PRD_IOM                 = (1 << 6),  /* io/memory transfer */
188         PRD_END                 = (1 << 7),  /* APRD chain end */
189 };
190 
191 /* Comman Parameter Block */
192 struct inic_cpb {
193         u8              resp_flags;     /* Response Flags */
194         u8              error;          /* ATA Error */
195         u8              status;         /* ATA Status */
196         u8              ctl_flags;      /* Control Flags */
197         __le32          len;            /* Total Transfer Length */
198         __le32          prd;            /* First PRD pointer */
199         u8              rsvd[4];
200         /* 16 bytes */
201         u8              feature;        /* ATA Feature */
202         u8              hob_feature;    /* ATA Ex. Feature */
203         u8              device;         /* ATA Device/Head */
204         u8              mirctl;         /* Mirror Control */
205         u8              nsect;          /* ATA Sector Count */
206         u8              hob_nsect;      /* ATA Ex. Sector Count */
207         u8              lbal;           /* ATA Sector Number */
208         u8              hob_lbal;       /* ATA Ex. Sector Number */
209         u8              lbam;           /* ATA Cylinder Low */
210         u8              hob_lbam;       /* ATA Ex. Cylinder Low */
211         u8              lbah;           /* ATA Cylinder High */
212         u8              hob_lbah;       /* ATA Ex. Cylinder High */
213         u8              command;        /* ATA Command */
214         u8              ctl;            /* ATA Control */
215         u8              slave_error;    /* Slave ATA Error */
216         u8              slave_status;   /* Slave ATA Status */
217         /* 32 bytes */
218 } __packed;
219 
220 /* Physical Region Descriptor */
221 struct inic_prd {
222         __le32          mad;            /* Physical Memory Address */
223         __le16          len;            /* Transfer Length */
224         u8              rsvd;
225         u8              flags;          /* Control Flags */
226 } __packed;
227 
228 struct inic_pkt {
229         struct inic_cpb cpb;
230         struct inic_prd prd[LIBATA_MAX_PRD + 1];        /* + 1 for cdb */
231         u8              cdb[ATAPI_CDB_LEN];
232 } __packed;
233 
234 struct inic_host_priv {
235         void __iomem    *mmio_base;
236         u16             cached_hctl;
237 };
238 
239 struct inic_port_priv {
240         struct inic_pkt *pkt;
241         dma_addr_t      pkt_dma;
242         u32             *cpb_tbl;
243         dma_addr_t      cpb_tbl_dma;
244 };
245 
246 static struct scsi_host_template inic_sht = {
247         ATA_BASE_SHT(DRV_NAME),
248         .sg_tablesize   = LIBATA_MAX_PRD,       /* maybe it can be larger? */
249         .dma_boundary   = INIC_DMA_BOUNDARY,
250 };
251 
252 static const int scr_map[] = {
253         [SCR_STATUS]    = 0,
254         [SCR_ERROR]     = 1,
255         [SCR_CONTROL]   = 2,
256 };
257 
258 static void __iomem *inic_port_base(struct ata_port *ap)
259 {
260         struct inic_host_priv *hpriv = ap->host->private_data;
261 
262         return hpriv->mmio_base + ap->port_no * PORT_SIZE;
263 }
264 
265 static void inic_reset_port(void __iomem *port_base)
266 {
267         void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
268 
269         /* stop IDMA engine */
270         readw(idma_ctl); /* flush */
271         msleep(1);
272 
273         /* mask IRQ and assert reset */
274         writew(IDMA_CTL_RST_IDMA, idma_ctl);
275         readw(idma_ctl); /* flush */
276         msleep(1);
277 
278         /* release reset */
279         writew(0, idma_ctl);
280 
281         /* clear irq */
282         writeb(0xff, port_base + PORT_IRQ_STAT);
283 }
284 
285 static int inic_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val)
286 {
287         void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR;
288 
289         if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
290                 return -EINVAL;
291 
292         *val = readl(scr_addr + scr_map[sc_reg] * 4);
293 
294         /* this controller has stuck DIAG.N, ignore it */
295         if (sc_reg == SCR_ERROR)
296                 *val &= ~SERR_PHYRDY_CHG;
297         return 0;
298 }
299 
300 static int inic_scr_write(struct ata_link *link, unsigned sc_reg, u32 val)
301 {
302         void __iomem *scr_addr = inic_port_base(link->ap) + PORT_SCR;
303 
304         if (unlikely(sc_reg >= ARRAY_SIZE(scr_map)))
305                 return -EINVAL;
306 
307         writel(val, scr_addr + scr_map[sc_reg] * 4);
308         return 0;
309 }
310 
311 static void inic_stop_idma(struct ata_port *ap)
312 {
313         void __iomem *port_base = inic_port_base(ap);
314 
315         readb(port_base + PORT_RPQ_FIFO);
316         readb(port_base + PORT_RPQ_CNT);
317         writew(0, port_base + PORT_IDMA_CTL);
318 }
319 
320 static void inic_host_err_intr(struct ata_port *ap, u8 irq_stat, u16 idma_stat)
321 {
322         struct ata_eh_info *ehi = &ap->link.eh_info;
323         struct inic_port_priv *pp = ap->private_data;
324         struct inic_cpb *cpb = &pp->pkt->cpb;
325         bool freeze = false;
326 
327         ata_ehi_clear_desc(ehi);
328         ata_ehi_push_desc(ehi, "irq_stat=0x%x idma_stat=0x%x",
329                           irq_stat, idma_stat);
330 
331         inic_stop_idma(ap);
332 
333         if (irq_stat & (PIRQ_OFFLINE | PIRQ_ONLINE)) {
334                 ata_ehi_push_desc(ehi, "hotplug");
335                 ata_ehi_hotplugged(ehi);
336                 freeze = true;
337         }
338 
339         if (idma_stat & IDMA_STAT_PERR) {
340                 ata_ehi_push_desc(ehi, "PCI error");
341                 freeze = true;
342         }
343 
344         if (idma_stat & IDMA_STAT_CPBERR) {
345                 ata_ehi_push_desc(ehi, "CPB error");
346 
347                 if (cpb->resp_flags & CPB_RESP_IGNORED) {
348                         __ata_ehi_push_desc(ehi, " ignored");
349                         ehi->err_mask |= AC_ERR_INVALID;
350                         freeze = true;
351                 }
352 
353                 if (cpb->resp_flags & CPB_RESP_ATA_ERR)
354                         ehi->err_mask |= AC_ERR_DEV;
355 
356                 if (cpb->resp_flags & CPB_RESP_SPURIOUS) {
357                         __ata_ehi_push_desc(ehi, " spurious-intr");
358                         ehi->err_mask |= AC_ERR_HSM;
359                         freeze = true;
360                 }
361 
362                 if (cpb->resp_flags &
363                     (CPB_RESP_UNDERFLOW | CPB_RESP_OVERFLOW)) {
364                         __ata_ehi_push_desc(ehi, " data-over/underflow");
365                         ehi->err_mask |= AC_ERR_HSM;
366                         freeze = true;
367                 }
368         }
369 
370         if (freeze)
371                 ata_port_freeze(ap);
372         else
373                 ata_port_abort(ap);
374 }
375 
376 static void inic_host_intr(struct ata_port *ap)
377 {
378         void __iomem *port_base = inic_port_base(ap);
379         struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
380         u8 irq_stat;
381         u16 idma_stat;
382 
383         /* read and clear IRQ status */
384         irq_stat = readb(port_base + PORT_IRQ_STAT);
385         writeb(irq_stat, port_base + PORT_IRQ_STAT);
386         idma_stat = readw(port_base + PORT_IDMA_STAT);
387 
388         if (unlikely((irq_stat & PIRQ_ERR) || (idma_stat & IDMA_STAT_ERR)))
389                 inic_host_err_intr(ap, irq_stat, idma_stat);
390 
391         if (unlikely(!qc))
392                 goto spurious;
393 
394         if (likely(idma_stat & IDMA_STAT_DONE)) {
395                 inic_stop_idma(ap);
396 
397                 /* Depending on circumstances, device error
398                  * isn't reported by IDMA, check it explicitly.
399                  */
400                 if (unlikely(readb(port_base + PORT_TF_COMMAND) &
401                              (ATA_DF | ATA_ERR)))
402                         qc->err_mask |= AC_ERR_DEV;
403 
404                 ata_qc_complete(qc);
405                 return;
406         }
407 
408  spurious:
409         ata_port_warn(ap, "unhandled interrupt: cmd=0x%x irq_stat=0x%x idma_stat=0x%x\n",
410                       qc ? qc->tf.command : 0xff, irq_stat, idma_stat);
411 }
412 
413 static irqreturn_t inic_interrupt(int irq, void *dev_instance)
414 {
415         struct ata_host *host = dev_instance;
416         struct inic_host_priv *hpriv = host->private_data;
417         u16 host_irq_stat;
418         int i, handled = 0;
419 
420         host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT);
421 
422         if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
423                 goto out;
424 
425         spin_lock(&host->lock);
426 
427         for (i = 0; i < NR_PORTS; i++)
428                 if (host_irq_stat & (HIRQ_PORT0 << i)) {
429                         inic_host_intr(host->ports[i]);
430                         handled++;
431                 }
432 
433         spin_unlock(&host->lock);
434 
435  out:
436         return IRQ_RETVAL(handled);
437 }
438 
439 static int inic_check_atapi_dma(struct ata_queued_cmd *qc)
440 {
441         /* For some reason ATAPI_PROT_DMA doesn't work for some
442          * commands including writes and other misc ops.  Use PIO
443          * protocol instead, which BTW is driven by the DMA engine
444          * anyway, so it shouldn't make much difference for native
445          * SATA devices.
446          */
447         if (atapi_cmd_type(qc->cdb[0]) == READ)
448                 return 0;
449         return 1;
450 }
451 
452 static void inic_fill_sg(struct inic_prd *prd, struct ata_queued_cmd *qc)
453 {
454         struct scatterlist *sg;
455         unsigned int si;
456         u8 flags = 0;
457 
458         if (qc->tf.flags & ATA_TFLAG_WRITE)
459                 flags |= PRD_WRITE;
460 
461         if (ata_is_dma(qc->tf.protocol))
462                 flags |= PRD_DMA;
463 
464         for_each_sg(qc->sg, sg, qc->n_elem, si) {
465                 prd->mad = cpu_to_le32(sg_dma_address(sg));
466                 prd->len = cpu_to_le16(sg_dma_len(sg));
467                 prd->flags = flags;
468                 prd++;
469         }
470 
471         WARN_ON(!si);
472         prd[-1].flags |= PRD_END;
473 }
474 
475 static void inic_qc_prep(struct ata_queued_cmd *qc)
476 {
477         struct inic_port_priv *pp = qc->ap->private_data;
478         struct inic_pkt *pkt = pp->pkt;
479         struct inic_cpb *cpb = &pkt->cpb;
480         struct inic_prd *prd = pkt->prd;
481         bool is_atapi = ata_is_atapi(qc->tf.protocol);
482         bool is_data = ata_is_data(qc->tf.protocol);
483         unsigned int cdb_len = 0;
484 
485         VPRINTK("ENTER\n");
486 
487         if (is_atapi)
488                 cdb_len = qc->dev->cdb_len;
489 
490         /* prepare packet, based on initio driver */
491         memset(pkt, 0, sizeof(struct inic_pkt));
492 
493         cpb->ctl_flags = CPB_CTL_VALID | CPB_CTL_IEN;
494         if (is_atapi || is_data)
495                 cpb->ctl_flags |= CPB_CTL_DATA;
496 
497         cpb->len = cpu_to_le32(qc->nbytes + cdb_len);
498         cpb->prd = cpu_to_le32(pp->pkt_dma + offsetof(struct inic_pkt, prd));
499 
500         cpb->device = qc->tf.device;
501         cpb->feature = qc->tf.feature;
502         cpb->nsect = qc->tf.nsect;
503         cpb->lbal = qc->tf.lbal;
504         cpb->lbam = qc->tf.lbam;
505         cpb->lbah = qc->tf.lbah;
506 
507         if (qc->tf.flags & ATA_TFLAG_LBA48) {
508                 cpb->hob_feature = qc->tf.hob_feature;
509                 cpb->hob_nsect = qc->tf.hob_nsect;
510                 cpb->hob_lbal = qc->tf.hob_lbal;
511                 cpb->hob_lbam = qc->tf.hob_lbam;
512                 cpb->hob_lbah = qc->tf.hob_lbah;
513         }
514 
515         cpb->command = qc->tf.command;
516         /* don't load ctl - dunno why.  it's like that in the initio driver */
517 
518         /* setup PRD for CDB */
519         if (is_atapi) {
520                 memcpy(pkt->cdb, qc->cdb, ATAPI_CDB_LEN);
521                 prd->mad = cpu_to_le32(pp->pkt_dma +
522                                        offsetof(struct inic_pkt, cdb));
523                 prd->len = cpu_to_le16(cdb_len);
524                 prd->flags = PRD_CDB | PRD_WRITE;
525                 if (!is_data)
526                         prd->flags |= PRD_END;
527                 prd++;
528         }
529 
530         /* setup sg table */
531         if (is_data)
532                 inic_fill_sg(prd, qc);
533 
534         pp->cpb_tbl[0] = pp->pkt_dma;
535 }
536 
537 static unsigned int inic_qc_issue(struct ata_queued_cmd *qc)
538 {
539         struct ata_port *ap = qc->ap;
540         void __iomem *port_base = inic_port_base(ap);
541 
542         /* fire up the ADMA engine */
543         writew(HCTL_FTHD0 | HCTL_LEDEN, port_base + HOST_CTL);
544         writew(IDMA_CTL_GO, port_base + PORT_IDMA_CTL);
545         writeb(0, port_base + PORT_CPB_PTQFIFO);
546 
547         return 0;
548 }
549 
550 static void inic_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
551 {
552         void __iomem *port_base = inic_port_base(ap);
553 
554         tf->feature     = readb(port_base + PORT_TF_FEATURE);
555         tf->nsect       = readb(port_base + PORT_TF_NSECT);
556         tf->lbal        = readb(port_base + PORT_TF_LBAL);
557         tf->lbam        = readb(port_base + PORT_TF_LBAM);
558         tf->lbah        = readb(port_base + PORT_TF_LBAH);
559         tf->device      = readb(port_base + PORT_TF_DEVICE);
560         tf->command     = readb(port_base + PORT_TF_COMMAND);
561 }
562 
563 static bool inic_qc_fill_rtf(struct ata_queued_cmd *qc)
564 {
565         struct ata_taskfile *rtf = &qc->result_tf;
566         struct ata_taskfile tf;
567 
568         /* FIXME: Except for status and error, result TF access
569          * doesn't work.  I tried reading from BAR0/2, CPB and BAR5.
570          * None works regardless of which command interface is used.
571          * For now return true iff status indicates device error.
572          * This means that we're reporting bogus sector for RW
573          * failures.  Eeekk....
574          */
575         inic_tf_read(qc->ap, &tf);
576 
577         if (!(tf.command & ATA_ERR))
578                 return false;
579 
580         rtf->command = tf.command;
581         rtf->feature = tf.feature;
582         return true;
583 }
584 
585 static void inic_freeze(struct ata_port *ap)
586 {
587         void __iomem *port_base = inic_port_base(ap);
588 
589         writeb(PIRQ_MASK_FREEZE, port_base + PORT_IRQ_MASK);
590         writeb(0xff, port_base + PORT_IRQ_STAT);
591 }
592 
593 static void inic_thaw(struct ata_port *ap)
594 {
595         void __iomem *port_base = inic_port_base(ap);
596 
597         writeb(0xff, port_base + PORT_IRQ_STAT);
598         writeb(PIRQ_MASK_DEFAULT, port_base + PORT_IRQ_MASK);
599 }
600 
601 static int inic_check_ready(struct ata_link *link)
602 {
603         void __iomem *port_base = inic_port_base(link->ap);
604 
605         return ata_check_ready(readb(port_base + PORT_TF_COMMAND));
606 }
607 
608 /*
609  * SRST and SControl hardreset don't give valid signature on this
610  * controller.  Only controller specific hardreset mechanism works.
611  */
612 static int inic_hardreset(struct ata_link *link, unsigned int *class,
613                           unsigned long deadline)
614 {
615         struct ata_port *ap = link->ap;
616         void __iomem *port_base = inic_port_base(ap);
617         void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
618         const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
619         int rc;
620 
621         /* hammer it into sane state */
622         inic_reset_port(port_base);
623 
624         writew(IDMA_CTL_RST_ATA, idma_ctl);
625         readw(idma_ctl);        /* flush */
626         ata_msleep(ap, 1);
627         writew(0, idma_ctl);
628 
629         rc = sata_link_resume(link, timing, deadline);
630         if (rc) {
631                 ata_link_warn(link,
632                               "failed to resume link after reset (errno=%d)\n",
633                               rc);
634                 return rc;
635         }
636 
637         *class = ATA_DEV_NONE;
638         if (ata_link_online(link)) {
639                 struct ata_taskfile tf;
640 
641                 /* wait for link to become ready */
642                 rc = ata_wait_after_reset(link, deadline, inic_check_ready);
643                 /* link occupied, -ENODEV too is an error */
644                 if (rc) {
645                         ata_link_warn(link,
646                                       "device not ready after hardreset (errno=%d)\n",
647                                       rc);
648                         return rc;
649                 }
650 
651                 inic_tf_read(ap, &tf);
652                 *class = ata_dev_classify(&tf);
653         }
654 
655         return 0;
656 }
657 
658 static void inic_error_handler(struct ata_port *ap)
659 {
660         void __iomem *port_base = inic_port_base(ap);
661 
662         inic_reset_port(port_base);
663         ata_std_error_handler(ap);
664 }
665 
666 static void inic_post_internal_cmd(struct ata_queued_cmd *qc)
667 {
668         /* make DMA engine forget about the failed command */
669         if (qc->flags & ATA_QCFLAG_FAILED)
670                 inic_reset_port(inic_port_base(qc->ap));
671 }
672 
673 static void init_port(struct ata_port *ap)
674 {
675         void __iomem *port_base = inic_port_base(ap);
676         struct inic_port_priv *pp = ap->private_data;
677 
678         /* clear packet and CPB table */
679         memset(pp->pkt, 0, sizeof(struct inic_pkt));
680         memset(pp->cpb_tbl, 0, IDMA_CPB_TBL_SIZE);
681 
682         /* setup CPB lookup table addresses */
683         writel(pp->cpb_tbl_dma, port_base + PORT_CPB_CPBLAR);
684 }
685 
686 static int inic_port_resume(struct ata_port *ap)
687 {
688         init_port(ap);
689         return 0;
690 }
691 
692 static int inic_port_start(struct ata_port *ap)
693 {
694         struct device *dev = ap->host->dev;
695         struct inic_port_priv *pp;
696 
697         /* alloc and initialize private data */
698         pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
699         if (!pp)
700                 return -ENOMEM;
701         ap->private_data = pp;
702 
703         /* Alloc resources */
704         pp->pkt = dmam_alloc_coherent(dev, sizeof(struct inic_pkt),
705                                       &pp->pkt_dma, GFP_KERNEL);
706         if (!pp->pkt)
707                 return -ENOMEM;
708 
709         pp->cpb_tbl = dmam_alloc_coherent(dev, IDMA_CPB_TBL_SIZE,
710                                           &pp->cpb_tbl_dma, GFP_KERNEL);
711         if (!pp->cpb_tbl)
712                 return -ENOMEM;
713 
714         init_port(ap);
715 
716         return 0;
717 }
718 
719 static struct ata_port_operations inic_port_ops = {
720         .inherits               = &sata_port_ops,
721 
722         .check_atapi_dma        = inic_check_atapi_dma,
723         .qc_prep                = inic_qc_prep,
724         .qc_issue               = inic_qc_issue,
725         .qc_fill_rtf            = inic_qc_fill_rtf,
726 
727         .freeze                 = inic_freeze,
728         .thaw                   = inic_thaw,
729         .hardreset              = inic_hardreset,
730         .error_handler          = inic_error_handler,
731         .post_internal_cmd      = inic_post_internal_cmd,
732 
733         .scr_read               = inic_scr_read,
734         .scr_write              = inic_scr_write,
735 
736         .port_resume            = inic_port_resume,
737         .port_start             = inic_port_start,
738 };
739 
740 static struct ata_port_info inic_port_info = {
741         .flags                  = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
742         .pio_mask               = ATA_PIO4,
743         .mwdma_mask             = ATA_MWDMA2,
744         .udma_mask              = ATA_UDMA6,
745         .port_ops               = &inic_port_ops
746 };
747 
748 static int init_controller(void __iomem *mmio_base, u16 hctl)
749 {
750         int i;
751         u16 val;
752 
753         hctl &= ~HCTL_KNOWN_BITS;
754 
755         /* Soft reset whole controller.  Spec says reset duration is 3
756          * PCI clocks, be generous and give it 10ms.
757          */
758         writew(hctl | HCTL_SOFTRST, mmio_base + HOST_CTL);
759         readw(mmio_base + HOST_CTL); /* flush */
760 
761         for (i = 0; i < 10; i++) {
762                 msleep(1);
763                 val = readw(mmio_base + HOST_CTL);
764                 if (!(val & HCTL_SOFTRST))
765                         break;
766         }
767 
768         if (val & HCTL_SOFTRST)
769                 return -EIO;
770 
771         /* mask all interrupts and reset ports */
772         for (i = 0; i < NR_PORTS; i++) {
773                 void __iomem *port_base = mmio_base + i * PORT_SIZE;
774 
775                 writeb(0xff, port_base + PORT_IRQ_MASK);
776                 inic_reset_port(port_base);
777         }
778 
779         /* port IRQ is masked now, unmask global IRQ */
780         writew(hctl & ~HCTL_IRQOFF, mmio_base + HOST_CTL);
781         val = readw(mmio_base + HOST_IRQ_MASK);
782         val &= ~(HIRQ_PORT0 | HIRQ_PORT1);
783         writew(val, mmio_base + HOST_IRQ_MASK);
784 
785         return 0;
786 }
787 
788 #ifdef CONFIG_PM
789 static int inic_pci_device_resume(struct pci_dev *pdev)
790 {
791         struct ata_host *host = pci_get_drvdata(pdev);
792         struct inic_host_priv *hpriv = host->private_data;
793         int rc;
794 
795         rc = ata_pci_device_do_resume(pdev);
796         if (rc)
797                 return rc;
798 
799         if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
800                 rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
801                 if (rc)
802                         return rc;
803         }
804 
805         ata_host_resume(host);
806 
807         return 0;
808 }
809 #endif
810 
811 static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
812 {
813         const struct ata_port_info *ppi[] = { &inic_port_info, NULL };
814         struct ata_host *host;
815         struct inic_host_priv *hpriv;
816         void __iomem * const *iomap;
817         int mmio_bar;
818         int i, rc;
819 
820         ata_print_version_once(&pdev->dev, DRV_VERSION);
821 
822         dev_alert(&pdev->dev, "inic162x support is broken with common data corruption issues and will be disabled by default, contact linux-ide@vger.kernel.org if in production use\n");
823 
824         /* alloc host */
825         host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS);
826         hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
827         if (!host || !hpriv)
828                 return -ENOMEM;
829 
830         host->private_data = hpriv;
831 
832         /* Acquire resources and fill host.  Note that PCI and cardbus
833          * use different BARs.
834          */
835         rc = pcim_enable_device(pdev);
836         if (rc)
837                 return rc;
838 
839         if (pci_resource_flags(pdev, MMIO_BAR_PCI) & IORESOURCE_MEM)
840                 mmio_bar = MMIO_BAR_PCI;
841         else
842                 mmio_bar = MMIO_BAR_CARDBUS;
843 
844         rc = pcim_iomap_regions(pdev, 1 << mmio_bar, DRV_NAME);
845         if (rc)
846                 return rc;
847         host->iomap = iomap = pcim_iomap_table(pdev);
848         hpriv->mmio_base = iomap[mmio_bar];
849         hpriv->cached_hctl = readw(hpriv->mmio_base + HOST_CTL);
850 
851         for (i = 0; i < NR_PORTS; i++) {
852                 struct ata_port *ap = host->ports[i];
853 
854                 ata_port_pbar_desc(ap, mmio_bar, -1, "mmio");
855                 ata_port_pbar_desc(ap, mmio_bar, i * PORT_SIZE, "port");
856         }
857 
858         /* Set dma_mask.  This devices doesn't support 64bit addressing. */
859         rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
860         if (rc) {
861                 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
862                 return rc;
863         }
864 
865         rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
866         if (rc) {
867                 dev_err(&pdev->dev, "32-bit consistent DMA enable failed\n");
868                 return rc;
869         }
870 
871         /*
872          * This controller is braindamaged.  dma_boundary is 0xffff
873          * like others but it will lock up the whole machine HARD if
874          * 65536 byte PRD entry is fed. Reduce maximum segment size.
875          */
876         rc = pci_set_dma_max_seg_size(pdev, 65536 - 512);
877         if (rc) {
878                 dev_err(&pdev->dev, "failed to set the maximum segment size\n");
879                 return rc;
880         }
881 
882         rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
883         if (rc) {
884                 dev_err(&pdev->dev, "failed to initialize controller\n");
885                 return rc;
886         }
887 
888         pci_set_master(pdev);
889         return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED,
890                                  &inic_sht);
891 }
892 
893 static const struct pci_device_id inic_pci_tbl[] = {
894         { PCI_VDEVICE(INIT, 0x1622), },
895         { },
896 };
897 
898 static struct pci_driver inic_pci_driver = {
899         .name           = DRV_NAME,
900         .id_table       = inic_pci_tbl,
901 #ifdef CONFIG_PM
902         .suspend        = ata_pci_device_suspend,
903         .resume         = inic_pci_device_resume,
904 #endif
905         .probe          = inic_init_one,
906         .remove         = ata_pci_remove_one,
907 };
908 
909 module_pci_driver(inic_pci_driver);
910 
911 MODULE_AUTHOR("Tejun Heo");
912 MODULE_DESCRIPTION("low-level driver for Initio 162x SATA");
913 MODULE_LICENSE("GPL v2");
914 MODULE_DEVICE_TABLE(pci, inic_pci_tbl);
915 MODULE_VERSION(DRV_VERSION);
916 

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