Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/ata/sata_fsl.c

  1 /*
  2  * drivers/ata/sata_fsl.c
  3  *
  4  * Freescale 3.0Gbps SATA device driver
  5  *
  6  * Author: Ashish Kalra <ashish.kalra@freescale.com>
  7  * Li Yang <leoli@freescale.com>
  8  *
  9  * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc.
 10  *
 11  * This program is free software; you can redistribute  it and/or modify it
 12  * under  the terms of  the GNU General  Public License as published by the
 13  * Free Software Foundation;  either version 2 of the  License, or (at your
 14  * option) any later version.
 15  *
 16  */
 17 
 18 #include <linux/kernel.h>
 19 #include <linux/module.h>
 20 #include <linux/platform_device.h>
 21 #include <linux/slab.h>
 22 
 23 #include <scsi/scsi_host.h>
 24 #include <scsi/scsi_cmnd.h>
 25 #include <linux/libata.h>
 26 #include <asm/io.h>
 27 #include <linux/of_address.h>
 28 #include <linux/of_irq.h>
 29 #include <linux/of_platform.h>
 30 
 31 static unsigned int intr_coalescing_count;
 32 module_param(intr_coalescing_count, int, S_IRUGO);
 33 MODULE_PARM_DESC(intr_coalescing_count,
 34                                  "INT coalescing count threshold (1..31)");
 35 
 36 static unsigned int intr_coalescing_ticks;
 37 module_param(intr_coalescing_ticks, int, S_IRUGO);
 38 MODULE_PARM_DESC(intr_coalescing_ticks,
 39                                  "INT coalescing timer threshold in AHB ticks");
 40 /* Controller information */
 41 enum {
 42         SATA_FSL_QUEUE_DEPTH    = 16,
 43         SATA_FSL_MAX_PRD        = 63,
 44         SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
 45         SATA_FSL_MAX_PRD_DIRECT = 16,   /* Direct PRDT entries */
 46 
 47         SATA_FSL_HOST_FLAGS     = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
 48                                 ATA_FLAG_PMP | ATA_FLAG_NCQ | ATA_FLAG_AN),
 49 
 50         SATA_FSL_MAX_CMDS       = SATA_FSL_QUEUE_DEPTH,
 51         SATA_FSL_CMD_HDR_SIZE   = 16,   /* 4 DWORDS */
 52         SATA_FSL_CMD_SLOT_SIZE  = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
 53 
 54         /*
 55          * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
 56          * chained indirect PRDEs up to a max count of 63.
 57          * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
 58          * be setup as an indirect descriptor, pointing to it's next
 59          * (contiguous) PRDE. Though chained indirect PRDE arrays are
 60          * supported,it will be more efficient to use a direct PRDT and
 61          * a single chain/link to indirect PRDE array/PRDT.
 62          */
 63 
 64         SATA_FSL_CMD_DESC_CFIS_SZ       = 32,
 65         SATA_FSL_CMD_DESC_SFIS_SZ       = 32,
 66         SATA_FSL_CMD_DESC_ACMD_SZ       = 16,
 67         SATA_FSL_CMD_DESC_RSRVD         = 16,
 68 
 69         SATA_FSL_CMD_DESC_SIZE  = (SATA_FSL_CMD_DESC_CFIS_SZ +
 70                                  SATA_FSL_CMD_DESC_SFIS_SZ +
 71                                  SATA_FSL_CMD_DESC_ACMD_SZ +
 72                                  SATA_FSL_CMD_DESC_RSRVD +
 73                                  SATA_FSL_MAX_PRD * 16),
 74 
 75         SATA_FSL_CMD_DESC_OFFSET_TO_PRDT        =
 76                                 (SATA_FSL_CMD_DESC_CFIS_SZ +
 77                                  SATA_FSL_CMD_DESC_SFIS_SZ +
 78                                  SATA_FSL_CMD_DESC_ACMD_SZ +
 79                                  SATA_FSL_CMD_DESC_RSRVD),
 80 
 81         SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
 82         SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
 83                                         SATA_FSL_CMD_DESC_AR_SZ),
 84 
 85         /*
 86          * MPC8315 has two SATA controllers, SATA1 & SATA2
 87          * (one port per controller)
 88          * MPC837x has 2/4 controllers, one port per controller
 89          */
 90 
 91         SATA_FSL_MAX_PORTS      = 1,
 92 
 93         SATA_FSL_IRQ_FLAG       = IRQF_SHARED,
 94 };
 95 
 96 /*
 97  * Interrupt Coalescing Control Register bitdefs  */
 98 enum {
 99         ICC_MIN_INT_COUNT_THRESHOLD     = 1,
100         ICC_MAX_INT_COUNT_THRESHOLD     = ((1 << 5) - 1),
101         ICC_MIN_INT_TICKS_THRESHOLD     = 0,
102         ICC_MAX_INT_TICKS_THRESHOLD     = ((1 << 19) - 1),
103         ICC_SAFE_INT_TICKS              = 1,
104 };
105 
106 /*
107 * Host Controller command register set - per port
108 */
109 enum {
110         CQ = 0,
111         CA = 8,
112         CC = 0x10,
113         CE = 0x18,
114         DE = 0x20,
115         CHBA = 0x24,
116         HSTATUS = 0x28,
117         HCONTROL = 0x2C,
118         CQPMP = 0x30,
119         SIGNATURE = 0x34,
120         ICC = 0x38,
121 
122         /*
123          * Host Status Register (HStatus) bitdefs
124          */
125         ONLINE = (1 << 31),
126         GOING_OFFLINE = (1 << 30),
127         BIST_ERR = (1 << 29),
128         CLEAR_ERROR = (1 << 27),
129 
130         FATAL_ERR_HC_MASTER_ERR = (1 << 18),
131         FATAL_ERR_PARITY_ERR_TX = (1 << 17),
132         FATAL_ERR_PARITY_ERR_RX = (1 << 16),
133         FATAL_ERR_DATA_UNDERRUN = (1 << 13),
134         FATAL_ERR_DATA_OVERRUN = (1 << 12),
135         FATAL_ERR_CRC_ERR_TX = (1 << 11),
136         FATAL_ERR_CRC_ERR_RX = (1 << 10),
137         FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
138         FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
139 
140         FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
141             FATAL_ERR_PARITY_ERR_TX |
142             FATAL_ERR_PARITY_ERR_RX |
143             FATAL_ERR_DATA_UNDERRUN |
144             FATAL_ERR_DATA_OVERRUN |
145             FATAL_ERR_CRC_ERR_TX |
146             FATAL_ERR_CRC_ERR_RX |
147             FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
148 
149         INT_ON_DATA_LENGTH_MISMATCH = (1 << 12),
150         INT_ON_FATAL_ERR = (1 << 5),
151         INT_ON_PHYRDY_CHG = (1 << 4),
152 
153         INT_ON_SIGNATURE_UPDATE = (1 << 3),
154         INT_ON_SNOTIFY_UPDATE = (1 << 2),
155         INT_ON_SINGL_DEVICE_ERR = (1 << 1),
156         INT_ON_CMD_COMPLETE = 1,
157 
158         INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE |
159             INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
160 
161         /*
162          * Host Control Register (HControl) bitdefs
163          */
164         HCONTROL_ONLINE_PHY_RST = (1 << 31),
165         HCONTROL_FORCE_OFFLINE = (1 << 30),
166         HCONTROL_LEGACY = (1 << 28),
167         HCONTROL_PARITY_PROT_MOD = (1 << 14),
168         HCONTROL_DPATH_PARITY = (1 << 12),
169         HCONTROL_SNOOP_ENABLE = (1 << 10),
170         HCONTROL_PMP_ATTACHED = (1 << 9),
171         HCONTROL_COPYOUT_STATFIS = (1 << 8),
172         IE_ON_FATAL_ERR = (1 << 5),
173         IE_ON_PHYRDY_CHG = (1 << 4),
174         IE_ON_SIGNATURE_UPDATE = (1 << 3),
175         IE_ON_SNOTIFY_UPDATE = (1 << 2),
176         IE_ON_SINGL_DEVICE_ERR = (1 << 1),
177         IE_ON_CMD_COMPLETE = 1,
178 
179         DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
180             IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE |
181             IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
182 
183         EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
184         DATA_SNOOP_ENABLE_V1 = (1 << 22),
185         DATA_SNOOP_ENABLE_V2 = (1 << 28),
186 };
187 
188 /*
189  * SATA Superset Registers
190  */
191 enum {
192         SSTATUS = 0,
193         SERROR = 4,
194         SCONTROL = 8,
195         SNOTIFY = 0xC,
196 };
197 
198 /*
199  * Control Status Register Set
200  */
201 enum {
202         TRANSCFG = 0,
203         TRANSSTATUS = 4,
204         LINKCFG = 8,
205         LINKCFG1 = 0xC,
206         LINKCFG2 = 0x10,
207         LINKSTATUS = 0x14,
208         LINKSTATUS1 = 0x18,
209         PHYCTRLCFG = 0x1C,
210         COMMANDSTAT = 0x20,
211 };
212 
213 /* TRANSCFG (transport-layer) configuration control */
214 enum {
215         TRANSCFG_RX_WATER_MARK = (1 << 4),
216 };
217 
218 /* PHY (link-layer) configuration control */
219 enum {
220         PHY_BIST_ENABLE = 0x01,
221 };
222 
223 /*
224  * Command Header Table entry, i.e, command slot
225  * 4 Dwords per command slot, command header size ==  64 Dwords.
226  */
227 struct cmdhdr_tbl_entry {
228         u32 cda;
229         u32 prde_fis_len;
230         u32 ttl;
231         u32 desc_info;
232 };
233 
234 /*
235  * Description information bitdefs
236  */
237 enum {
238         CMD_DESC_RES = (1 << 11),
239         VENDOR_SPECIFIC_BIST = (1 << 10),
240         CMD_DESC_SNOOP_ENABLE = (1 << 9),
241         FPDMA_QUEUED_CMD = (1 << 8),
242         SRST_CMD = (1 << 7),
243         BIST = (1 << 6),
244         ATAPI_CMD = (1 << 5),
245 };
246 
247 /*
248  * Command Descriptor
249  */
250 struct command_desc {
251         u8 cfis[8 * 4];
252         u8 sfis[8 * 4];
253         u8 acmd[4 * 4];
254         u8 fill[4 * 4];
255         u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
256         u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
257 };
258 
259 /*
260  * Physical region table descriptor(PRD)
261  */
262 
263 struct prde {
264         u32 dba;
265         u8 fill[2 * 4];
266         u32 ddc_and_ext;
267 };
268 
269 /*
270  * ata_port private data
271  * This is our per-port instance data.
272  */
273 struct sata_fsl_port_priv {
274         struct cmdhdr_tbl_entry *cmdslot;
275         dma_addr_t cmdslot_paddr;
276         struct command_desc *cmdentry;
277         dma_addr_t cmdentry_paddr;
278 };
279 
280 /*
281  * ata_port->host_set private data
282  */
283 struct sata_fsl_host_priv {
284         void __iomem *hcr_base;
285         void __iomem *ssr_base;
286         void __iomem *csr_base;
287         int irq;
288         int data_snoop;
289         struct device_attribute intr_coalescing;
290         struct device_attribute rx_watermark;
291 };
292 
293 static void fsl_sata_set_irq_coalescing(struct ata_host *host,
294                 unsigned int count, unsigned int ticks)
295 {
296         struct sata_fsl_host_priv *host_priv = host->private_data;
297         void __iomem *hcr_base = host_priv->hcr_base;
298         unsigned long flags;
299 
300         if (count > ICC_MAX_INT_COUNT_THRESHOLD)
301                 count = ICC_MAX_INT_COUNT_THRESHOLD;
302         else if (count < ICC_MIN_INT_COUNT_THRESHOLD)
303                 count = ICC_MIN_INT_COUNT_THRESHOLD;
304 
305         if (ticks > ICC_MAX_INT_TICKS_THRESHOLD)
306                 ticks = ICC_MAX_INT_TICKS_THRESHOLD;
307         else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) &&
308                         (count > ICC_MIN_INT_COUNT_THRESHOLD))
309                 ticks = ICC_SAFE_INT_TICKS;
310 
311         spin_lock_irqsave(&host->lock, flags);
312         iowrite32((count << 24 | ticks), hcr_base + ICC);
313 
314         intr_coalescing_count = count;
315         intr_coalescing_ticks = ticks;
316         spin_unlock_irqrestore(&host->lock, flags);
317 
318         DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x\n",
319                         intr_coalescing_count, intr_coalescing_ticks);
320         DPRINTK("ICC register status: (hcr base: 0x%x) = 0x%x\n",
321                         hcr_base, ioread32(hcr_base + ICC));
322 }
323 
324 static ssize_t fsl_sata_intr_coalescing_show(struct device *dev,
325                 struct device_attribute *attr, char *buf)
326 {
327         return sprintf(buf, "%d %d\n",
328                         intr_coalescing_count, intr_coalescing_ticks);
329 }
330 
331 static ssize_t fsl_sata_intr_coalescing_store(struct device *dev,
332                 struct device_attribute *attr,
333                 const char *buf, size_t count)
334 {
335         unsigned int coalescing_count,  coalescing_ticks;
336 
337         if (sscanf(buf, "%d%d",
338                                 &coalescing_count,
339                                 &coalescing_ticks) != 2) {
340                 printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
341                 return -EINVAL;
342         }
343 
344         fsl_sata_set_irq_coalescing(dev_get_drvdata(dev),
345                         coalescing_count, coalescing_ticks);
346 
347         return strlen(buf);
348 }
349 
350 static ssize_t fsl_sata_rx_watermark_show(struct device *dev,
351                 struct device_attribute *attr, char *buf)
352 {
353         unsigned int rx_watermark;
354         unsigned long flags;
355         struct ata_host *host = dev_get_drvdata(dev);
356         struct sata_fsl_host_priv *host_priv = host->private_data;
357         void __iomem *csr_base = host_priv->csr_base;
358 
359         spin_lock_irqsave(&host->lock, flags);
360         rx_watermark = ioread32(csr_base + TRANSCFG);
361         rx_watermark &= 0x1f;
362 
363         spin_unlock_irqrestore(&host->lock, flags);
364         return sprintf(buf, "%d\n", rx_watermark);
365 }
366 
367 static ssize_t fsl_sata_rx_watermark_store(struct device *dev,
368                 struct device_attribute *attr,
369                 const char *buf, size_t count)
370 {
371         unsigned int rx_watermark;
372         unsigned long flags;
373         struct ata_host *host = dev_get_drvdata(dev);
374         struct sata_fsl_host_priv *host_priv = host->private_data;
375         void __iomem *csr_base = host_priv->csr_base;
376         u32 temp;
377 
378         if (sscanf(buf, "%d", &rx_watermark) != 1) {
379                 printk(KERN_ERR "fsl-sata: wrong parameter format.\n");
380                 return -EINVAL;
381         }
382 
383         spin_lock_irqsave(&host->lock, flags);
384         temp = ioread32(csr_base + TRANSCFG);
385         temp &= 0xffffffe0;
386         iowrite32(temp | rx_watermark, csr_base + TRANSCFG);
387 
388         spin_unlock_irqrestore(&host->lock, flags);
389         return strlen(buf);
390 }
391 
392 static inline unsigned int sata_fsl_tag(unsigned int tag,
393                                         void __iomem *hcr_base)
394 {
395         /* We let libATA core do actual (queue) tag allocation */
396 
397         /* all non NCQ/queued commands should have tag#0 */
398         if (ata_tag_internal(tag)) {
399                 DPRINTK("mapping internal cmds to tag#0\n");
400                 return 0;
401         }
402 
403         if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
404                 DPRINTK("tag %d invalid : out of range\n", tag);
405                 return 0;
406         }
407 
408         if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
409                 DPRINTK("tag %d invalid : in use!!\n", tag);
410                 return 0;
411         }
412 
413         return tag;
414 }
415 
416 static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp,
417                                          unsigned int tag, u32 desc_info,
418                                          u32 data_xfer_len, u8 num_prde,
419                                          u8 fis_len)
420 {
421         dma_addr_t cmd_descriptor_address;
422 
423         cmd_descriptor_address = pp->cmdentry_paddr +
424             tag * SATA_FSL_CMD_DESC_SIZE;
425 
426         /* NOTE: both data_xfer_len & fis_len are Dword counts */
427 
428         pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
429         pp->cmdslot[tag].prde_fis_len =
430             cpu_to_le32((num_prde << 16) | (fis_len << 2));
431         pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
432         pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
433 
434         VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
435                 pp->cmdslot[tag].cda,
436                 pp->cmdslot[tag].prde_fis_len,
437                 pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info);
438 
439 }
440 
441 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
442                                      u32 *ttl, dma_addr_t cmd_desc_paddr,
443                                      int data_snoop)
444 {
445         struct scatterlist *sg;
446         unsigned int num_prde = 0;
447         u32 ttl_dwords = 0;
448 
449         /*
450          * NOTE : direct & indirect prdt's are contiguously allocated
451          */
452         struct prde *prd = (struct prde *)&((struct command_desc *)
453                                             cmd_desc)->prdt;
454 
455         struct prde *prd_ptr_to_indirect_ext = NULL;
456         unsigned indirect_ext_segment_sz = 0;
457         dma_addr_t indirect_ext_segment_paddr;
458         unsigned int si;
459 
460         VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd);
461 
462         indirect_ext_segment_paddr = cmd_desc_paddr +
463             SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
464 
465         for_each_sg(qc->sg, sg, qc->n_elem, si) {
466                 dma_addr_t sg_addr = sg_dma_address(sg);
467                 u32 sg_len = sg_dma_len(sg);
468 
469                 VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n",
470                         (unsigned long long)sg_addr, sg_len);
471 
472                 /* warn if each s/g element is not dword aligned */
473                 if (unlikely(sg_addr & 0x03))
474                         ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n",
475                                      (unsigned long long)sg_addr);
476                 if (unlikely(sg_len & 0x03))
477                         ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n",
478                                      sg_len);
479 
480                 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
481                     sg_next(sg) != NULL) {
482                         VPRINTK("setting indirect prde\n");
483                         prd_ptr_to_indirect_ext = prd;
484                         prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
485                         indirect_ext_segment_sz = 0;
486                         ++prd;
487                         ++num_prde;
488                 }
489 
490                 ttl_dwords += sg_len;
491                 prd->dba = cpu_to_le32(sg_addr);
492                 prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03));
493 
494                 VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n",
495                         ttl_dwords, prd->dba, prd->ddc_and_ext);
496 
497                 ++num_prde;
498                 ++prd;
499                 if (prd_ptr_to_indirect_ext)
500                         indirect_ext_segment_sz += sg_len;
501         }
502 
503         if (prd_ptr_to_indirect_ext) {
504                 /* set indirect extension flag along with indirect ext. size */
505                 prd_ptr_to_indirect_ext->ddc_and_ext =
506                     cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
507                                  data_snoop |
508                                  (indirect_ext_segment_sz & ~0x03)));
509         }
510 
511         *ttl = ttl_dwords;
512         return num_prde;
513 }
514 
515 static void sata_fsl_qc_prep(struct ata_queued_cmd *qc)
516 {
517         struct ata_port *ap = qc->ap;
518         struct sata_fsl_port_priv *pp = ap->private_data;
519         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
520         void __iomem *hcr_base = host_priv->hcr_base;
521         unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
522         struct command_desc *cd;
523         u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
524         u32 num_prde = 0;
525         u32 ttl_dwords = 0;
526         dma_addr_t cd_paddr;
527 
528         cd = (struct command_desc *)pp->cmdentry + tag;
529         cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
530 
531         ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
532 
533         VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n",
534                 cd->cfis[0], cd->cfis[1], cd->cfis[2]);
535 
536         if (qc->tf.protocol == ATA_PROT_NCQ) {
537                 VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n",
538                         cd->cfis[3], cd->cfis[11]);
539         }
540 
541         /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
542         if (ata_is_atapi(qc->tf.protocol)) {
543                 desc_info |= ATAPI_CMD;
544                 memset((void *)&cd->acmd, 0, 32);
545                 memcpy((void *)&cd->acmd, qc->cdb, qc->dev->cdb_len);
546         }
547 
548         if (qc->flags & ATA_QCFLAG_DMAMAP)
549                 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
550                                             &ttl_dwords, cd_paddr,
551                                             host_priv->data_snoop);
552 
553         if (qc->tf.protocol == ATA_PROT_NCQ)
554                 desc_info |= FPDMA_QUEUED_CMD;
555 
556         sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords,
557                                      num_prde, 5);
558 
559         VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n",
560                 desc_info, ttl_dwords, num_prde);
561 }
562 
563 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
564 {
565         struct ata_port *ap = qc->ap;
566         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
567         void __iomem *hcr_base = host_priv->hcr_base;
568         unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
569 
570         VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
571                 ioread32(CQ + hcr_base),
572                 ioread32(CA + hcr_base),
573                 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
574 
575         iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
576 
577         /* Simply queue command to the controller/device */
578         iowrite32(1 << tag, CQ + hcr_base);
579 
580         VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n",
581                 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
582 
583         VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
584                 ioread32(CE + hcr_base),
585                 ioread32(DE + hcr_base),
586                 ioread32(CC + hcr_base),
587                 ioread32(COMMANDSTAT + host_priv->csr_base));
588 
589         return 0;
590 }
591 
592 static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
593 {
594         struct sata_fsl_port_priv *pp = qc->ap->private_data;
595         struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
596         void __iomem *hcr_base = host_priv->hcr_base;
597         unsigned int tag = sata_fsl_tag(qc->tag, hcr_base);
598         struct command_desc *cd;
599 
600         cd = pp->cmdentry + tag;
601 
602         ata_tf_from_fis(cd->sfis, &qc->result_tf);
603         return true;
604 }
605 
606 static int sata_fsl_scr_write(struct ata_link *link,
607                               unsigned int sc_reg_in, u32 val)
608 {
609         struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
610         void __iomem *ssr_base = host_priv->ssr_base;
611         unsigned int sc_reg;
612 
613         switch (sc_reg_in) {
614         case SCR_STATUS:
615         case SCR_ERROR:
616         case SCR_CONTROL:
617         case SCR_ACTIVE:
618                 sc_reg = sc_reg_in;
619                 break;
620         default:
621                 return -EINVAL;
622         }
623 
624         VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg);
625 
626         iowrite32(val, ssr_base + (sc_reg * 4));
627         return 0;
628 }
629 
630 static int sata_fsl_scr_read(struct ata_link *link,
631                              unsigned int sc_reg_in, u32 *val)
632 {
633         struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
634         void __iomem *ssr_base = host_priv->ssr_base;
635         unsigned int sc_reg;
636 
637         switch (sc_reg_in) {
638         case SCR_STATUS:
639         case SCR_ERROR:
640         case SCR_CONTROL:
641         case SCR_ACTIVE:
642                 sc_reg = sc_reg_in;
643                 break;
644         default:
645                 return -EINVAL;
646         }
647 
648         VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg);
649 
650         *val = ioread32(ssr_base + (sc_reg * 4));
651         return 0;
652 }
653 
654 static void sata_fsl_freeze(struct ata_port *ap)
655 {
656         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
657         void __iomem *hcr_base = host_priv->hcr_base;
658         u32 temp;
659 
660         VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
661                 ioread32(CQ + hcr_base),
662                 ioread32(CA + hcr_base),
663                 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
664         VPRINTK("CmdStat = 0x%x\n",
665                 ioread32(host_priv->csr_base + COMMANDSTAT));
666 
667         /* disable interrupts on the controller/port */
668         temp = ioread32(hcr_base + HCONTROL);
669         iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
670 
671         VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n",
672                 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
673 }
674 
675 static void sata_fsl_thaw(struct ata_port *ap)
676 {
677         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
678         void __iomem *hcr_base = host_priv->hcr_base;
679         u32 temp;
680 
681         /* ack. any pending IRQs for this controller/port */
682         temp = ioread32(hcr_base + HSTATUS);
683 
684         VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F));
685 
686         if (temp & 0x3F)
687                 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
688 
689         /* enable interrupts on the controller/port */
690         temp = ioread32(hcr_base + HCONTROL);
691         iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
692 
693         VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n",
694                 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
695 }
696 
697 static void sata_fsl_pmp_attach(struct ata_port *ap)
698 {
699         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
700         void __iomem *hcr_base = host_priv->hcr_base;
701         u32 temp;
702 
703         temp = ioread32(hcr_base + HCONTROL);
704         iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
705 }
706 
707 static void sata_fsl_pmp_detach(struct ata_port *ap)
708 {
709         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
710         void __iomem *hcr_base = host_priv->hcr_base;
711         u32 temp;
712 
713         temp = ioread32(hcr_base + HCONTROL);
714         temp &= ~HCONTROL_PMP_ATTACHED;
715         iowrite32(temp, hcr_base + HCONTROL);
716 
717         /* enable interrupts on the controller/port */
718         temp = ioread32(hcr_base + HCONTROL);
719         iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
720 
721 }
722 
723 static int sata_fsl_port_start(struct ata_port *ap)
724 {
725         struct device *dev = ap->host->dev;
726         struct sata_fsl_port_priv *pp;
727         void *mem;
728         dma_addr_t mem_dma;
729         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
730         void __iomem *hcr_base = host_priv->hcr_base;
731         u32 temp;
732 
733         pp = kzalloc(sizeof(*pp), GFP_KERNEL);
734         if (!pp)
735                 return -ENOMEM;
736 
737         mem = dma_zalloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
738                                   GFP_KERNEL);
739         if (!mem) {
740                 kfree(pp);
741                 return -ENOMEM;
742         }
743 
744         pp->cmdslot = mem;
745         pp->cmdslot_paddr = mem_dma;
746 
747         mem += SATA_FSL_CMD_SLOT_SIZE;
748         mem_dma += SATA_FSL_CMD_SLOT_SIZE;
749 
750         pp->cmdentry = mem;
751         pp->cmdentry_paddr = mem_dma;
752 
753         ap->private_data = pp;
754 
755         VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n",
756                 pp->cmdslot_paddr, pp->cmdentry_paddr);
757 
758         /* Now, update the CHBA register in host controller cmd register set */
759         iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
760 
761         /*
762          * Now, we can bring the controller on-line & also initiate
763          * the COMINIT sequence, we simply return here and the boot-probing
764          * & device discovery process is re-initiated by libATA using a
765          * Softreset EH (dummy) session. Hence, boot probing and device
766          * discovey will be part of sata_fsl_softreset() callback.
767          */
768 
769         temp = ioread32(hcr_base + HCONTROL);
770         iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
771 
772         VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
773         VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
774         VPRINTK("CHBA  = 0x%x\n", ioread32(hcr_base + CHBA));
775 
776         return 0;
777 }
778 
779 static void sata_fsl_port_stop(struct ata_port *ap)
780 {
781         struct device *dev = ap->host->dev;
782         struct sata_fsl_port_priv *pp = ap->private_data;
783         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
784         void __iomem *hcr_base = host_priv->hcr_base;
785         u32 temp;
786 
787         /*
788          * Force host controller to go off-line, aborting current operations
789          */
790         temp = ioread32(hcr_base + HCONTROL);
791         temp &= ~HCONTROL_ONLINE_PHY_RST;
792         temp |= HCONTROL_FORCE_OFFLINE;
793         iowrite32(temp, hcr_base + HCONTROL);
794 
795         /* Poll for controller to go offline - should happen immediately */
796         ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
797 
798         ap->private_data = NULL;
799         dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
800                           pp->cmdslot, pp->cmdslot_paddr);
801 
802         kfree(pp);
803 }
804 
805 static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
806 {
807         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
808         void __iomem *hcr_base = host_priv->hcr_base;
809         struct ata_taskfile tf;
810         u32 temp;
811 
812         temp = ioread32(hcr_base + SIGNATURE);
813 
814         VPRINTK("raw sig = 0x%x\n", temp);
815         VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
816         VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
817 
818         tf.lbah = (temp >> 24) & 0xff;
819         tf.lbam = (temp >> 16) & 0xff;
820         tf.lbal = (temp >> 8) & 0xff;
821         tf.nsect = temp & 0xff;
822 
823         return ata_dev_classify(&tf);
824 }
825 
826 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
827                                         unsigned long deadline)
828 {
829         struct ata_port *ap = link->ap;
830         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
831         void __iomem *hcr_base = host_priv->hcr_base;
832         u32 temp;
833         int i = 0;
834         unsigned long start_jiffies;
835 
836         DPRINTK("in xx_hardreset\n");
837 
838 try_offline_again:
839         /*
840          * Force host controller to go off-line, aborting current operations
841          */
842         temp = ioread32(hcr_base + HCONTROL);
843         temp &= ~HCONTROL_ONLINE_PHY_RST;
844         iowrite32(temp, hcr_base + HCONTROL);
845 
846         /* Poll for controller to go offline */
847         temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
848                                  1, 500);
849 
850         if (temp & ONLINE) {
851                 ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i);
852 
853                 /*
854                  * Try to offline controller atleast twice
855                  */
856                 i++;
857                 if (i == 2)
858                         goto err;
859                 else
860                         goto try_offline_again;
861         }
862 
863         DPRINTK("hardreset, controller off-lined\n");
864         VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
865         VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
866 
867         /*
868          * PHY reset should remain asserted for atleast 1ms
869          */
870         ata_msleep(ap, 1);
871 
872         sata_set_spd(link);
873 
874         /*
875          * Now, bring the host controller online again, this can take time
876          * as PHY reset and communication establishment, 1st D2H FIS and
877          * device signature update is done, on safe side assume 500ms
878          * NOTE : Host online status may be indicated immediately!!
879          */
880 
881         temp = ioread32(hcr_base + HCONTROL);
882         temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
883         temp |= HCONTROL_PMP_ATTACHED;
884         iowrite32(temp, hcr_base + HCONTROL);
885 
886         temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
887 
888         if (!(temp & ONLINE)) {
889                 ata_port_err(ap, "Hardreset failed, not on-lined\n");
890                 goto err;
891         }
892 
893         DPRINTK("hardreset, controller off-lined & on-lined\n");
894         VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
895         VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
896 
897         /*
898          * First, wait for the PHYRDY change to occur before waiting for
899          * the signature, and also verify if SStatus indicates device
900          * presence
901          */
902 
903         temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
904         if ((!(temp & 0x10)) || ata_link_offline(link)) {
905                 ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n",
906                               ioread32(hcr_base + HSTATUS));
907                 *class = ATA_DEV_NONE;
908                 return 0;
909         }
910 
911         /*
912          * Wait for the first D2H from device,i.e,signature update notification
913          */
914         start_jiffies = jiffies;
915         temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
916                         500, jiffies_to_msecs(deadline - start_jiffies));
917 
918         if ((temp & 0xFF) != 0x18) {
919                 ata_port_warn(ap, "No Signature Update\n");
920                 *class = ATA_DEV_NONE;
921                 goto do_followup_srst;
922         } else {
923                 ata_port_info(ap, "Signature Update detected @ %d msecs\n",
924                               jiffies_to_msecs(jiffies - start_jiffies));
925                 *class = sata_fsl_dev_classify(ap);
926                 return 0;
927         }
928 
929 do_followup_srst:
930         /*
931          * request libATA to perform follow-up softreset
932          */
933         return -EAGAIN;
934 
935 err:
936         return -EIO;
937 }
938 
939 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
940                                         unsigned long deadline)
941 {
942         struct ata_port *ap = link->ap;
943         struct sata_fsl_port_priv *pp = ap->private_data;
944         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
945         void __iomem *hcr_base = host_priv->hcr_base;
946         int pmp = sata_srst_pmp(link);
947         u32 temp;
948         struct ata_taskfile tf;
949         u8 *cfis;
950         u32 Serror;
951 
952         DPRINTK("in xx_softreset\n");
953 
954         if (ata_link_offline(link)) {
955                 DPRINTK("PHY reports no device\n");
956                 *class = ATA_DEV_NONE;
957                 return 0;
958         }
959 
960         /*
961          * Send a device reset (SRST) explicitly on command slot #0
962          * Check : will the command queue (reg) be cleared during offlining ??
963          * Also we will be online only if Phy commn. has been established
964          * and device presence has been detected, therefore if we have
965          * reached here, we can send a command to the target device
966          */
967 
968         DPRINTK("Sending SRST/device reset\n");
969 
970         ata_tf_init(link->device, &tf);
971         cfis = (u8 *) &pp->cmdentry->cfis;
972 
973         /* device reset/SRST is a control register update FIS, uses tag0 */
974         sata_fsl_setup_cmd_hdr_entry(pp, 0,
975                 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
976 
977         tf.ctl |= ATA_SRST;     /* setup SRST bit in taskfile control reg */
978         ata_tf_to_fis(&tf, pmp, 0, cfis);
979 
980         DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
981                 cfis[0], cfis[1], cfis[2], cfis[3]);
982 
983         /*
984          * Queue SRST command to the controller/device, ensure that no
985          * other commands are active on the controller/device
986          */
987 
988         DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
989                 ioread32(CQ + hcr_base),
990                 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
991 
992         iowrite32(0xFFFF, CC + hcr_base);
993         if (pmp != SATA_PMP_CTRL_PORT)
994                 iowrite32(pmp, CQPMP + hcr_base);
995         iowrite32(1, CQ + hcr_base);
996 
997         temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
998         if (temp & 0x1) {
999                 ata_port_warn(ap, "ATA_SRST issue failed\n");
1000 
1001                 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
1002                         ioread32(CQ + hcr_base),
1003                         ioread32(CA + hcr_base), ioread32(CC + hcr_base));
1004 
1005                 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
1006 
1007                 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1008                 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1009                 DPRINTK("Serror = 0x%x\n", Serror);
1010                 goto err;
1011         }
1012 
1013         ata_msleep(ap, 1);
1014 
1015         /*
1016          * SATA device enters reset state after receiving a Control register
1017          * FIS with SRST bit asserted and it awaits another H2D Control reg.
1018          * FIS with SRST bit cleared, then the device does internal diags &
1019          * initialization, followed by indicating it's initialization status
1020          * using ATA signature D2H register FIS to the host controller.
1021          */
1022 
1023         sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
1024                                       0, 0, 5);
1025 
1026         tf.ctl &= ~ATA_SRST;    /* 2nd H2D Ctl. register FIS */
1027         ata_tf_to_fis(&tf, pmp, 0, cfis);
1028 
1029         if (pmp != SATA_PMP_CTRL_PORT)
1030                 iowrite32(pmp, CQPMP + hcr_base);
1031         iowrite32(1, CQ + hcr_base);
1032         ata_msleep(ap, 150);            /* ?? */
1033 
1034         /*
1035          * The above command would have signalled an interrupt on command
1036          * complete, which needs special handling, by clearing the Nth
1037          * command bit of the CCreg
1038          */
1039         iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
1040 
1041         DPRINTK("SATA FSL : Now checking device signature\n");
1042 
1043         *class = ATA_DEV_NONE;
1044 
1045         /* Verify if SStatus indicates device presence */
1046         if (ata_link_online(link)) {
1047                 /*
1048                  * if we are here, device presence has been detected,
1049                  * 1st D2H FIS would have been received, but sfis in
1050                  * command desc. is not updated, but signature register
1051                  * would have been updated
1052                  */
1053 
1054                 *class = sata_fsl_dev_classify(ap);
1055 
1056                 DPRINTK("class = %d\n", *class);
1057                 VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC));
1058                 VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE));
1059         }
1060 
1061         return 0;
1062 
1063 err:
1064         return -EIO;
1065 }
1066 
1067 static void sata_fsl_error_handler(struct ata_port *ap)
1068 {
1069 
1070         DPRINTK("in xx_error_handler\n");
1071         sata_pmp_error_handler(ap);
1072 
1073 }
1074 
1075 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
1076 {
1077         if (qc->flags & ATA_QCFLAG_FAILED)
1078                 qc->err_mask |= AC_ERR_OTHER;
1079 
1080         if (qc->err_mask) {
1081                 /* make DMA engine forget about the failed command */
1082 
1083         }
1084 }
1085 
1086 static void sata_fsl_error_intr(struct ata_port *ap)
1087 {
1088         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1089         void __iomem *hcr_base = host_priv->hcr_base;
1090         u32 hstatus, dereg=0, cereg = 0, SError = 0;
1091         unsigned int err_mask = 0, action = 0;
1092         int freeze = 0, abort=0;
1093         struct ata_link *link = NULL;
1094         struct ata_queued_cmd *qc = NULL;
1095         struct ata_eh_info *ehi;
1096 
1097         hstatus = ioread32(hcr_base + HSTATUS);
1098         cereg = ioread32(hcr_base + CE);
1099 
1100         /* first, analyze and record host port events */
1101         link = &ap->link;
1102         ehi = &link->eh_info;
1103         ata_ehi_clear_desc(ehi);
1104 
1105         /*
1106          * Handle & Clear SError
1107          */
1108 
1109         sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1110         if (unlikely(SError & 0xFFFF0000))
1111                 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
1112 
1113         DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1114                 hstatus, cereg, ioread32(hcr_base + DE), SError);
1115 
1116         /* handle fatal errors */
1117         if (hstatus & FATAL_ERROR_DECODE) {
1118                 ehi->err_mask |= AC_ERR_ATA_BUS;
1119                 ehi->action |= ATA_EH_SOFTRESET;
1120 
1121                 freeze = 1;
1122         }
1123 
1124         /* Handle SDB FIS receive & notify update */
1125         if (hstatus & INT_ON_SNOTIFY_UPDATE)
1126                 sata_async_notification(ap);
1127 
1128         /* Handle PHYRDY change notification */
1129         if (hstatus & INT_ON_PHYRDY_CHG) {
1130                 DPRINTK("SATA FSL: PHYRDY change indication\n");
1131 
1132                 /* Setup a soft-reset EH action */
1133                 ata_ehi_hotplugged(ehi);
1134                 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
1135                 freeze = 1;
1136         }
1137 
1138         /* handle single device errors */
1139         if (cereg) {
1140                 /*
1141                  * clear the command error, also clears queue to the device
1142                  * in error, and we can (re)issue commands to this device.
1143                  * When a device is in error all commands queued into the
1144                  * host controller and at the device are considered aborted
1145                  * and the queue for that device is stopped. Now, after
1146                  * clearing the device error, we can issue commands to the
1147                  * device to interrogate it to find the source of the error.
1148                  */
1149                 abort = 1;
1150 
1151                 DPRINTK("single device error, CE=0x%x, DE=0x%x\n",
1152                         ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1153 
1154                 /* find out the offending link and qc */
1155                 if (ap->nr_pmp_links) {
1156                         unsigned int dev_num;
1157 
1158                         dereg = ioread32(hcr_base + DE);
1159                         iowrite32(dereg, hcr_base + DE);
1160                         iowrite32(cereg, hcr_base + CE);
1161 
1162                         dev_num = ffs(dereg) - 1;
1163                         if (dev_num < ap->nr_pmp_links && dereg != 0) {
1164                                 link = &ap->pmp_link[dev_num];
1165                                 ehi = &link->eh_info;
1166                                 qc = ata_qc_from_tag(ap, link->active_tag);
1167                                 /*
1168                                  * We should consider this as non fatal error,
1169                                  * and TF must be updated as done below.
1170                                  */
1171 
1172                                 err_mask |= AC_ERR_DEV;
1173 
1174                         } else {
1175                                 err_mask |= AC_ERR_HSM;
1176                                 action |= ATA_EH_HARDRESET;
1177                                 freeze = 1;
1178                         }
1179                 } else {
1180                         dereg = ioread32(hcr_base + DE);
1181                         iowrite32(dereg, hcr_base + DE);
1182                         iowrite32(cereg, hcr_base + CE);
1183 
1184                         qc = ata_qc_from_tag(ap, link->active_tag);
1185                         /*
1186                          * We should consider this as non fatal error,
1187                          * and TF must be updated as done below.
1188                         */
1189                         err_mask |= AC_ERR_DEV;
1190                 }
1191         }
1192 
1193         /* record error info */
1194         if (qc)
1195                 qc->err_mask |= err_mask;
1196         else
1197                 ehi->err_mask |= err_mask;
1198 
1199         ehi->action |= action;
1200 
1201         /* freeze or abort */
1202         if (freeze)
1203                 ata_port_freeze(ap);
1204         else if (abort) {
1205                 if (qc)
1206                         ata_link_abort(qc->dev->link);
1207                 else
1208                         ata_port_abort(ap);
1209         }
1210 }
1211 
1212 static void sata_fsl_host_intr(struct ata_port *ap)
1213 {
1214         struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1215         void __iomem *hcr_base = host_priv->hcr_base;
1216         u32 hstatus, done_mask = 0;
1217         struct ata_queued_cmd *qc;
1218         u32 SError;
1219         u32 tag;
1220         u32 status_mask = INT_ON_ERROR;
1221 
1222         hstatus = ioread32(hcr_base + HSTATUS);
1223 
1224         sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1225 
1226         /* Read command completed register */
1227         done_mask = ioread32(hcr_base + CC);
1228 
1229         /* Workaround for data length mismatch errata */
1230         if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) {
1231                 for (tag = 0; tag < ATA_MAX_QUEUE; tag++) {
1232                         qc = ata_qc_from_tag(ap, tag);
1233                         if (qc && ata_is_atapi(qc->tf.protocol)) {
1234                                 u32 hcontrol;
1235                                 /* Set HControl[27] to clear error registers */
1236                                 hcontrol = ioread32(hcr_base + HCONTROL);
1237                                 iowrite32(hcontrol | CLEAR_ERROR,
1238                                                 hcr_base + HCONTROL);
1239 
1240                                 /* Clear HControl[27] */
1241                                 iowrite32(hcontrol & ~CLEAR_ERROR,
1242                                                 hcr_base + HCONTROL);
1243 
1244                                 /* Clear SError[E] bit */
1245                                 sata_fsl_scr_write(&ap->link, SCR_ERROR,
1246                                                 SError);
1247 
1248                                 /* Ignore fatal error and device error */
1249                                 status_mask &= ~(INT_ON_SINGL_DEVICE_ERR
1250                                                 | INT_ON_FATAL_ERR);
1251                                 break;
1252                         }
1253                 }
1254         }
1255 
1256         if (unlikely(SError & 0xFFFF0000)) {
1257                 DPRINTK("serror @host_intr : 0x%x\n", SError);
1258                 sata_fsl_error_intr(ap);
1259         }
1260 
1261         if (unlikely(hstatus & status_mask)) {
1262                 DPRINTK("error interrupt!!\n");
1263                 sata_fsl_error_intr(ap);
1264                 return;
1265         }
1266 
1267         VPRINTK("Status of all queues :\n");
1268         VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%x\n",
1269                 done_mask,
1270                 ioread32(hcr_base + CA),
1271                 ioread32(hcr_base + CE),
1272                 ioread32(hcr_base + CQ),
1273                 ap->qc_active);
1274 
1275         if (done_mask & ap->qc_active) {
1276                 int i;
1277                 /* clear CC bit, this will also complete the interrupt */
1278                 iowrite32(done_mask, hcr_base + CC);
1279 
1280                 DPRINTK("Status of all queues :\n");
1281                 DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1282                         done_mask, ioread32(hcr_base + CA),
1283                         ioread32(hcr_base + CE));
1284 
1285                 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1286                         if (done_mask & (1 << i))
1287                                 DPRINTK
1288                                     ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1289                                      i, ioread32(hcr_base + CC),
1290                                      ioread32(hcr_base + CA));
1291                 }
1292                 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
1293                 return;
1294 
1295         } else if ((ap->qc_active & (1 << ATA_TAG_INTERNAL))) {
1296                 iowrite32(1, hcr_base + CC);
1297                 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
1298 
1299                 DPRINTK("completing non-ncq cmd, CC=0x%x\n",
1300                          ioread32(hcr_base + CC));
1301 
1302                 if (qc) {
1303                         ata_qc_complete(qc);
1304                 }
1305         } else {
1306                 /* Spurious Interrupt!! */
1307                 DPRINTK("spurious interrupt!!, CC = 0x%x\n",
1308                         ioread32(hcr_base + CC));
1309                 iowrite32(done_mask, hcr_base + CC);
1310                 return;
1311         }
1312 }
1313 
1314 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1315 {
1316         struct ata_host *host = dev_instance;
1317         struct sata_fsl_host_priv *host_priv = host->private_data;
1318         void __iomem *hcr_base = host_priv->hcr_base;
1319         u32 interrupt_enables;
1320         unsigned handled = 0;
1321         struct ata_port *ap;
1322 
1323         /* ack. any pending IRQs for this controller/port */
1324         interrupt_enables = ioread32(hcr_base + HSTATUS);
1325         interrupt_enables &= 0x3F;
1326 
1327         DPRINTK("interrupt status 0x%x\n", interrupt_enables);
1328 
1329         if (!interrupt_enables)
1330                 return IRQ_NONE;
1331 
1332         spin_lock(&host->lock);
1333 
1334         /* Assuming one port per host controller */
1335 
1336         ap = host->ports[0];
1337         if (ap) {
1338                 sata_fsl_host_intr(ap);
1339         } else {
1340                 dev_warn(host->dev, "interrupt on disabled port 0\n");
1341         }
1342 
1343         iowrite32(interrupt_enables, hcr_base + HSTATUS);
1344         handled = 1;
1345 
1346         spin_unlock(&host->lock);
1347 
1348         return IRQ_RETVAL(handled);
1349 }
1350 
1351 /*
1352  * Multiple ports are represented by multiple SATA controllers with
1353  * one port per controller
1354  */
1355 static int sata_fsl_init_controller(struct ata_host *host)
1356 {
1357         struct sata_fsl_host_priv *host_priv = host->private_data;
1358         void __iomem *hcr_base = host_priv->hcr_base;
1359         u32 temp;
1360 
1361         /*
1362          * NOTE : We cannot bring the controller online before setting
1363          * the CHBA, hence main controller initialization is done as
1364          * part of the port_start() callback
1365          */
1366 
1367         /* sata controller to operate in enterprise mode */
1368         temp = ioread32(hcr_base + HCONTROL);
1369         iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL);
1370 
1371         /* ack. any pending IRQs for this controller/port */
1372         temp = ioread32(hcr_base + HSTATUS);
1373         if (temp & 0x3F)
1374                 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1375 
1376         /* Keep interrupts disabled on the controller */
1377         temp = ioread32(hcr_base + HCONTROL);
1378         iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1379 
1380         /* Disable interrupt coalescing control(icc), for the moment */
1381         DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC));
1382         iowrite32(0x01000000, hcr_base + ICC);
1383 
1384         /* clear error registers, SError is cleared by libATA  */
1385         iowrite32(0x00000FFFF, hcr_base + CE);
1386         iowrite32(0x00000FFFF, hcr_base + DE);
1387 
1388         /*
1389          * reset the number of command complete bits which will cause the
1390          * interrupt to be signaled
1391          */
1392         fsl_sata_set_irq_coalescing(host, intr_coalescing_count,
1393                         intr_coalescing_ticks);
1394 
1395         /*
1396          * host controller will be brought on-line, during xx_port_start()
1397          * callback, that should also initiate the OOB, COMINIT sequence
1398          */
1399 
1400         DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
1401         DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
1402 
1403         return 0;
1404 }
1405 
1406 /*
1407  * scsi mid-layer and libata interface structures
1408  */
1409 static struct scsi_host_template sata_fsl_sht = {
1410         ATA_NCQ_SHT("sata_fsl"),
1411         .can_queue = SATA_FSL_QUEUE_DEPTH,
1412         .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1413         .dma_boundary = ATA_DMA_BOUNDARY,
1414 };
1415 
1416 static struct ata_port_operations sata_fsl_ops = {
1417         .inherits               = &sata_pmp_port_ops,
1418 
1419         .qc_defer = ata_std_qc_defer,
1420         .qc_prep = sata_fsl_qc_prep,
1421         .qc_issue = sata_fsl_qc_issue,
1422         .qc_fill_rtf = sata_fsl_qc_fill_rtf,
1423 
1424         .scr_read = sata_fsl_scr_read,
1425         .scr_write = sata_fsl_scr_write,
1426 
1427         .freeze = sata_fsl_freeze,
1428         .thaw = sata_fsl_thaw,
1429         .softreset = sata_fsl_softreset,
1430         .hardreset = sata_fsl_hardreset,
1431         .pmp_softreset = sata_fsl_softreset,
1432         .error_handler = sata_fsl_error_handler,
1433         .post_internal_cmd = sata_fsl_post_internal_cmd,
1434 
1435         .port_start = sata_fsl_port_start,
1436         .port_stop = sata_fsl_port_stop,
1437 
1438         .pmp_attach = sata_fsl_pmp_attach,
1439         .pmp_detach = sata_fsl_pmp_detach,
1440 };
1441 
1442 static const struct ata_port_info sata_fsl_port_info[] = {
1443         {
1444          .flags = SATA_FSL_HOST_FLAGS,
1445          .pio_mask = ATA_PIO4,
1446          .udma_mask = ATA_UDMA6,
1447          .port_ops = &sata_fsl_ops,
1448          },
1449 };
1450 
1451 static int sata_fsl_probe(struct platform_device *ofdev)
1452 {
1453         int retval = -ENXIO;
1454         void __iomem *hcr_base = NULL;
1455         void __iomem *ssr_base = NULL;
1456         void __iomem *csr_base = NULL;
1457         struct sata_fsl_host_priv *host_priv = NULL;
1458         int irq;
1459         struct ata_host *host = NULL;
1460         u32 temp;
1461 
1462         struct ata_port_info pi = sata_fsl_port_info[0];
1463         const struct ata_port_info *ppi[] = { &pi, NULL };
1464 
1465         dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n");
1466 
1467         hcr_base = of_iomap(ofdev->dev.of_node, 0);
1468         if (!hcr_base)
1469                 goto error_exit_with_cleanup;
1470 
1471         ssr_base = hcr_base + 0x100;
1472         csr_base = hcr_base + 0x140;
1473 
1474         if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) {
1475                 temp = ioread32(csr_base + TRANSCFG);
1476                 temp = temp & 0xffffffe0;
1477                 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
1478         }
1479 
1480         DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG));
1481         DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc));
1482         DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE);
1483 
1484         host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1485         if (!host_priv)
1486                 goto error_exit_with_cleanup;
1487 
1488         host_priv->hcr_base = hcr_base;
1489         host_priv->ssr_base = ssr_base;
1490         host_priv->csr_base = csr_base;
1491 
1492         irq = irq_of_parse_and_map(ofdev->dev.of_node, 0);
1493         if (!irq) {
1494                 dev_err(&ofdev->dev, "invalid irq from platform\n");
1495                 goto error_exit_with_cleanup;
1496         }
1497         host_priv->irq = irq;
1498 
1499         if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2"))
1500                 host_priv->data_snoop = DATA_SNOOP_ENABLE_V2;
1501         else
1502                 host_priv->data_snoop = DATA_SNOOP_ENABLE_V1;
1503 
1504         /* allocate host structure */
1505         host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1506         if (!host) {
1507                 retval = -ENOMEM;
1508                 goto error_exit_with_cleanup;
1509         }
1510 
1511         /* host->iomap is not used currently */
1512         host->private_data = host_priv;
1513 
1514         /* initialize host controller */
1515         sata_fsl_init_controller(host);
1516 
1517         /*
1518          * Now, register with libATA core, this will also initiate the
1519          * device discovery process, invoking our port_start() handler &
1520          * error_handler() to execute a dummy Softreset EH session
1521          */
1522         ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1523                           &sata_fsl_sht);
1524 
1525         platform_set_drvdata(ofdev, host);
1526 
1527         host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show;
1528         host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store;
1529         sysfs_attr_init(&host_priv->intr_coalescing.attr);
1530         host_priv->intr_coalescing.attr.name = "intr_coalescing";
1531         host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR;
1532         retval = device_create_file(host->dev, &host_priv->intr_coalescing);
1533         if (retval)
1534                 goto error_exit_with_cleanup;
1535 
1536         host_priv->rx_watermark.show = fsl_sata_rx_watermark_show;
1537         host_priv->rx_watermark.store = fsl_sata_rx_watermark_store;
1538         sysfs_attr_init(&host_priv->rx_watermark.attr);
1539         host_priv->rx_watermark.attr.name = "rx_watermark";
1540         host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR;
1541         retval = device_create_file(host->dev, &host_priv->rx_watermark);
1542         if (retval) {
1543                 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1544                 goto error_exit_with_cleanup;
1545         }
1546 
1547         return 0;
1548 
1549 error_exit_with_cleanup:
1550 
1551         if (host)
1552                 ata_host_detach(host);
1553 
1554         if (hcr_base)
1555                 iounmap(hcr_base);
1556         kfree(host_priv);
1557 
1558         return retval;
1559 }
1560 
1561 static int sata_fsl_remove(struct platform_device *ofdev)
1562 {
1563         struct ata_host *host = platform_get_drvdata(ofdev);
1564         struct sata_fsl_host_priv *host_priv = host->private_data;
1565 
1566         device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1567         device_remove_file(&ofdev->dev, &host_priv->rx_watermark);
1568 
1569         ata_host_detach(host);
1570 
1571         irq_dispose_mapping(host_priv->irq);
1572         iounmap(host_priv->hcr_base);
1573         kfree(host_priv);
1574 
1575         return 0;
1576 }
1577 
1578 #ifdef CONFIG_PM_SLEEP
1579 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
1580 {
1581         struct ata_host *host = platform_get_drvdata(op);
1582         return ata_host_suspend(host, state);
1583 }
1584 
1585 static int sata_fsl_resume(struct platform_device *op)
1586 {
1587         struct ata_host *host = platform_get_drvdata(op);
1588         struct sata_fsl_host_priv *host_priv = host->private_data;
1589         int ret;
1590         void __iomem *hcr_base = host_priv->hcr_base;
1591         struct ata_port *ap = host->ports[0];
1592         struct sata_fsl_port_priv *pp = ap->private_data;
1593 
1594         ret = sata_fsl_init_controller(host);
1595         if (ret) {
1596                 dev_err(&op->dev, "Error initializing hardware\n");
1597                 return ret;
1598         }
1599 
1600         /* Recovery the CHBA register in host controller cmd register set */
1601         iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
1602 
1603         iowrite32((ioread32(hcr_base + HCONTROL)
1604                                 | HCONTROL_ONLINE_PHY_RST
1605                                 | HCONTROL_SNOOP_ENABLE
1606                                 | HCONTROL_PMP_ATTACHED),
1607                         hcr_base + HCONTROL);
1608 
1609         ata_host_resume(host);
1610         return 0;
1611 }
1612 #endif
1613 
1614 static struct of_device_id fsl_sata_match[] = {
1615         {
1616                 .compatible = "fsl,pq-sata",
1617         },
1618         {
1619                 .compatible = "fsl,pq-sata-v2",
1620         },
1621         {},
1622 };
1623 
1624 MODULE_DEVICE_TABLE(of, fsl_sata_match);
1625 
1626 static struct platform_driver fsl_sata_driver = {
1627         .driver = {
1628                 .name = "fsl-sata",
1629                 .of_match_table = fsl_sata_match,
1630         },
1631         .probe          = sata_fsl_probe,
1632         .remove         = sata_fsl_remove,
1633 #ifdef CONFIG_PM_SLEEP
1634         .suspend        = sata_fsl_suspend,
1635         .resume         = sata_fsl_resume,
1636 #endif
1637 };
1638 
1639 module_platform_driver(fsl_sata_driver);
1640 
1641 MODULE_LICENSE("GPL");
1642 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1643 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1644 MODULE_VERSION("1.10");
1645 

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