Version:  2.0.40 2.2.26 2.4.37 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0

Linux/drivers/ata/sata_dwc_460ex.c

  1 /*
  2  * drivers/ata/sata_dwc_460ex.c
  3  *
  4  * Synopsys DesignWare Cores (DWC) SATA host driver
  5  *
  6  * Author: Mark Miesfeld <mmiesfeld@amcc.com>
  7  *
  8  * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
  9  * Copyright 2008 DENX Software Engineering
 10  *
 11  * Based on versions provided by AMCC and Synopsys which are:
 12  *          Copyright 2006 Applied Micro Circuits Corporation
 13  *          COPYRIGHT (C) 2005  SYNOPSYS, INC.  ALL RIGHTS RESERVED
 14  *
 15  * This program is free software; you can redistribute  it and/or modify it
 16  * under  the terms of  the GNU General  Public License as published by the
 17  * Free Software Foundation;  either version 2 of the  License, or (at your
 18  * option) any later version.
 19  */
 20 
 21 #ifdef CONFIG_SATA_DWC_DEBUG
 22 #define DEBUG
 23 #endif
 24 
 25 #ifdef CONFIG_SATA_DWC_VDEBUG
 26 #define VERBOSE_DEBUG
 27 #define DEBUG_NCQ
 28 #endif
 29 
 30 #include <linux/kernel.h>
 31 #include <linux/module.h>
 32 #include <linux/device.h>
 33 #include <linux/of_address.h>
 34 #include <linux/of_irq.h>
 35 #include <linux/of_platform.h>
 36 #include <linux/platform_device.h>
 37 #include <linux/libata.h>
 38 #include <linux/slab.h>
 39 #include "libata.h"
 40 
 41 #include <scsi/scsi_host.h>
 42 #include <scsi/scsi_cmnd.h>
 43 
 44 /* These two are defined in "libata.h" */
 45 #undef  DRV_NAME
 46 #undef  DRV_VERSION
 47 
 48 #define DRV_NAME        "sata-dwc"
 49 #define DRV_VERSION     "1.3"
 50 
 51 #ifndef out_le32
 52 #define out_le32(a, v)  __raw_writel(__cpu_to_le32(v), (void __iomem *)(a))
 53 #endif
 54 
 55 #ifndef in_le32
 56 #define in_le32(a)      __le32_to_cpu(__raw_readl((void __iomem *)(a)))
 57 #endif
 58 
 59 #ifndef NO_IRQ
 60 #define NO_IRQ          0
 61 #endif
 62 
 63 /* SATA DMA driver Globals */
 64 #define DMA_NUM_CHANS           1
 65 #define DMA_NUM_CHAN_REGS       8
 66 
 67 /* SATA DMA Register definitions */
 68 #define AHB_DMA_BRST_DFLT       64      /* 16 data items burst length*/
 69 
 70 struct dmareg {
 71         u32 low;                /* Low bits 0-31 */
 72         u32 high;               /* High bits 32-63 */
 73 };
 74 
 75 /* DMA Per Channel registers */
 76 struct dma_chan_regs {
 77         struct dmareg sar;      /* Source Address */
 78         struct dmareg dar;      /* Destination address */
 79         struct dmareg llp;      /* Linked List Pointer */
 80         struct dmareg ctl;      /* Control */
 81         struct dmareg sstat;    /* Source Status not implemented in core */
 82         struct dmareg dstat;    /* Destination Status not implemented in core*/
 83         struct dmareg sstatar;  /* Source Status Address not impl in core */
 84         struct dmareg dstatar;  /* Destination Status Address not implemente */
 85         struct dmareg cfg;      /* Config */
 86         struct dmareg sgr;      /* Source Gather */
 87         struct dmareg dsr;      /* Destination Scatter */
 88 };
 89 
 90 /* Generic Interrupt Registers */
 91 struct dma_interrupt_regs {
 92         struct dmareg tfr;      /* Transfer Interrupt */
 93         struct dmareg block;    /* Block Interrupt */
 94         struct dmareg srctran;  /* Source Transfer Interrupt */
 95         struct dmareg dsttran;  /* Dest Transfer Interrupt */
 96         struct dmareg error;    /* Error */
 97 };
 98 
 99 struct ahb_dma_regs {
100         struct dma_chan_regs    chan_regs[DMA_NUM_CHAN_REGS];
101         struct dma_interrupt_regs interrupt_raw;        /* Raw Interrupt */
102         struct dma_interrupt_regs interrupt_status;     /* Interrupt Status */
103         struct dma_interrupt_regs interrupt_mask;       /* Interrupt Mask */
104         struct dma_interrupt_regs interrupt_clear;      /* Interrupt Clear */
105         struct dmareg           statusInt;      /* Interrupt combined*/
106         struct dmareg           rq_srcreg;      /* Src Trans Req */
107         struct dmareg           rq_dstreg;      /* Dst Trans Req */
108         struct dmareg           rq_sgl_srcreg;  /* Sngl Src Trans Req*/
109         struct dmareg           rq_sgl_dstreg;  /* Sngl Dst Trans Req*/
110         struct dmareg           rq_lst_srcreg;  /* Last Src Trans Req*/
111         struct dmareg           rq_lst_dstreg;  /* Last Dst Trans Req*/
112         struct dmareg           dma_cfg;                /* DMA Config */
113         struct dmareg           dma_chan_en;            /* DMA Channel Enable*/
114         struct dmareg           dma_id;                 /* DMA ID */
115         struct dmareg           dma_test;               /* DMA Test */
116         struct dmareg           res1;                   /* reserved */
117         struct dmareg           res2;                   /* reserved */
118         /*
119          * DMA Comp Params
120          * Param 6 = dma_param[0], Param 5 = dma_param[1],
121          * Param 4 = dma_param[2] ...
122          */
123         struct dmareg           dma_params[6];
124 };
125 
126 /* Data structure for linked list item */
127 struct lli {
128         u32             sar;            /* Source Address */
129         u32             dar;            /* Destination address */
130         u32             llp;            /* Linked List Pointer */
131         struct dmareg   ctl;            /* Control */
132         struct dmareg   dstat;          /* Destination Status */
133 };
134 
135 enum {
136         SATA_DWC_DMAC_LLI_SZ =  (sizeof(struct lli)),
137         SATA_DWC_DMAC_LLI_NUM = 256,
138         SATA_DWC_DMAC_LLI_TBL_SZ = (SATA_DWC_DMAC_LLI_SZ * \
139                                         SATA_DWC_DMAC_LLI_NUM),
140         SATA_DWC_DMAC_TWIDTH_BYTES = 4,
141         SATA_DWC_DMAC_CTRL_TSIZE_MAX = (0x00000800 * \
142                                                 SATA_DWC_DMAC_TWIDTH_BYTES),
143 };
144 
145 /* DMA Register Operation Bits */
146 enum {
147         DMA_EN  =               0x00000001, /* Enable AHB DMA */
148         DMA_CTL_LLP_SRCEN =     0x10000000, /* Blk chain enable Src */
149         DMA_CTL_LLP_DSTEN =     0x08000000, /* Blk chain enable Dst */
150 };
151 
152 #define DMA_CTL_BLK_TS(size)    ((size) & 0x000000FFF)  /* Blk Transfer size */
153 #define DMA_CHANNEL(ch)         (0x00000001 << (ch))    /* Select channel */
154         /* Enable channel */
155 #define DMA_ENABLE_CHAN(ch)     ((0x00000001 << (ch)) |                 \
156                                  ((0x000000001 << (ch)) << 8))
157         /* Disable channel */
158 #define DMA_DISABLE_CHAN(ch)    (0x00000000 | ((0x000000001 << (ch)) << 8))
159         /* Transfer Type & Flow Controller */
160 #define DMA_CTL_TTFC(type)      (((type) & 0x7) << 20)
161 #define DMA_CTL_SMS(num)        (((num) & 0x3) << 25) /* Src Master Select */
162 #define DMA_CTL_DMS(num)        (((num) & 0x3) << 23)/* Dst Master Select */
163         /* Src Burst Transaction Length */
164 #define DMA_CTL_SRC_MSIZE(size) (((size) & 0x7) << 14)
165         /* Dst Burst Transaction Length */
166 #define DMA_CTL_DST_MSIZE(size) (((size) & 0x7) << 11)
167         /* Source Transfer Width */
168 #define DMA_CTL_SRC_TRWID(size) (((size) & 0x7) << 4)
169         /* Destination Transfer Width */
170 #define DMA_CTL_DST_TRWID(size) (((size) & 0x7) << 1)
171 
172 /* Assign HW handshaking interface (x) to destination / source peripheral */
173 #define DMA_CFG_HW_HS_DEST(int_num) (((int_num) & 0xF) << 11)
174 #define DMA_CFG_HW_HS_SRC(int_num) (((int_num) & 0xF) << 7)
175 #define DMA_CFG_HW_CH_PRIOR(int_num) (((int_num) & 0xF) << 5)
176 #define DMA_LLP_LMS(addr, master) (((addr) & 0xfffffffc) | (master))
177 
178 /*
179  * This define is used to set block chaining disabled in the control low
180  * register.  It is already in little endian format so it can be &'d dirctly.
181  * It is essentially: cpu_to_le32(~(DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN))
182  */
183 enum {
184         DMA_CTL_LLP_DISABLE_LE32 = 0xffffffe7,
185         DMA_CTL_TTFC_P2M_DMAC = 0x00000002, /* Per to mem, DMAC cntr */
186         DMA_CTL_TTFC_M2P_PER =  0x00000003, /* Mem to per, peripheral cntr */
187         DMA_CTL_SINC_INC =      0x00000000, /* Source Address Increment */
188         DMA_CTL_SINC_DEC =      0x00000200,
189         DMA_CTL_SINC_NOCHANGE = 0x00000400,
190         DMA_CTL_DINC_INC =      0x00000000, /* Destination Address Increment */
191         DMA_CTL_DINC_DEC =      0x00000080,
192         DMA_CTL_DINC_NOCHANGE = 0x00000100,
193         DMA_CTL_INT_EN =        0x00000001, /* Interrupt Enable */
194 
195 /* Channel Configuration Register high bits */
196         DMA_CFG_FCMOD_REQ =     0x00000001, /* Flow Control - request based */
197         DMA_CFG_PROTCTL =       (0x00000003 << 2),/* Protection Control */
198 
199 /* Channel Configuration Register low bits */
200         DMA_CFG_RELD_DST =      0x80000000, /* Reload Dest / Src Addr */
201         DMA_CFG_RELD_SRC =      0x40000000,
202         DMA_CFG_HS_SELSRC =     0x00000800, /* Software handshake Src/ Dest */
203         DMA_CFG_HS_SELDST =     0x00000400,
204         DMA_CFG_FIFOEMPTY =     (0x00000001 << 9), /* FIFO Empty bit */
205 
206 /* Channel Linked List Pointer Register */
207         DMA_LLP_AHBMASTER1 =    0,      /* List Master Select */
208         DMA_LLP_AHBMASTER2 =    1,
209 
210         SATA_DWC_MAX_PORTS = 1,
211 
212         SATA_DWC_SCR_OFFSET = 0x24,
213         SATA_DWC_REG_OFFSET = 0x64,
214 };
215 
216 /* DWC SATA Registers */
217 struct sata_dwc_regs {
218         u32 fptagr;             /* 1st party DMA tag */
219         u32 fpbor;              /* 1st party DMA buffer offset */
220         u32 fptcr;              /* 1st party DMA Xfr count */
221         u32 dmacr;              /* DMA Control */
222         u32 dbtsr;              /* DMA Burst Transac size */
223         u32 intpr;              /* Interrupt Pending */
224         u32 intmr;              /* Interrupt Mask */
225         u32 errmr;              /* Error Mask */
226         u32 llcr;               /* Link Layer Control */
227         u32 phycr;              /* PHY Control */
228         u32 physr;              /* PHY Status */
229         u32 rxbistpd;           /* Recvd BIST pattern def register */
230         u32 rxbistpd1;          /* Recvd BIST data dword1 */
231         u32 rxbistpd2;          /* Recvd BIST pattern data dword2 */
232         u32 txbistpd;           /* Trans BIST pattern def register */
233         u32 txbistpd1;          /* Trans BIST data dword1 */
234         u32 txbistpd2;          /* Trans BIST data dword2 */
235         u32 bistcr;             /* BIST Control Register */
236         u32 bistfctr;           /* BIST FIS Count Register */
237         u32 bistsr;             /* BIST Status Register */
238         u32 bistdecr;           /* BIST Dword Error count register */
239         u32 res[15];            /* Reserved locations */
240         u32 testr;              /* Test Register */
241         u32 versionr;           /* Version Register */
242         u32 idr;                /* ID Register */
243         u32 unimpl[192];        /* Unimplemented */
244         u32 dmadr[256]; /* FIFO Locations in DMA Mode */
245 };
246 
247 enum {
248         SCR_SCONTROL_DET_ENABLE =       0x00000001,
249         SCR_SSTATUS_DET_PRESENT =       0x00000001,
250         SCR_SERROR_DIAG_X       =       0x04000000,
251 /* DWC SATA Register Operations */
252         SATA_DWC_TXFIFO_DEPTH   =       0x01FF,
253         SATA_DWC_RXFIFO_DEPTH   =       0x01FF,
254         SATA_DWC_DMACR_TMOD_TXCHEN =    0x00000004,
255         SATA_DWC_DMACR_TXCHEN   = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
256         SATA_DWC_DMACR_RXCHEN   = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
257         SATA_DWC_DMACR_TXRXCH_CLEAR =   SATA_DWC_DMACR_TMOD_TXCHEN,
258         SATA_DWC_INTPR_DMAT     =       0x00000001,
259         SATA_DWC_INTPR_NEWFP    =       0x00000002,
260         SATA_DWC_INTPR_PMABRT   =       0x00000004,
261         SATA_DWC_INTPR_ERR      =       0x00000008,
262         SATA_DWC_INTPR_NEWBIST  =       0x00000010,
263         SATA_DWC_INTPR_IPF      =       0x10000000,
264         SATA_DWC_INTMR_DMATM    =       0x00000001,
265         SATA_DWC_INTMR_NEWFPM   =       0x00000002,
266         SATA_DWC_INTMR_PMABRTM  =       0x00000004,
267         SATA_DWC_INTMR_ERRM     =       0x00000008,
268         SATA_DWC_INTMR_NEWBISTM =       0x00000010,
269         SATA_DWC_LLCR_SCRAMEN   =       0x00000001,
270         SATA_DWC_LLCR_DESCRAMEN =       0x00000002,
271         SATA_DWC_LLCR_RPDEN     =       0x00000004,
272 /* This is all error bits, zero's are reserved fields. */
273         SATA_DWC_SERROR_ERR_BITS =      0x0FFF0F03
274 };
275 
276 #define SATA_DWC_SCR0_SPD_GET(v)        (((v) >> 4) & 0x0000000F)
277 #define SATA_DWC_DMACR_TX_CLEAR(v)      (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
278                                                  SATA_DWC_DMACR_TMOD_TXCHEN)
279 #define SATA_DWC_DMACR_RX_CLEAR(v)      (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
280                                                  SATA_DWC_DMACR_TMOD_TXCHEN)
281 #define SATA_DWC_DBTSR_MWR(size)        (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
282 #define SATA_DWC_DBTSR_MRD(size)        ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
283                                                  << 16)
284 struct sata_dwc_device {
285         struct device           *dev;           /* generic device struct */
286         struct ata_probe_ent    *pe;            /* ptr to probe-ent */
287         struct ata_host         *host;
288         u8 __iomem              *reg_base;
289         struct sata_dwc_regs    *sata_dwc_regs; /* DW Synopsys SATA specific */
290         int                     irq_dma;
291 };
292 
293 #define SATA_DWC_QCMD_MAX       32
294 
295 struct sata_dwc_device_port {
296         struct sata_dwc_device  *hsdev;
297         int                     cmd_issued[SATA_DWC_QCMD_MAX];
298         struct lli              *llit[SATA_DWC_QCMD_MAX];  /* DMA LLI table */
299         dma_addr_t              llit_dma[SATA_DWC_QCMD_MAX];
300         u32                     dma_chan[SATA_DWC_QCMD_MAX];
301         int                     dma_pending[SATA_DWC_QCMD_MAX];
302 };
303 
304 /*
305  * Commonly used DWC SATA driver Macros
306  */
307 #define HSDEV_FROM_HOST(host)  ((struct sata_dwc_device *)\
308                                         (host)->private_data)
309 #define HSDEV_FROM_AP(ap)  ((struct sata_dwc_device *)\
310                                         (ap)->host->private_data)
311 #define HSDEVP_FROM_AP(ap)   ((struct sata_dwc_device_port *)\
312                                         (ap)->private_data)
313 #define HSDEV_FROM_QC(qc)       ((struct sata_dwc_device *)\
314                                         (qc)->ap->host->private_data)
315 #define HSDEV_FROM_HSDEVP(p)    ((struct sata_dwc_device *)\
316                                                 (hsdevp)->hsdev)
317 
318 enum {
319         SATA_DWC_CMD_ISSUED_NOT         = 0,
320         SATA_DWC_CMD_ISSUED_PEND        = 1,
321         SATA_DWC_CMD_ISSUED_EXEC        = 2,
322         SATA_DWC_CMD_ISSUED_NODATA      = 3,
323 
324         SATA_DWC_DMA_PENDING_NONE       = 0,
325         SATA_DWC_DMA_PENDING_TX         = 1,
326         SATA_DWC_DMA_PENDING_RX         = 2,
327 };
328 
329 struct sata_dwc_host_priv {
330         void    __iomem  *scr_addr_sstatus;
331         u32     sata_dwc_sactive_issued ;
332         u32     sata_dwc_sactive_queued ;
333         u32     dma_interrupt_count;
334         struct  ahb_dma_regs    *sata_dma_regs;
335         struct  device  *dwc_dev;
336         int     dma_channel;
337 };
338 
339 static struct sata_dwc_host_priv host_pvt;
340 
341 /*
342  * Prototypes
343  */
344 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
345 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
346                                 u32 check_status);
347 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
348 static void sata_dwc_port_stop(struct ata_port *ap);
349 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
350 static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq);
351 static void dma_dwc_exit(struct sata_dwc_device *hsdev);
352 static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
353                               struct lli *lli, dma_addr_t dma_lli,
354                               void __iomem *addr, int dir);
355 static void dma_dwc_xfer_start(int dma_ch);
356 
357 static const char *get_prot_descript(u8 protocol)
358 {
359         switch ((enum ata_tf_protocols)protocol) {
360         case ATA_PROT_NODATA:
361                 return "ATA no data";
362         case ATA_PROT_PIO:
363                 return "ATA PIO";
364         case ATA_PROT_DMA:
365                 return "ATA DMA";
366         case ATA_PROT_NCQ:
367                 return "ATA NCQ";
368         case ATAPI_PROT_NODATA:
369                 return "ATAPI no data";
370         case ATAPI_PROT_PIO:
371                 return "ATAPI PIO";
372         case ATAPI_PROT_DMA:
373                 return "ATAPI DMA";
374         default:
375                 return "unknown";
376         }
377 }
378 
379 static const char *get_dma_dir_descript(int dma_dir)
380 {
381         switch ((enum dma_data_direction)dma_dir) {
382         case DMA_BIDIRECTIONAL:
383                 return "bidirectional";
384         case DMA_TO_DEVICE:
385                 return "to device";
386         case DMA_FROM_DEVICE:
387                 return "from device";
388         default:
389                 return "none";
390         }
391 }
392 
393 static void sata_dwc_tf_dump(struct ata_taskfile *tf)
394 {
395         dev_vdbg(host_pvt.dwc_dev, "taskfile cmd: 0x%02x protocol: %s flags:"
396                 "0x%lx device: %x\n", tf->command,
397                 get_prot_descript(tf->protocol), tf->flags, tf->device);
398         dev_vdbg(host_pvt.dwc_dev, "feature: 0x%02x nsect: 0x%x lbal: 0x%x "
399                 "lbam: 0x%x lbah: 0x%x\n", tf->feature, tf->nsect, tf->lbal,
400                  tf->lbam, tf->lbah);
401         dev_vdbg(host_pvt.dwc_dev, "hob_feature: 0x%02x hob_nsect: 0x%x "
402                 "hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
403                 tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
404                 tf->hob_lbah);
405 }
406 
407 /*
408  * Function: get_burst_length_encode
409  * arguments: datalength: length in bytes of data
410  * returns value to be programmed in register corresponding to data length
411  * This value is effectively the log(base 2) of the length
412  */
413 static  int get_burst_length_encode(int datalength)
414 {
415         int items = datalength >> 2;    /* div by 4 to get lword count */
416 
417         if (items >= 64)
418                 return 5;
419 
420         if (items >= 32)
421                 return 4;
422 
423         if (items >= 16)
424                 return 3;
425 
426         if (items >= 8)
427                 return 2;
428 
429         if (items >= 4)
430                 return 1;
431 
432         return 0;
433 }
434 
435 static  void clear_chan_interrupts(int c)
436 {
437         out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.tfr.low),
438                  DMA_CHANNEL(c));
439         out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.block.low),
440                  DMA_CHANNEL(c));
441         out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.srctran.low),
442                  DMA_CHANNEL(c));
443         out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.dsttran.low),
444                  DMA_CHANNEL(c));
445         out_le32(&(host_pvt.sata_dma_regs->interrupt_clear.error.low),
446                  DMA_CHANNEL(c));
447 }
448 
449 /*
450  * Function: dma_request_channel
451  * arguments: None
452  * returns channel number if available else -1
453  * This function assigns the next available DMA channel from the list to the
454  * requester
455  */
456 static int dma_request_channel(void)
457 {
458         /* Check if the channel is not currently in use */
459         if (!(in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) &
460                 DMA_CHANNEL(host_pvt.dma_channel)))
461                 return host_pvt.dma_channel;
462         dev_err(host_pvt.dwc_dev, "%s Channel %d is currently in use\n",
463                 __func__, host_pvt.dma_channel);
464         return -1;
465 }
466 
467 /*
468  * Function: dma_dwc_interrupt
469  * arguments: irq, dev_id, pt_regs
470  * returns channel number if available else -1
471  * Interrupt Handler for DW AHB SATA DMA
472  */
473 static irqreturn_t dma_dwc_interrupt(int irq, void *hsdev_instance)
474 {
475         int chan;
476         u32 tfr_reg, err_reg;
477         unsigned long flags;
478         struct sata_dwc_device *hsdev = hsdev_instance;
479         struct ata_host *host = (struct ata_host *)hsdev->host;
480         struct ata_port *ap;
481         struct sata_dwc_device_port *hsdevp;
482         u8 tag = 0;
483         unsigned int port = 0;
484 
485         spin_lock_irqsave(&host->lock, flags);
486         ap = host->ports[port];
487         hsdevp = HSDEVP_FROM_AP(ap);
488         tag = ap->link.active_tag;
489 
490         tfr_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.tfr\
491                         .low));
492         err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error\
493                         .low));
494 
495         dev_dbg(ap->dev, "eot=0x%08x err=0x%08x pending=%d active port=%d\n",
496                 tfr_reg, err_reg, hsdevp->dma_pending[tag], port);
497 
498         chan = host_pvt.dma_channel;
499         if (chan >= 0) {
500                 /* Check for end-of-transfer interrupt. */
501                 if (tfr_reg & DMA_CHANNEL(chan)) {
502                         /*
503                          * Each DMA command produces 2 interrupts.  Only
504                          * complete the command after both interrupts have been
505                          * seen. (See sata_dwc_isr())
506                          */
507                         host_pvt.dma_interrupt_count++;
508                         sata_dwc_clear_dmacr(hsdevp, tag);
509 
510                         if (hsdevp->dma_pending[tag] ==
511                             SATA_DWC_DMA_PENDING_NONE) {
512                                 dev_err(ap->dev, "DMA not pending eot=0x%08x "
513                                         "err=0x%08x tag=0x%02x pending=%d\n",
514                                         tfr_reg, err_reg, tag,
515                                         hsdevp->dma_pending[tag]);
516                         }
517 
518                         if ((host_pvt.dma_interrupt_count % 2) == 0)
519                                 sata_dwc_dma_xfer_complete(ap, 1);
520 
521                         /* Clear the interrupt */
522                         out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
523                                 .tfr.low),
524                                  DMA_CHANNEL(chan));
525                 }
526 
527                 /* Check for error interrupt. */
528                 if (err_reg & DMA_CHANNEL(chan)) {
529                         /* TODO Need error handler ! */
530                         dev_err(ap->dev, "error interrupt err_reg=0x%08x\n",
531                                 err_reg);
532 
533                         /* Clear the interrupt. */
534                         out_le32(&(host_pvt.sata_dma_regs->interrupt_clear\
535                                 .error.low),
536                                  DMA_CHANNEL(chan));
537                 }
538         }
539         spin_unlock_irqrestore(&host->lock, flags);
540         return IRQ_HANDLED;
541 }
542 
543 /*
544  * Function: dma_request_interrupts
545  * arguments: hsdev
546  * returns status
547  * This function registers ISR for a particular DMA channel interrupt
548  */
549 static int dma_request_interrupts(struct sata_dwc_device *hsdev, int irq)
550 {
551         int retval = 0;
552         int chan = host_pvt.dma_channel;
553 
554         if (chan >= 0) {
555                 /* Unmask error interrupt */
556                 out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.error.low,
557                          DMA_ENABLE_CHAN(chan));
558 
559                 /* Unmask end-of-transfer interrupt */
560                 out_le32(&(host_pvt.sata_dma_regs)->interrupt_mask.tfr.low,
561                          DMA_ENABLE_CHAN(chan));
562         }
563 
564         retval = request_irq(irq, dma_dwc_interrupt, 0, "SATA DMA", hsdev);
565         if (retval) {
566                 dev_err(host_pvt.dwc_dev, "%s: could not get IRQ %d\n",
567                 __func__, irq);
568                 return -ENODEV;
569         }
570 
571         /* Mark this interrupt as requested */
572         hsdev->irq_dma = irq;
573         return 0;
574 }
575 
576 /*
577  * Function: map_sg_to_lli
578  * The Synopsis driver has a comment proposing that better performance
579  * is possible by only enabling interrupts on the last item in the linked list.
580  * However, it seems that could be a problem if an error happened on one of the
581  * first items.  The transfer would halt, but no error interrupt would occur.
582  * Currently this function sets interrupts enabled for each linked list item:
583  * DMA_CTL_INT_EN.
584  */
585 static int map_sg_to_lli(struct scatterlist *sg, int num_elems,
586                         struct lli *lli, dma_addr_t dma_lli,
587                         void __iomem *dmadr_addr, int dir)
588 {
589         int i, idx = 0;
590         int fis_len = 0;
591         dma_addr_t next_llp;
592         int bl;
593         int sms_val, dms_val;
594 
595         sms_val = 0;
596         dms_val = 1 + host_pvt.dma_channel;
597         dev_dbg(host_pvt.dwc_dev,
598                 "%s: sg=%p nelem=%d lli=%p dma_lli=0x%pad dmadr=0x%p\n",
599                 __func__, sg, num_elems, lli, &dma_lli, dmadr_addr);
600 
601         bl = get_burst_length_encode(AHB_DMA_BRST_DFLT);
602 
603         for (i = 0; i < num_elems; i++, sg++) {
604                 u32 addr, offset;
605                 u32 sg_len, len;
606 
607                 addr = (u32) sg_dma_address(sg);
608                 sg_len = sg_dma_len(sg);
609 
610                 dev_dbg(host_pvt.dwc_dev, "%s: elem=%d sg_addr=0x%x sg_len"
611                         "=%d\n", __func__, i, addr, sg_len);
612 
613                 while (sg_len) {
614                         if (idx >= SATA_DWC_DMAC_LLI_NUM) {
615                                 /* The LLI table is not large enough. */
616                                 dev_err(host_pvt.dwc_dev, "LLI table overrun "
617                                 "(idx=%d)\n", idx);
618                                 break;
619                         }
620                         len = (sg_len > SATA_DWC_DMAC_CTRL_TSIZE_MAX) ?
621                                 SATA_DWC_DMAC_CTRL_TSIZE_MAX : sg_len;
622 
623                         offset = addr & 0xffff;
624                         if ((offset + sg_len) > 0x10000)
625                                 len = 0x10000 - offset;
626 
627                         /*
628                          * Make sure a LLI block is not created that will span
629                          * 8K max FIS boundary.  If the block spans such a FIS
630                          * boundary, there is a chance that a DMA burst will
631                          * cross that boundary -- this results in an error in
632                          * the host controller.
633                          */
634                         if (fis_len + len > 8192) {
635                                 dev_dbg(host_pvt.dwc_dev, "SPLITTING: fis_len="
636                                         "%d(0x%x) len=%d(0x%x)\n", fis_len,
637                                          fis_len, len, len);
638                                 len = 8192 - fis_len;
639                                 fis_len = 0;
640                         } else {
641                                 fis_len += len;
642                         }
643                         if (fis_len == 8192)
644                                 fis_len = 0;
645 
646                         /*
647                          * Set DMA addresses and lower half of control register
648                          * based on direction.
649                          */
650                         if (dir == DMA_FROM_DEVICE) {
651                                 lli[idx].dar = cpu_to_le32(addr);
652                                 lli[idx].sar = cpu_to_le32((u32)dmadr_addr);
653 
654                                 lli[idx].ctl.low = cpu_to_le32(
655                                         DMA_CTL_TTFC(DMA_CTL_TTFC_P2M_DMAC) |
656                                         DMA_CTL_SMS(sms_val) |
657                                         DMA_CTL_DMS(dms_val) |
658                                         DMA_CTL_SRC_MSIZE(bl) |
659                                         DMA_CTL_DST_MSIZE(bl) |
660                                         DMA_CTL_SINC_NOCHANGE |
661                                         DMA_CTL_SRC_TRWID(2) |
662                                         DMA_CTL_DST_TRWID(2) |
663                                         DMA_CTL_INT_EN |
664                                         DMA_CTL_LLP_SRCEN |
665                                         DMA_CTL_LLP_DSTEN);
666                         } else {        /* DMA_TO_DEVICE */
667                                 lli[idx].sar = cpu_to_le32(addr);
668                                 lli[idx].dar = cpu_to_le32((u32)dmadr_addr);
669 
670                                 lli[idx].ctl.low = cpu_to_le32(
671                                         DMA_CTL_TTFC(DMA_CTL_TTFC_M2P_PER) |
672                                         DMA_CTL_SMS(dms_val) |
673                                         DMA_CTL_DMS(sms_val) |
674                                         DMA_CTL_SRC_MSIZE(bl) |
675                                         DMA_CTL_DST_MSIZE(bl) |
676                                         DMA_CTL_DINC_NOCHANGE |
677                                         DMA_CTL_SRC_TRWID(2) |
678                                         DMA_CTL_DST_TRWID(2) |
679                                         DMA_CTL_INT_EN |
680                                         DMA_CTL_LLP_SRCEN |
681                                         DMA_CTL_LLP_DSTEN);
682                         }
683 
684                         dev_dbg(host_pvt.dwc_dev, "%s setting ctl.high len: "
685                                 "0x%08x val: 0x%08x\n", __func__,
686                                 len, DMA_CTL_BLK_TS(len / 4));
687 
688                         /* Program the LLI CTL high register */
689                         lli[idx].ctl.high = cpu_to_le32(DMA_CTL_BLK_TS\
690                                                 (len / 4));
691 
692                         /* Program the next pointer.  The next pointer must be
693                          * the physical address, not the virtual address.
694                          */
695                         next_llp = (dma_lli + ((idx + 1) * sizeof(struct \
696                                                         lli)));
697 
698                         /* The last 2 bits encode the list master select. */
699                         next_llp = DMA_LLP_LMS(next_llp, DMA_LLP_AHBMASTER2);
700 
701                         lli[idx].llp = cpu_to_le32(next_llp);
702                         idx++;
703                         sg_len -= len;
704                         addr += len;
705                 }
706         }
707 
708         /*
709          * The last next ptr has to be zero and the last control low register
710          * has to have LLP_SRC_EN and LLP_DST_EN (linked list pointer source
711          * and destination enable) set back to 0 (disabled.) This is what tells
712          * the core that this is the last item in the linked list.
713          */
714         if (idx) {
715                 lli[idx-1].llp = 0x00000000;
716                 lli[idx-1].ctl.low &= DMA_CTL_LLP_DISABLE_LE32;
717 
718                 /* Flush cache to memory */
719                 dma_cache_sync(NULL, lli, (sizeof(struct lli) * idx),
720                                DMA_BIDIRECTIONAL);
721         }
722 
723         return idx;
724 }
725 
726 /*
727  * Function: dma_dwc_xfer_start
728  * arguments: Channel number
729  * Return : None
730  * Enables the DMA channel
731  */
732 static void dma_dwc_xfer_start(int dma_ch)
733 {
734         /* Enable the DMA channel */
735         out_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low),
736                  in_le32(&(host_pvt.sata_dma_regs->dma_chan_en.low)) |
737                  DMA_ENABLE_CHAN(dma_ch));
738 }
739 
740 static int dma_dwc_xfer_setup(struct scatterlist *sg, int num_elems,
741                               struct lli *lli, dma_addr_t dma_lli,
742                               void __iomem *addr, int dir)
743 {
744         int dma_ch;
745         int num_lli;
746         /* Acquire DMA channel */
747         dma_ch = dma_request_channel();
748         if (dma_ch == -1) {
749                 dev_err(host_pvt.dwc_dev, "%s: dma channel unavailable\n",
750                          __func__);
751                 return -EAGAIN;
752         }
753 
754         /* Convert SG list to linked list of items (LLIs) for AHB DMA */
755         num_lli = map_sg_to_lli(sg, num_elems, lli, dma_lli, addr, dir);
756 
757         dev_dbg(host_pvt.dwc_dev, "%s sg: 0x%p, count: %d lli: %p dma_lli:"
758                 " 0x%0xlx addr: %p lli count: %d\n", __func__, sg, num_elems,
759                  lli, (u32)dma_lli, addr, num_lli);
760 
761         clear_chan_interrupts(dma_ch);
762 
763         /* Program the CFG register. */
764         out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.high),
765                  DMA_CFG_HW_HS_SRC(dma_ch) | DMA_CFG_HW_HS_DEST(dma_ch) |
766                  DMA_CFG_PROTCTL | DMA_CFG_FCMOD_REQ);
767         out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].cfg.low),
768                  DMA_CFG_HW_CH_PRIOR(dma_ch));
769 
770         /* Program the address of the linked list */
771         out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].llp.low),
772                  DMA_LLP_LMS(dma_lli, DMA_LLP_AHBMASTER2));
773 
774         /* Program the CTL register with src enable / dst enable */
775         out_le32(&(host_pvt.sata_dma_regs->chan_regs[dma_ch].ctl.low),
776                  DMA_CTL_LLP_SRCEN | DMA_CTL_LLP_DSTEN);
777         return dma_ch;
778 }
779 
780 /*
781  * Function: dma_dwc_exit
782  * arguments: None
783  * returns status
784  * This function exits the SATA DMA driver
785  */
786 static void dma_dwc_exit(struct sata_dwc_device *hsdev)
787 {
788         dev_dbg(host_pvt.dwc_dev, "%s:\n", __func__);
789         if (host_pvt.sata_dma_regs) {
790                 iounmap((void __iomem *)host_pvt.sata_dma_regs);
791                 host_pvt.sata_dma_regs = NULL;
792         }
793 
794         if (hsdev->irq_dma) {
795                 free_irq(hsdev->irq_dma, hsdev);
796                 hsdev->irq_dma = 0;
797         }
798 }
799 
800 /*
801  * Function: dma_dwc_init
802  * arguments: hsdev
803  * returns status
804  * This function initializes the SATA DMA driver
805  */
806 static int dma_dwc_init(struct sata_dwc_device *hsdev, int irq)
807 {
808         int err;
809 
810         err = dma_request_interrupts(hsdev, irq);
811         if (err) {
812                 dev_err(host_pvt.dwc_dev, "%s: dma_request_interrupts returns"
813                         " %d\n", __func__, err);
814                 return err;
815         }
816 
817         /* Enabe DMA */
818         out_le32(&(host_pvt.sata_dma_regs->dma_cfg.low), DMA_EN);
819 
820         dev_notice(host_pvt.dwc_dev, "DMA initialized\n");
821         dev_dbg(host_pvt.dwc_dev, "SATA DMA registers=0x%p\n", host_pvt.\
822                 sata_dma_regs);
823 
824         return 0;
825 }
826 
827 static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
828 {
829         if (scr > SCR_NOTIFICATION) {
830                 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
831                         __func__, scr);
832                 return -EINVAL;
833         }
834 
835         *val = in_le32(link->ap->ioaddr.scr_addr + (scr * 4));
836         dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
837                 __func__, link->ap->print_id, scr, *val);
838 
839         return 0;
840 }
841 
842 static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
843 {
844         dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=val=0x%08x\n",
845                 __func__, link->ap->print_id, scr, val);
846         if (scr > SCR_NOTIFICATION) {
847                 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
848                          __func__, scr);
849                 return -EINVAL;
850         }
851         out_le32(link->ap->ioaddr.scr_addr + (scr * 4), val);
852 
853         return 0;
854 }
855 
856 static u32 core_scr_read(unsigned int scr)
857 {
858         return in_le32(host_pvt.scr_addr_sstatus + (scr * 4));
859 }
860 
861 static void core_scr_write(unsigned int scr, u32 val)
862 {
863         out_le32(host_pvt.scr_addr_sstatus + (scr * 4), val);
864 }
865 
866 static void clear_serror(void)
867 {
868         u32 val;
869         val = core_scr_read(SCR_ERROR);
870         core_scr_write(SCR_ERROR, val);
871 }
872 
873 static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
874 {
875         out_le32(&hsdev->sata_dwc_regs->intpr,
876                  in_le32(&hsdev->sata_dwc_regs->intpr));
877 }
878 
879 static u32 qcmd_tag_to_mask(u8 tag)
880 {
881         return 0x00000001 << (tag & 0x1f);
882 }
883 
884 /* See ahci.c */
885 static void sata_dwc_error_intr(struct ata_port *ap,
886                                 struct sata_dwc_device *hsdev, uint intpr)
887 {
888         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
889         struct ata_eh_info *ehi = &ap->link.eh_info;
890         unsigned int err_mask = 0, action = 0;
891         struct ata_queued_cmd *qc;
892         u32 serror;
893         u8 status, tag;
894         u32 err_reg;
895 
896         ata_ehi_clear_desc(ehi);
897 
898         serror = core_scr_read(SCR_ERROR);
899         status = ap->ops->sff_check_status(ap);
900 
901         err_reg = in_le32(&(host_pvt.sata_dma_regs->interrupt_status.error.\
902                         low));
903         tag = ap->link.active_tag;
904 
905         dev_err(ap->dev, "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x "
906                 "dma_intp=%d pending=%d issued=%d dma_err_status=0x%08x\n",
907                 __func__, serror, intpr, status, host_pvt.dma_interrupt_count,
908                 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag], err_reg);
909 
910         /* Clear error register and interrupt bit */
911         clear_serror();
912         clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
913 
914         /* This is the only error happening now.  TODO check for exact error */
915 
916         err_mask |= AC_ERR_HOST_BUS;
917         action |= ATA_EH_RESET;
918 
919         /* Pass this on to EH */
920         ehi->serror |= serror;
921         ehi->action |= action;
922 
923         qc = ata_qc_from_tag(ap, tag);
924         if (qc)
925                 qc->err_mask |= err_mask;
926         else
927                 ehi->err_mask |= err_mask;
928 
929         ata_port_abort(ap);
930 }
931 
932 /*
933  * Function : sata_dwc_isr
934  * arguments : irq, void *dev_instance, struct pt_regs *regs
935  * Return value : irqreturn_t - status of IRQ
936  * This Interrupt handler called via port ops registered function.
937  * .irq_handler = sata_dwc_isr
938  */
939 static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
940 {
941         struct ata_host *host = (struct ata_host *)dev_instance;
942         struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
943         struct ata_port *ap;
944         struct ata_queued_cmd *qc;
945         unsigned long flags;
946         u8 status, tag;
947         int handled, num_processed, port = 0;
948         uint intpr, sactive, sactive2, tag_mask;
949         struct sata_dwc_device_port *hsdevp;
950         host_pvt.sata_dwc_sactive_issued = 0;
951 
952         spin_lock_irqsave(&host->lock, flags);
953 
954         /* Read the interrupt register */
955         intpr = in_le32(&hsdev->sata_dwc_regs->intpr);
956 
957         ap = host->ports[port];
958         hsdevp = HSDEVP_FROM_AP(ap);
959 
960         dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
961                 ap->link.active_tag);
962 
963         /* Check for error interrupt */
964         if (intpr & SATA_DWC_INTPR_ERR) {
965                 sata_dwc_error_intr(ap, hsdev, intpr);
966                 handled = 1;
967                 goto DONE;
968         }
969 
970         /* Check for DMA SETUP FIS (FP DMA) interrupt */
971         if (intpr & SATA_DWC_INTPR_NEWFP) {
972                 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
973 
974                 tag = (u8)(in_le32(&hsdev->sata_dwc_regs->fptagr));
975                 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
976                 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
977                         dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
978 
979                 host_pvt.sata_dwc_sactive_issued |= qcmd_tag_to_mask(tag);
980 
981                 qc = ata_qc_from_tag(ap, tag);
982                 /*
983                  * Start FP DMA for NCQ command.  At this point the tag is the
984                  * active tag.  It is the tag that matches the command about to
985                  * be completed.
986                  */
987                 qc->ap->link.active_tag = tag;
988                 sata_dwc_bmdma_start_by_tag(qc, tag);
989 
990                 handled = 1;
991                 goto DONE;
992         }
993         sactive = core_scr_read(SCR_ACTIVE);
994         tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
995 
996         /* If no sactive issued and tag_mask is zero then this is not NCQ */
997         if (host_pvt.sata_dwc_sactive_issued == 0 && tag_mask == 0) {
998                 if (ap->link.active_tag == ATA_TAG_POISON)
999                         tag = 0;
1000                 else
1001                         tag = ap->link.active_tag;
1002                 qc = ata_qc_from_tag(ap, tag);
1003 
1004                 /* DEV interrupt w/ no active qc? */
1005                 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
1006                         dev_err(ap->dev, "%s interrupt with no active qc "
1007                                 "qc=%p\n", __func__, qc);
1008                         ap->ops->sff_check_status(ap);
1009                         handled = 1;
1010                         goto DONE;
1011                 }
1012                 status = ap->ops->sff_check_status(ap);
1013 
1014                 qc->ap->link.active_tag = tag;
1015                 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
1016 
1017                 if (status & ATA_ERR) {
1018                         dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
1019                         sata_dwc_qc_complete(ap, qc, 1);
1020                         handled = 1;
1021                         goto DONE;
1022                 }
1023 
1024                 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
1025                         __func__, get_prot_descript(qc->tf.protocol));
1026 DRVSTILLBUSY:
1027                 if (ata_is_dma(qc->tf.protocol)) {
1028                         /*
1029                          * Each DMA transaction produces 2 interrupts. The DMAC
1030                          * transfer complete interrupt and the SATA controller
1031                          * operation done interrupt. The command should be
1032                          * completed only after both interrupts are seen.
1033                          */
1034                         host_pvt.dma_interrupt_count++;
1035                         if (hsdevp->dma_pending[tag] == \
1036                                         SATA_DWC_DMA_PENDING_NONE) {
1037                                 dev_err(ap->dev, "%s: DMA not pending "
1038                                         "intpr=0x%08x status=0x%08x pending"
1039                                         "=%d\n", __func__, intpr, status,
1040                                         hsdevp->dma_pending[tag]);
1041                         }
1042 
1043                         if ((host_pvt.dma_interrupt_count % 2) == 0)
1044                                 sata_dwc_dma_xfer_complete(ap, 1);
1045                 } else if (ata_is_pio(qc->tf.protocol)) {
1046                         ata_sff_hsm_move(ap, qc, status, 0);
1047                         handled = 1;
1048                         goto DONE;
1049                 } else {
1050                         if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
1051                                 goto DRVSTILLBUSY;
1052                 }
1053 
1054                 handled = 1;
1055                 goto DONE;
1056         }
1057 
1058         /*
1059          * This is a NCQ command. At this point we need to figure out for which
1060          * tags we have gotten a completion interrupt.  One interrupt may serve
1061          * as completion for more than one operation when commands are queued
1062          * (NCQ).  We need to process each completed command.
1063          */
1064 
1065          /* process completed commands */
1066         sactive = core_scr_read(SCR_ACTIVE);
1067         tag_mask = (host_pvt.sata_dwc_sactive_issued | sactive) ^ sactive;
1068 
1069         if (sactive != 0 || (host_pvt.sata_dwc_sactive_issued) > 1 || \
1070                                                         tag_mask > 1) {
1071                 dev_dbg(ap->dev, "%s NCQ:sactive=0x%08x  sactive_issued=0x%08x"
1072                         "tag_mask=0x%08x\n", __func__, sactive,
1073                         host_pvt.sata_dwc_sactive_issued, tag_mask);
1074         }
1075 
1076         if ((tag_mask | (host_pvt.sata_dwc_sactive_issued)) != \
1077                                         (host_pvt.sata_dwc_sactive_issued)) {
1078                 dev_warn(ap->dev, "Bad tag mask?  sactive=0x%08x "
1079                          "(host_pvt.sata_dwc_sactive_issued)=0x%08x  tag_mask"
1080                          "=0x%08x\n", sactive, host_pvt.sata_dwc_sactive_issued,
1081                           tag_mask);
1082         }
1083 
1084         /* read just to clear ... not bad if currently still busy */
1085         status = ap->ops->sff_check_status(ap);
1086         dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
1087 
1088         tag = 0;
1089         num_processed = 0;
1090         while (tag_mask) {
1091                 num_processed++;
1092                 while (!(tag_mask & 0x00000001)) {
1093                         tag++;
1094                         tag_mask <<= 1;
1095                 }
1096 
1097                 tag_mask &= (~0x00000001);
1098                 qc = ata_qc_from_tag(ap, tag);
1099 
1100                 /* To be picked up by completion functions */
1101                 qc->ap->link.active_tag = tag;
1102                 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
1103 
1104                 /* Let libata/scsi layers handle error */
1105                 if (status & ATA_ERR) {
1106                         dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
1107                                 status);
1108                         sata_dwc_qc_complete(ap, qc, 1);
1109                         handled = 1;
1110                         goto DONE;
1111                 }
1112 
1113                 /* Process completed command */
1114                 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
1115                         get_prot_descript(qc->tf.protocol));
1116                 if (ata_is_dma(qc->tf.protocol)) {
1117                         host_pvt.dma_interrupt_count++;
1118                         if (hsdevp->dma_pending[tag] == \
1119                                         SATA_DWC_DMA_PENDING_NONE)
1120                                 dev_warn(ap->dev, "%s: DMA not pending?\n",
1121                                         __func__);
1122                         if ((host_pvt.dma_interrupt_count % 2) == 0)
1123                                 sata_dwc_dma_xfer_complete(ap, 1);
1124                 } else {
1125                         if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
1126                                 goto STILLBUSY;
1127                 }
1128                 continue;
1129 
1130 STILLBUSY:
1131                 ap->stats.idle_irq++;
1132                 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
1133                         ap->print_id);
1134         } /* while tag_mask */
1135 
1136         /*
1137          * Check to see if any commands completed while we were processing our
1138          * initial set of completed commands (read status clears interrupts,
1139          * so we might miss a completed command interrupt if one came in while
1140          * we were processing --we read status as part of processing a completed
1141          * command).
1142          */
1143         sactive2 = core_scr_read(SCR_ACTIVE);
1144         if (sactive2 != sactive) {
1145                 dev_dbg(ap->dev, "More completed - sactive=0x%x sactive2"
1146                         "=0x%x\n", sactive, sactive2);
1147         }
1148         handled = 1;
1149 
1150 DONE:
1151         spin_unlock_irqrestore(&host->lock, flags);
1152         return IRQ_RETVAL(handled);
1153 }
1154 
1155 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
1156 {
1157         struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
1158 
1159         if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
1160                 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1161                          SATA_DWC_DMACR_RX_CLEAR(
1162                                  in_le32(&(hsdev->sata_dwc_regs->dmacr))));
1163         } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
1164                 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1165                          SATA_DWC_DMACR_TX_CLEAR(
1166                                  in_le32(&(hsdev->sata_dwc_regs->dmacr))));
1167         } else {
1168                 /*
1169                  * This should not happen, it indicates the driver is out of
1170                  * sync.  If it does happen, clear dmacr anyway.
1171                  */
1172                 dev_err(host_pvt.dwc_dev, "%s DMA protocol RX and"
1173                         "TX DMA not pending tag=0x%02x pending=%d"
1174                         " dmacr: 0x%08x\n", __func__, tag,
1175                         hsdevp->dma_pending[tag],
1176                         in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1177                 out_le32(&(hsdev->sata_dwc_regs->dmacr),
1178                         SATA_DWC_DMACR_TXRXCH_CLEAR);
1179         }
1180 }
1181 
1182 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
1183 {
1184         struct ata_queued_cmd *qc;
1185         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1186         struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1187         u8 tag = 0;
1188 
1189         tag = ap->link.active_tag;
1190         qc = ata_qc_from_tag(ap, tag);
1191         if (!qc) {
1192                 dev_err(ap->dev, "failed to get qc");
1193                 return;
1194         }
1195 
1196 #ifdef DEBUG_NCQ
1197         if (tag > 0) {
1198                 dev_info(ap->dev, "%s tag=%u cmd=0x%02x dma dir=%s proto=%s "
1199                          "dmacr=0x%08x\n", __func__, qc->tag, qc->tf.command,
1200                          get_dma_dir_descript(qc->dma_dir),
1201                          get_prot_descript(qc->tf.protocol),
1202                          in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1203         }
1204 #endif
1205 
1206         if (ata_is_dma(qc->tf.protocol)) {
1207                 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
1208                         dev_err(ap->dev, "%s DMA protocol RX and TX DMA not "
1209                                 "pending dmacr: 0x%08x\n", __func__,
1210                                 in_le32(&(hsdev->sata_dwc_regs->dmacr)));
1211                 }
1212 
1213                 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
1214                 sata_dwc_qc_complete(ap, qc, check_status);
1215                 ap->link.active_tag = ATA_TAG_POISON;
1216         } else {
1217                 sata_dwc_qc_complete(ap, qc, check_status);
1218         }
1219 }
1220 
1221 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
1222                                 u32 check_status)
1223 {
1224         u8 status = 0;
1225         u32 mask = 0x0;
1226         u8 tag = qc->tag;
1227         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1228         host_pvt.sata_dwc_sactive_queued = 0;
1229         dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
1230 
1231         if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
1232                 dev_err(ap->dev, "TX DMA PENDING\n");
1233         else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
1234                 dev_err(ap->dev, "RX DMA PENDING\n");
1235         dev_dbg(ap->dev, "QC complete cmd=0x%02x status=0x%02x ata%u:"
1236                 " protocol=%d\n", qc->tf.command, status, ap->print_id,
1237                  qc->tf.protocol);
1238 
1239         /* clear active bit */
1240         mask = (~(qcmd_tag_to_mask(tag)));
1241         host_pvt.sata_dwc_sactive_queued = (host_pvt.sata_dwc_sactive_queued) \
1242                                                 & mask;
1243         host_pvt.sata_dwc_sactive_issued = (host_pvt.sata_dwc_sactive_issued) \
1244                                                 & mask;
1245         ata_qc_complete(qc);
1246         return 0;
1247 }
1248 
1249 static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
1250 {
1251         /* Enable selective interrupts by setting the interrupt maskregister*/
1252         out_le32(&hsdev->sata_dwc_regs->intmr,
1253                  SATA_DWC_INTMR_ERRM |
1254                  SATA_DWC_INTMR_NEWFPM |
1255                  SATA_DWC_INTMR_PMABRTM |
1256                  SATA_DWC_INTMR_DMATM);
1257         /*
1258          * Unmask the error bits that should trigger an error interrupt by
1259          * setting the error mask register.
1260          */
1261         out_le32(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
1262 
1263         dev_dbg(host_pvt.dwc_dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
1264                  __func__, in_le32(&hsdev->sata_dwc_regs->intmr),
1265                 in_le32(&hsdev->sata_dwc_regs->errmr));
1266 }
1267 
1268 static void sata_dwc_setup_port(struct ata_ioports *port, unsigned long base)
1269 {
1270         port->cmd_addr = (void __iomem *)base + 0x00;
1271         port->data_addr = (void __iomem *)base + 0x00;
1272 
1273         port->error_addr = (void __iomem *)base + 0x04;
1274         port->feature_addr = (void __iomem *)base + 0x04;
1275 
1276         port->nsect_addr = (void __iomem *)base + 0x08;
1277 
1278         port->lbal_addr = (void __iomem *)base + 0x0c;
1279         port->lbam_addr = (void __iomem *)base + 0x10;
1280         port->lbah_addr = (void __iomem *)base + 0x14;
1281 
1282         port->device_addr = (void __iomem *)base + 0x18;
1283         port->command_addr = (void __iomem *)base + 0x1c;
1284         port->status_addr = (void __iomem *)base + 0x1c;
1285 
1286         port->altstatus_addr = (void __iomem *)base + 0x20;
1287         port->ctl_addr = (void __iomem *)base + 0x20;
1288 }
1289 
1290 /*
1291  * Function : sata_dwc_port_start
1292  * arguments : struct ata_ioports *port
1293  * Return value : returns 0 if success, error code otherwise
1294  * This function allocates the scatter gather LLI table for AHB DMA
1295  */
1296 static int sata_dwc_port_start(struct ata_port *ap)
1297 {
1298         int err = 0;
1299         struct sata_dwc_device *hsdev;
1300         struct sata_dwc_device_port *hsdevp = NULL;
1301         struct device *pdev;
1302         int i;
1303 
1304         hsdev = HSDEV_FROM_AP(ap);
1305 
1306         dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
1307 
1308         hsdev->host = ap->host;
1309         pdev = ap->host->dev;
1310         if (!pdev) {
1311                 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
1312                 err = -ENODEV;
1313                 goto CLEANUP;
1314         }
1315 
1316         /* Allocate Port Struct */
1317         hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
1318         if (!hsdevp) {
1319                 dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__);
1320                 err = -ENOMEM;
1321                 goto CLEANUP;
1322         }
1323         hsdevp->hsdev = hsdev;
1324 
1325         for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
1326                 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
1327 
1328         ap->bmdma_prd = NULL;   /* set these so libata doesn't use them */
1329         ap->bmdma_prd_dma = 0;
1330 
1331         /*
1332          * DMA - Assign scatter gather LLI table. We can't use the libata
1333          * version since it's PRD is IDE PCI specific.
1334          */
1335         for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
1336                 hsdevp->llit[i] = dma_alloc_coherent(pdev,
1337                                                      SATA_DWC_DMAC_LLI_TBL_SZ,
1338                                                      &(hsdevp->llit_dma[i]),
1339                                                      GFP_ATOMIC);
1340                 if (!hsdevp->llit[i]) {
1341                         dev_err(ap->dev, "%s: dma_alloc_coherent failed\n",
1342                                  __func__);
1343                         err = -ENOMEM;
1344                         goto CLEANUP_ALLOC;
1345                 }
1346         }
1347 
1348         if (ap->port_no == 0)  {
1349                 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
1350                         __func__);
1351                 out_le32(&hsdev->sata_dwc_regs->dmacr,
1352                          SATA_DWC_DMACR_TXRXCH_CLEAR);
1353 
1354                 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
1355                          __func__);
1356                 out_le32(&hsdev->sata_dwc_regs->dbtsr,
1357                          (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1358                           SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
1359         }
1360 
1361         /* Clear any error bits before libata starts issuing commands */
1362         clear_serror();
1363         ap->private_data = hsdevp;
1364         dev_dbg(ap->dev, "%s: done\n", __func__);
1365         return 0;
1366 
1367 CLEANUP_ALLOC:
1368         kfree(hsdevp);
1369 CLEANUP:
1370         dev_dbg(ap->dev, "%s: fail. ap->id = %d\n", __func__, ap->print_id);
1371         return err;
1372 }
1373 
1374 static void sata_dwc_port_stop(struct ata_port *ap)
1375 {
1376         int i;
1377         struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1378         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1379 
1380         dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
1381 
1382         if (hsdevp && hsdev) {
1383                 /* deallocate LLI table */
1384                 for (i = 0; i < SATA_DWC_QCMD_MAX; i++) {
1385                         dma_free_coherent(ap->host->dev,
1386                                           SATA_DWC_DMAC_LLI_TBL_SZ,
1387                                          hsdevp->llit[i], hsdevp->llit_dma[i]);
1388                 }
1389 
1390                 kfree(hsdevp);
1391         }
1392         ap->private_data = NULL;
1393 }
1394 
1395 /*
1396  * Function : sata_dwc_exec_command_by_tag
1397  * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
1398  * Return value : None
1399  * This function keeps track of individual command tag ids and calls
1400  * ata_exec_command in libata
1401  */
1402 static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
1403                                          struct ata_taskfile *tf,
1404                                          u8 tag, u32 cmd_issued)
1405 {
1406         unsigned long flags;
1407         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1408 
1409         dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
1410                 ata_get_cmd_descript(tf->command), tag);
1411 
1412         spin_lock_irqsave(&ap->host->lock, flags);
1413         hsdevp->cmd_issued[tag] = cmd_issued;
1414         spin_unlock_irqrestore(&ap->host->lock, flags);
1415         /*
1416          * Clear SError before executing a new command.
1417          * sata_dwc_scr_write and read can not be used here. Clearing the PM
1418          * managed SError register for the disk needs to be done before the
1419          * task file is loaded.
1420          */
1421         clear_serror();
1422         ata_sff_exec_command(ap, tf);
1423 }
1424 
1425 static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
1426 {
1427         sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
1428                                      SATA_DWC_CMD_ISSUED_PEND);
1429 }
1430 
1431 static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
1432 {
1433         u8 tag = qc->tag;
1434 
1435         if (ata_is_ncq(qc->tf.protocol)) {
1436                 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1437                         __func__, qc->ap->link.sactive, tag);
1438         } else {
1439                 tag = 0;
1440         }
1441         sata_dwc_bmdma_setup_by_tag(qc, tag);
1442 }
1443 
1444 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
1445 {
1446         int start_dma;
1447         u32 reg, dma_chan;
1448         struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
1449         struct ata_port *ap = qc->ap;
1450         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1451         int dir = qc->dma_dir;
1452         dma_chan = hsdevp->dma_chan[tag];
1453 
1454         if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
1455                 start_dma = 1;
1456                 if (dir == DMA_TO_DEVICE)
1457                         hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
1458                 else
1459                         hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
1460         } else {
1461                 dev_err(ap->dev, "%s: Command not pending cmd_issued=%d "
1462                         "(tag=%d) DMA NOT started\n", __func__,
1463                         hsdevp->cmd_issued[tag], tag);
1464                 start_dma = 0;
1465         }
1466 
1467         dev_dbg(ap->dev, "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s "
1468                 "start_dma? %x\n", __func__, qc, tag, qc->tf.command,
1469                 get_dma_dir_descript(qc->dma_dir), start_dma);
1470         sata_dwc_tf_dump(&(qc->tf));
1471 
1472         if (start_dma) {
1473                 reg = core_scr_read(SCR_ERROR);
1474                 if (reg & SATA_DWC_SERROR_ERR_BITS) {
1475                         dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
1476                                 __func__, reg);
1477                 }
1478 
1479                 if (dir == DMA_TO_DEVICE)
1480                         out_le32(&hsdev->sata_dwc_regs->dmacr,
1481                                 SATA_DWC_DMACR_TXCHEN);
1482                 else
1483                         out_le32(&hsdev->sata_dwc_regs->dmacr,
1484                                 SATA_DWC_DMACR_RXCHEN);
1485 
1486                 /* Enable AHB DMA transfer on the specified channel */
1487                 dma_dwc_xfer_start(dma_chan);
1488         }
1489 }
1490 
1491 static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
1492 {
1493         u8 tag = qc->tag;
1494 
1495         if (ata_is_ncq(qc->tf.protocol)) {
1496                 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1497                         __func__, qc->ap->link.sactive, tag);
1498         } else {
1499                 tag = 0;
1500         }
1501         dev_dbg(qc->ap->dev, "%s\n", __func__);
1502         sata_dwc_bmdma_start_by_tag(qc, tag);
1503 }
1504 
1505 /*
1506  * Function : sata_dwc_qc_prep_by_tag
1507  * arguments : ata_queued_cmd *qc, u8 tag
1508  * Return value : None
1509  * qc_prep for a particular queued command based on tag
1510  */
1511 static void sata_dwc_qc_prep_by_tag(struct ata_queued_cmd *qc, u8 tag)
1512 {
1513         struct scatterlist *sg = qc->sg;
1514         struct ata_port *ap = qc->ap;
1515         int dma_chan;
1516         struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
1517         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1518 
1519         dev_dbg(ap->dev, "%s: port=%d dma dir=%s n_elem=%d\n",
1520                 __func__, ap->port_no, get_dma_dir_descript(qc->dma_dir),
1521                  qc->n_elem);
1522 
1523         dma_chan = dma_dwc_xfer_setup(sg, qc->n_elem, hsdevp->llit[tag],
1524                                       hsdevp->llit_dma[tag],
1525                                       (void __iomem *)&hsdev->sata_dwc_regs->dmadr,
1526                                       qc->dma_dir);
1527         if (dma_chan < 0) {
1528                 dev_err(ap->dev, "%s: dma_dwc_xfer_setup returns err %d\n",
1529                         __func__, dma_chan);
1530                 return;
1531         }
1532         hsdevp->dma_chan[tag] = dma_chan;
1533 }
1534 
1535 static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1536 {
1537         u32 sactive;
1538         u8 tag = qc->tag;
1539         struct ata_port *ap = qc->ap;
1540 
1541 #ifdef DEBUG_NCQ
1542         if (qc->tag > 0 || ap->link.sactive > 1)
1543                 dev_info(ap->dev, "%s ap id=%d cmd(0x%02x)=%s qc tag=%d "
1544                          "prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
1545                          __func__, ap->print_id, qc->tf.command,
1546                          ata_get_cmd_descript(qc->tf.command),
1547                          qc->tag, get_prot_descript(qc->tf.protocol),
1548                          ap->link.active_tag, ap->link.sactive);
1549 #endif
1550 
1551         if (!ata_is_ncq(qc->tf.protocol))
1552                 tag = 0;
1553         sata_dwc_qc_prep_by_tag(qc, tag);
1554 
1555         if (ata_is_ncq(qc->tf.protocol)) {
1556                 sactive = core_scr_read(SCR_ACTIVE);
1557                 sactive |= (0x00000001 << tag);
1558                 core_scr_write(SCR_ACTIVE, sactive);
1559 
1560                 dev_dbg(qc->ap->dev, "%s: tag=%d ap->link.sactive = 0x%08x "
1561                         "sactive=0x%08x\n", __func__, tag, qc->ap->link.sactive,
1562                         sactive);
1563 
1564                 ap->ops->sff_tf_load(ap, &qc->tf);
1565                 sata_dwc_exec_command_by_tag(ap, &qc->tf, qc->tag,
1566                                              SATA_DWC_CMD_ISSUED_PEND);
1567         } else {
1568                 ata_sff_qc_issue(qc);
1569         }
1570         return 0;
1571 }
1572 
1573 /*
1574  * Function : sata_dwc_qc_prep
1575  * arguments : ata_queued_cmd *qc
1576  * Return value : None
1577  * qc_prep for a particular queued command
1578  */
1579 
1580 static void sata_dwc_qc_prep(struct ata_queued_cmd *qc)
1581 {
1582         if ((qc->dma_dir == DMA_NONE) || (qc->tf.protocol == ATA_PROT_PIO))
1583                 return;
1584 
1585 #ifdef DEBUG_NCQ
1586         if (qc->tag > 0)
1587                 dev_info(qc->ap->dev, "%s: qc->tag=%d ap->active_tag=0x%08x\n",
1588                          __func__, qc->tag, qc->ap->link.active_tag);
1589 
1590         return ;
1591 #endif
1592 }
1593 
1594 static void sata_dwc_error_handler(struct ata_port *ap)
1595 {
1596         ata_sff_error_handler(ap);
1597 }
1598 
1599 static int sata_dwc_hardreset(struct ata_link *link, unsigned int *class,
1600                               unsigned long deadline)
1601 {
1602         struct sata_dwc_device *hsdev = HSDEV_FROM_AP(link->ap);
1603         int ret;
1604 
1605         ret = sata_sff_hardreset(link, class, deadline);
1606 
1607         sata_dwc_enable_interrupts(hsdev);
1608 
1609         /* Reconfigure the DMA control register */
1610         out_le32(&hsdev->sata_dwc_regs->dmacr,
1611                  SATA_DWC_DMACR_TXRXCH_CLEAR);
1612 
1613         /* Reconfigure the DMA Burst Transaction Size register */
1614         out_le32(&hsdev->sata_dwc_regs->dbtsr,
1615                  SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1616                  SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
1617 
1618         return ret;
1619 }
1620 
1621 /*
1622  * scsi mid-layer and libata interface structures
1623  */
1624 static struct scsi_host_template sata_dwc_sht = {
1625         ATA_NCQ_SHT(DRV_NAME),
1626         /*
1627          * test-only: Currently this driver doesn't handle NCQ
1628          * correctly. We enable NCQ but set the queue depth to a
1629          * max of 1. This will get fixed in in a future release.
1630          */
1631         .sg_tablesize           = LIBATA_MAX_PRD,
1632         /* .can_queue           = ATA_MAX_QUEUE, */
1633         .dma_boundary           = ATA_DMA_BOUNDARY,
1634 };
1635 
1636 static struct ata_port_operations sata_dwc_ops = {
1637         .inherits               = &ata_sff_port_ops,
1638 
1639         .error_handler          = sata_dwc_error_handler,
1640         .hardreset              = sata_dwc_hardreset,
1641 
1642         .qc_prep                = sata_dwc_qc_prep,
1643         .qc_issue               = sata_dwc_qc_issue,
1644 
1645         .scr_read               = sata_dwc_scr_read,
1646         .scr_write              = sata_dwc_scr_write,
1647 
1648         .port_start             = sata_dwc_port_start,
1649         .port_stop              = sata_dwc_port_stop,
1650 
1651         .bmdma_setup            = sata_dwc_bmdma_setup,
1652         .bmdma_start            = sata_dwc_bmdma_start,
1653 };
1654 
1655 static const struct ata_port_info sata_dwc_port_info[] = {
1656         {
1657                 .flags          = ATA_FLAG_SATA | ATA_FLAG_NCQ,
1658                 .pio_mask       = ATA_PIO4,
1659                 .udma_mask      = ATA_UDMA6,
1660                 .port_ops       = &sata_dwc_ops,
1661         },
1662 };
1663 
1664 static int sata_dwc_probe(struct platform_device *ofdev)
1665 {
1666         struct sata_dwc_device *hsdev;
1667         u32 idr, versionr;
1668         char *ver = (char *)&versionr;
1669         u8 __iomem *base;
1670         int err = 0;
1671         int irq;
1672         struct ata_host *host;
1673         struct ata_port_info pi = sata_dwc_port_info[0];
1674         const struct ata_port_info *ppi[] = { &pi, NULL };
1675         struct device_node *np = ofdev->dev.of_node;
1676         u32 dma_chan;
1677 
1678         /* Allocate DWC SATA device */
1679         host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
1680         hsdev = devm_kzalloc(&ofdev->dev, sizeof(*hsdev), GFP_KERNEL);
1681         if (!host || !hsdev)
1682                 return -ENOMEM;
1683 
1684         host->private_data = hsdev;
1685 
1686         if (of_property_read_u32(np, "dma-channel", &dma_chan)) {
1687                 dev_warn(&ofdev->dev, "no dma-channel property set."
1688                          " Use channel 0\n");
1689                 dma_chan = 0;
1690         }
1691         host_pvt.dma_channel = dma_chan;
1692 
1693         /* Ioremap SATA registers */
1694         base = of_iomap(np, 0);
1695         if (!base) {
1696                 dev_err(&ofdev->dev, "ioremap failed for SATA register"
1697                         " address\n");
1698                 return -ENODEV;
1699         }
1700         hsdev->reg_base = base;
1701         dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
1702 
1703         /* Synopsys DWC SATA specific Registers */
1704         hsdev->sata_dwc_regs = (void *__iomem)(base + SATA_DWC_REG_OFFSET);
1705 
1706         /* Setup port */
1707         host->ports[0]->ioaddr.cmd_addr = base;
1708         host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
1709         host_pvt.scr_addr_sstatus = base + SATA_DWC_SCR_OFFSET;
1710         sata_dwc_setup_port(&host->ports[0]->ioaddr, (unsigned long)base);
1711 
1712         /* Read the ID and Version Registers */
1713         idr = in_le32(&hsdev->sata_dwc_regs->idr);
1714         versionr = in_le32(&hsdev->sata_dwc_regs->versionr);
1715         dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
1716                    idr, ver[0], ver[1], ver[2]);
1717 
1718         /* Get SATA DMA interrupt number */
1719         irq = irq_of_parse_and_map(np, 1);
1720         if (irq == NO_IRQ) {
1721                 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1722                 err = -ENODEV;
1723                 goto error_iomap;
1724         }
1725 
1726         /* Get physical SATA DMA register base address */
1727         host_pvt.sata_dma_regs = (void *)of_iomap(np, 1);
1728         if (!(host_pvt.sata_dma_regs)) {
1729                 dev_err(&ofdev->dev, "ioremap failed for AHBDMA register"
1730                         " address\n");
1731                 err = -ENODEV;
1732                 goto error_iomap;
1733         }
1734 
1735         /* Save dev for later use in dev_xxx() routines */
1736         host_pvt.dwc_dev = &ofdev->dev;
1737 
1738         /* Initialize AHB DMAC */
1739         err = dma_dwc_init(hsdev, irq);
1740         if (err)
1741                 goto error_dma_iomap;
1742 
1743         /* Enable SATA Interrupts */
1744         sata_dwc_enable_interrupts(hsdev);
1745 
1746         /* Get SATA interrupt number */
1747         irq = irq_of_parse_and_map(np, 0);
1748         if (irq == NO_IRQ) {
1749                 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1750                 err = -ENODEV;
1751                 goto error_out;
1752         }
1753 
1754         /*
1755          * Now, register with libATA core, this will also initiate the
1756          * device discovery process, invoking our port_start() handler &
1757          * error_handler() to execute a dummy Softreset EH session
1758          */
1759         err = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1760         if (err)
1761                 dev_err(&ofdev->dev, "failed to activate host");
1762 
1763         dev_set_drvdata(&ofdev->dev, host);
1764         return 0;
1765 
1766 error_out:
1767         /* Free SATA DMA resources */
1768         dma_dwc_exit(hsdev);
1769 error_dma_iomap:
1770         iounmap((void __iomem *)host_pvt.sata_dma_regs);
1771 error_iomap:
1772         iounmap(base);
1773         return err;
1774 }
1775 
1776 static int sata_dwc_remove(struct platform_device *ofdev)
1777 {
1778         struct device *dev = &ofdev->dev;
1779         struct ata_host *host = dev_get_drvdata(dev);
1780         struct sata_dwc_device *hsdev = host->private_data;
1781 
1782         ata_host_detach(host);
1783 
1784         /* Free SATA DMA resources */
1785         dma_dwc_exit(hsdev);
1786 
1787         iounmap((void __iomem *)host_pvt.sata_dma_regs);
1788         iounmap(hsdev->reg_base);
1789         dev_dbg(&ofdev->dev, "done\n");
1790         return 0;
1791 }
1792 
1793 static const struct of_device_id sata_dwc_match[] = {
1794         { .compatible = "amcc,sata-460ex", },
1795         {}
1796 };
1797 MODULE_DEVICE_TABLE(of, sata_dwc_match);
1798 
1799 static struct platform_driver sata_dwc_driver = {
1800         .driver = {
1801                 .name = DRV_NAME,
1802                 .of_match_table = sata_dwc_match,
1803         },
1804         .probe = sata_dwc_probe,
1805         .remove = sata_dwc_remove,
1806 };
1807 
1808 module_platform_driver(sata_dwc_driver);
1809 
1810 MODULE_LICENSE("GPL");
1811 MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
1812 MODULE_DESCRIPTION("DesignWare Cores SATA controller low lever driver");
1813 MODULE_VERSION(DRV_VERSION);
1814 

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