Version:  2.0.40 2.2.26 2.4.37 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8

Linux/drivers/ata/sata_dwc_460ex.c

  1 /*
  2  * drivers/ata/sata_dwc_460ex.c
  3  *
  4  * Synopsys DesignWare Cores (DWC) SATA host driver
  5  *
  6  * Author: Mark Miesfeld <mmiesfeld@amcc.com>
  7  *
  8  * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
  9  * Copyright 2008 DENX Software Engineering
 10  *
 11  * Based on versions provided by AMCC and Synopsys which are:
 12  *          Copyright 2006 Applied Micro Circuits Corporation
 13  *          COPYRIGHT (C) 2005  SYNOPSYS, INC.  ALL RIGHTS RESERVED
 14  *
 15  * This program is free software; you can redistribute  it and/or modify it
 16  * under  the terms of  the GNU General  Public License as published by the
 17  * Free Software Foundation;  either version 2 of the  License, or (at your
 18  * option) any later version.
 19  */
 20 
 21 #ifdef CONFIG_SATA_DWC_DEBUG
 22 #define DEBUG
 23 #endif
 24 
 25 #ifdef CONFIG_SATA_DWC_VDEBUG
 26 #define VERBOSE_DEBUG
 27 #define DEBUG_NCQ
 28 #endif
 29 
 30 #include <linux/kernel.h>
 31 #include <linux/module.h>
 32 #include <linux/device.h>
 33 #include <linux/dmaengine.h>
 34 #include <linux/of_address.h>
 35 #include <linux/of_irq.h>
 36 #include <linux/of_platform.h>
 37 #include <linux/platform_device.h>
 38 #include <linux/phy/phy.h>
 39 #include <linux/libata.h>
 40 #include <linux/slab.h>
 41 
 42 #include "libata.h"
 43 
 44 #include <scsi/scsi_host.h>
 45 #include <scsi/scsi_cmnd.h>
 46 
 47 /* These two are defined in "libata.h" */
 48 #undef  DRV_NAME
 49 #undef  DRV_VERSION
 50 
 51 #define DRV_NAME        "sata-dwc"
 52 #define DRV_VERSION     "1.3"
 53 
 54 #define sata_dwc_writel(a, v)   writel_relaxed(v, a)
 55 #define sata_dwc_readl(a)       readl_relaxed(a)
 56 
 57 #ifndef NO_IRQ
 58 #define NO_IRQ          0
 59 #endif
 60 
 61 #define AHB_DMA_BRST_DFLT       64      /* 16 data items burst length */
 62 
 63 enum {
 64         SATA_DWC_MAX_PORTS = 1,
 65 
 66         SATA_DWC_SCR_OFFSET = 0x24,
 67         SATA_DWC_REG_OFFSET = 0x64,
 68 };
 69 
 70 /* DWC SATA Registers */
 71 struct sata_dwc_regs {
 72         u32 fptagr;             /* 1st party DMA tag */
 73         u32 fpbor;              /* 1st party DMA buffer offset */
 74         u32 fptcr;              /* 1st party DMA Xfr count */
 75         u32 dmacr;              /* DMA Control */
 76         u32 dbtsr;              /* DMA Burst Transac size */
 77         u32 intpr;              /* Interrupt Pending */
 78         u32 intmr;              /* Interrupt Mask */
 79         u32 errmr;              /* Error Mask */
 80         u32 llcr;               /* Link Layer Control */
 81         u32 phycr;              /* PHY Control */
 82         u32 physr;              /* PHY Status */
 83         u32 rxbistpd;           /* Recvd BIST pattern def register */
 84         u32 rxbistpd1;          /* Recvd BIST data dword1 */
 85         u32 rxbistpd2;          /* Recvd BIST pattern data dword2 */
 86         u32 txbistpd;           /* Trans BIST pattern def register */
 87         u32 txbistpd1;          /* Trans BIST data dword1 */
 88         u32 txbistpd2;          /* Trans BIST data dword2 */
 89         u32 bistcr;             /* BIST Control Register */
 90         u32 bistfctr;           /* BIST FIS Count Register */
 91         u32 bistsr;             /* BIST Status Register */
 92         u32 bistdecr;           /* BIST Dword Error count register */
 93         u32 res[15];            /* Reserved locations */
 94         u32 testr;              /* Test Register */
 95         u32 versionr;           /* Version Register */
 96         u32 idr;                /* ID Register */
 97         u32 unimpl[192];        /* Unimplemented */
 98         u32 dmadr[256];         /* FIFO Locations in DMA Mode */
 99 };
100 
101 enum {
102         SCR_SCONTROL_DET_ENABLE =       0x00000001,
103         SCR_SSTATUS_DET_PRESENT =       0x00000001,
104         SCR_SERROR_DIAG_X       =       0x04000000,
105 /* DWC SATA Register Operations */
106         SATA_DWC_TXFIFO_DEPTH   =       0x01FF,
107         SATA_DWC_RXFIFO_DEPTH   =       0x01FF,
108         SATA_DWC_DMACR_TMOD_TXCHEN =    0x00000004,
109         SATA_DWC_DMACR_TXCHEN   = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
110         SATA_DWC_DMACR_RXCHEN   = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
111         SATA_DWC_DMACR_TXRXCH_CLEAR =   SATA_DWC_DMACR_TMOD_TXCHEN,
112         SATA_DWC_INTPR_DMAT     =       0x00000001,
113         SATA_DWC_INTPR_NEWFP    =       0x00000002,
114         SATA_DWC_INTPR_PMABRT   =       0x00000004,
115         SATA_DWC_INTPR_ERR      =       0x00000008,
116         SATA_DWC_INTPR_NEWBIST  =       0x00000010,
117         SATA_DWC_INTPR_IPF      =       0x10000000,
118         SATA_DWC_INTMR_DMATM    =       0x00000001,
119         SATA_DWC_INTMR_NEWFPM   =       0x00000002,
120         SATA_DWC_INTMR_PMABRTM  =       0x00000004,
121         SATA_DWC_INTMR_ERRM     =       0x00000008,
122         SATA_DWC_INTMR_NEWBISTM =       0x00000010,
123         SATA_DWC_LLCR_SCRAMEN   =       0x00000001,
124         SATA_DWC_LLCR_DESCRAMEN =       0x00000002,
125         SATA_DWC_LLCR_RPDEN     =       0x00000004,
126 /* This is all error bits, zero's are reserved fields. */
127         SATA_DWC_SERROR_ERR_BITS =      0x0FFF0F03
128 };
129 
130 #define SATA_DWC_SCR0_SPD_GET(v)        (((v) >> 4) & 0x0000000F)
131 #define SATA_DWC_DMACR_TX_CLEAR(v)      (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
132                                                  SATA_DWC_DMACR_TMOD_TXCHEN)
133 #define SATA_DWC_DMACR_RX_CLEAR(v)      (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
134                                                  SATA_DWC_DMACR_TMOD_TXCHEN)
135 #define SATA_DWC_DBTSR_MWR(size)        (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
136 #define SATA_DWC_DBTSR_MRD(size)        ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
137                                                  << 16)
138 struct sata_dwc_device {
139         struct device           *dev;           /* generic device struct */
140         struct ata_probe_ent    *pe;            /* ptr to probe-ent */
141         struct ata_host         *host;
142         struct sata_dwc_regs __iomem *sata_dwc_regs;    /* DW SATA specific */
143         u32                     sactive_issued;
144         u32                     sactive_queued;
145         struct phy              *phy;
146         phys_addr_t             dmadr;
147 #ifdef CONFIG_SATA_DWC_OLD_DMA
148         struct dw_dma_chip      *dma;
149 #endif
150 };
151 
152 #define SATA_DWC_QCMD_MAX       32
153 
154 struct sata_dwc_device_port {
155         struct sata_dwc_device  *hsdev;
156         int                     cmd_issued[SATA_DWC_QCMD_MAX];
157         int                     dma_pending[SATA_DWC_QCMD_MAX];
158 
159         /* DMA info */
160         struct dma_chan                 *chan;
161         struct dma_async_tx_descriptor  *desc[SATA_DWC_QCMD_MAX];
162         u32                             dma_interrupt_count;
163 };
164 
165 /*
166  * Commonly used DWC SATA driver macros
167  */
168 #define HSDEV_FROM_HOST(host)   ((struct sata_dwc_device *)(host)->private_data)
169 #define HSDEV_FROM_AP(ap)       ((struct sata_dwc_device *)(ap)->host->private_data)
170 #define HSDEVP_FROM_AP(ap)      ((struct sata_dwc_device_port *)(ap)->private_data)
171 #define HSDEV_FROM_QC(qc)       ((struct sata_dwc_device *)(qc)->ap->host->private_data)
172 #define HSDEV_FROM_HSDEVP(p)    ((struct sata_dwc_device *)(p)->hsdev)
173 
174 enum {
175         SATA_DWC_CMD_ISSUED_NOT         = 0,
176         SATA_DWC_CMD_ISSUED_PEND        = 1,
177         SATA_DWC_CMD_ISSUED_EXEC        = 2,
178         SATA_DWC_CMD_ISSUED_NODATA      = 3,
179 
180         SATA_DWC_DMA_PENDING_NONE       = 0,
181         SATA_DWC_DMA_PENDING_TX         = 1,
182         SATA_DWC_DMA_PENDING_RX         = 2,
183 };
184 
185 /*
186  * Prototypes
187  */
188 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
189 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
190                                 u32 check_status);
191 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
192 static void sata_dwc_port_stop(struct ata_port *ap);
193 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
194 
195 #ifdef CONFIG_SATA_DWC_OLD_DMA
196 
197 #include <linux/platform_data/dma-dw.h>
198 #include <linux/dma/dw.h>
199 
200 static struct dw_dma_slave sata_dwc_dma_dws = {
201         .src_id = 0,
202         .dst_id = 0,
203         .m_master = 1,
204         .p_master = 0,
205 };
206 
207 static bool sata_dwc_dma_filter(struct dma_chan *chan, void *param)
208 {
209         struct dw_dma_slave *dws = &sata_dwc_dma_dws;
210 
211         if (dws->dma_dev != chan->device->dev)
212                 return false;
213 
214         chan->private = dws;
215         return true;
216 }
217 
218 static int sata_dwc_dma_get_channel_old(struct sata_dwc_device_port *hsdevp)
219 {
220         struct sata_dwc_device *hsdev = hsdevp->hsdev;
221         struct dw_dma_slave *dws = &sata_dwc_dma_dws;
222         dma_cap_mask_t mask;
223 
224         dws->dma_dev = hsdev->dev;
225 
226         dma_cap_zero(mask);
227         dma_cap_set(DMA_SLAVE, mask);
228 
229         /* Acquire DMA channel */
230         hsdevp->chan = dma_request_channel(mask, sata_dwc_dma_filter, hsdevp);
231         if (!hsdevp->chan) {
232                 dev_err(hsdev->dev, "%s: dma channel unavailable\n",
233                          __func__);
234                 return -EAGAIN;
235         }
236 
237         return 0;
238 }
239 
240 static int sata_dwc_dma_init_old(struct platform_device *pdev,
241                                  struct sata_dwc_device *hsdev)
242 {
243         struct device_node *np = pdev->dev.of_node;
244         struct resource *res;
245 
246         hsdev->dma = devm_kzalloc(&pdev->dev, sizeof(*hsdev->dma), GFP_KERNEL);
247         if (!hsdev->dma)
248                 return -ENOMEM;
249 
250         hsdev->dma->dev = &pdev->dev;
251 
252         /* Get SATA DMA interrupt number */
253         hsdev->dma->irq = irq_of_parse_and_map(np, 1);
254         if (hsdev->dma->irq == NO_IRQ) {
255                 dev_err(&pdev->dev, "no SATA DMA irq\n");
256                 return -ENODEV;
257         }
258 
259         /* Get physical SATA DMA register base address */
260         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
261         hsdev->dma->regs = devm_ioremap_resource(&pdev->dev, res);
262         if (IS_ERR(hsdev->dma->regs))
263                 return PTR_ERR(hsdev->dma->regs);
264 
265         /* Initialize AHB DMAC */
266         return dw_dma_probe(hsdev->dma);
267 }
268 
269 static void sata_dwc_dma_exit_old(struct sata_dwc_device *hsdev)
270 {
271         if (!hsdev->dma)
272                 return;
273 
274         dw_dma_remove(hsdev->dma);
275 }
276 
277 #endif
278 
279 static const char *get_prot_descript(u8 protocol)
280 {
281         switch (protocol) {
282         case ATA_PROT_NODATA:
283                 return "ATA no data";
284         case ATA_PROT_PIO:
285                 return "ATA PIO";
286         case ATA_PROT_DMA:
287                 return "ATA DMA";
288         case ATA_PROT_NCQ:
289                 return "ATA NCQ";
290         case ATA_PROT_NCQ_NODATA:
291                 return "ATA NCQ no data";
292         case ATAPI_PROT_NODATA:
293                 return "ATAPI no data";
294         case ATAPI_PROT_PIO:
295                 return "ATAPI PIO";
296         case ATAPI_PROT_DMA:
297                 return "ATAPI DMA";
298         default:
299                 return "unknown";
300         }
301 }
302 
303 static const char *get_dma_dir_descript(int dma_dir)
304 {
305         switch ((enum dma_data_direction)dma_dir) {
306         case DMA_BIDIRECTIONAL:
307                 return "bidirectional";
308         case DMA_TO_DEVICE:
309                 return "to device";
310         case DMA_FROM_DEVICE:
311                 return "from device";
312         default:
313                 return "none";
314         }
315 }
316 
317 static void sata_dwc_tf_dump(struct ata_port *ap, struct ata_taskfile *tf)
318 {
319         dev_vdbg(ap->dev,
320                 "taskfile cmd: 0x%02x protocol: %s flags: 0x%lx device: %x\n",
321                 tf->command, get_prot_descript(tf->protocol), tf->flags,
322                 tf->device);
323         dev_vdbg(ap->dev,
324                 "feature: 0x%02x nsect: 0x%x lbal: 0x%x lbam: 0x%x lbah: 0x%x\n",
325                 tf->feature, tf->nsect, tf->lbal, tf->lbam, tf->lbah);
326         dev_vdbg(ap->dev,
327                 "hob_feature: 0x%02x hob_nsect: 0x%x hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
328                 tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
329                 tf->hob_lbah);
330 }
331 
332 static void dma_dwc_xfer_done(void *hsdev_instance)
333 {
334         unsigned long flags;
335         struct sata_dwc_device *hsdev = hsdev_instance;
336         struct ata_host *host = (struct ata_host *)hsdev->host;
337         struct ata_port *ap;
338         struct sata_dwc_device_port *hsdevp;
339         u8 tag = 0;
340         unsigned int port = 0;
341 
342         spin_lock_irqsave(&host->lock, flags);
343         ap = host->ports[port];
344         hsdevp = HSDEVP_FROM_AP(ap);
345         tag = ap->link.active_tag;
346 
347         /*
348          * Each DMA command produces 2 interrupts.  Only
349          * complete the command after both interrupts have been
350          * seen. (See sata_dwc_isr())
351          */
352         hsdevp->dma_interrupt_count++;
353         sata_dwc_clear_dmacr(hsdevp, tag);
354 
355         if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
356                 dev_err(ap->dev, "DMA not pending tag=0x%02x pending=%d\n",
357                         tag, hsdevp->dma_pending[tag]);
358         }
359 
360         if ((hsdevp->dma_interrupt_count % 2) == 0)
361                 sata_dwc_dma_xfer_complete(ap, 1);
362 
363         spin_unlock_irqrestore(&host->lock, flags);
364 }
365 
366 static struct dma_async_tx_descriptor *dma_dwc_xfer_setup(struct ata_queued_cmd *qc)
367 {
368         struct ata_port *ap = qc->ap;
369         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
370         struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
371         struct dma_slave_config sconf;
372         struct dma_async_tx_descriptor *desc;
373 
374         if (qc->dma_dir == DMA_DEV_TO_MEM) {
375                 sconf.src_addr = hsdev->dmadr;
376                 sconf.device_fc = false;
377         } else {        /* DMA_MEM_TO_DEV */
378                 sconf.dst_addr = hsdev->dmadr;
379                 sconf.device_fc = false;
380         }
381 
382         sconf.direction = qc->dma_dir;
383         sconf.src_maxburst = AHB_DMA_BRST_DFLT / 4;     /* in items */
384         sconf.dst_maxburst = AHB_DMA_BRST_DFLT / 4;     /* in items */
385         sconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
386         sconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
387 
388         dmaengine_slave_config(hsdevp->chan, &sconf);
389 
390         /* Convert SG list to linked list of items (LLIs) for AHB DMA */
391         desc = dmaengine_prep_slave_sg(hsdevp->chan, qc->sg, qc->n_elem,
392                                        qc->dma_dir,
393                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
394 
395         if (!desc)
396                 return NULL;
397 
398         desc->callback = dma_dwc_xfer_done;
399         desc->callback_param = hsdev;
400 
401         dev_dbg(hsdev->dev, "%s sg: 0x%p, count: %d addr: %pa\n", __func__,
402                 qc->sg, qc->n_elem, &hsdev->dmadr);
403 
404         return desc;
405 }
406 
407 static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
408 {
409         if (scr > SCR_NOTIFICATION) {
410                 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
411                         __func__, scr);
412                 return -EINVAL;
413         }
414 
415         *val = sata_dwc_readl(link->ap->ioaddr.scr_addr + (scr * 4));
416         dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=0x%08x\n", __func__,
417                 link->ap->print_id, scr, *val);
418 
419         return 0;
420 }
421 
422 static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
423 {
424         dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=0x%08x\n", __func__,
425                 link->ap->print_id, scr, val);
426         if (scr > SCR_NOTIFICATION) {
427                 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
428                          __func__, scr);
429                 return -EINVAL;
430         }
431         sata_dwc_writel(link->ap->ioaddr.scr_addr + (scr * 4), val);
432 
433         return 0;
434 }
435 
436 static void clear_serror(struct ata_port *ap)
437 {
438         u32 val;
439         sata_dwc_scr_read(&ap->link, SCR_ERROR, &val);
440         sata_dwc_scr_write(&ap->link, SCR_ERROR, val);
441 }
442 
443 static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
444 {
445         sata_dwc_writel(&hsdev->sata_dwc_regs->intpr,
446                         sata_dwc_readl(&hsdev->sata_dwc_regs->intpr));
447 }
448 
449 static u32 qcmd_tag_to_mask(u8 tag)
450 {
451         return 0x00000001 << (tag & 0x1f);
452 }
453 
454 /* See ahci.c */
455 static void sata_dwc_error_intr(struct ata_port *ap,
456                                 struct sata_dwc_device *hsdev, uint intpr)
457 {
458         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
459         struct ata_eh_info *ehi = &ap->link.eh_info;
460         unsigned int err_mask = 0, action = 0;
461         struct ata_queued_cmd *qc;
462         u32 serror;
463         u8 status, tag;
464 
465         ata_ehi_clear_desc(ehi);
466 
467         sata_dwc_scr_read(&ap->link, SCR_ERROR, &serror);
468         status = ap->ops->sff_check_status(ap);
469 
470         tag = ap->link.active_tag;
471 
472         dev_err(ap->dev,
473                 "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x dma_intp=%d pending=%d issued=%d",
474                 __func__, serror, intpr, status, hsdevp->dma_interrupt_count,
475                 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag]);
476 
477         /* Clear error register and interrupt bit */
478         clear_serror(ap);
479         clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
480 
481         /* This is the only error happening now.  TODO check for exact error */
482 
483         err_mask |= AC_ERR_HOST_BUS;
484         action |= ATA_EH_RESET;
485 
486         /* Pass this on to EH */
487         ehi->serror |= serror;
488         ehi->action |= action;
489 
490         qc = ata_qc_from_tag(ap, tag);
491         if (qc)
492                 qc->err_mask |= err_mask;
493         else
494                 ehi->err_mask |= err_mask;
495 
496         ata_port_abort(ap);
497 }
498 
499 /*
500  * Function : sata_dwc_isr
501  * arguments : irq, void *dev_instance, struct pt_regs *regs
502  * Return value : irqreturn_t - status of IRQ
503  * This Interrupt handler called via port ops registered function.
504  * .irq_handler = sata_dwc_isr
505  */
506 static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
507 {
508         struct ata_host *host = (struct ata_host *)dev_instance;
509         struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
510         struct ata_port *ap;
511         struct ata_queued_cmd *qc;
512         unsigned long flags;
513         u8 status, tag;
514         int handled, num_processed, port = 0;
515         uint intpr, sactive, sactive2, tag_mask;
516         struct sata_dwc_device_port *hsdevp;
517         hsdev->sactive_issued = 0;
518 
519         spin_lock_irqsave(&host->lock, flags);
520 
521         /* Read the interrupt register */
522         intpr = sata_dwc_readl(&hsdev->sata_dwc_regs->intpr);
523 
524         ap = host->ports[port];
525         hsdevp = HSDEVP_FROM_AP(ap);
526 
527         dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
528                 ap->link.active_tag);
529 
530         /* Check for error interrupt */
531         if (intpr & SATA_DWC_INTPR_ERR) {
532                 sata_dwc_error_intr(ap, hsdev, intpr);
533                 handled = 1;
534                 goto DONE;
535         }
536 
537         /* Check for DMA SETUP FIS (FP DMA) interrupt */
538         if (intpr & SATA_DWC_INTPR_NEWFP) {
539                 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
540 
541                 tag = (u8)(sata_dwc_readl(&hsdev->sata_dwc_regs->fptagr));
542                 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
543                 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
544                         dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
545 
546                 hsdev->sactive_issued |= qcmd_tag_to_mask(tag);
547 
548                 qc = ata_qc_from_tag(ap, tag);
549                 /*
550                  * Start FP DMA for NCQ command.  At this point the tag is the
551                  * active tag.  It is the tag that matches the command about to
552                  * be completed.
553                  */
554                 qc->ap->link.active_tag = tag;
555                 sata_dwc_bmdma_start_by_tag(qc, tag);
556 
557                 handled = 1;
558                 goto DONE;
559         }
560         sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
561         tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
562 
563         /* If no sactive issued and tag_mask is zero then this is not NCQ */
564         if (hsdev->sactive_issued == 0 && tag_mask == 0) {
565                 if (ap->link.active_tag == ATA_TAG_POISON)
566                         tag = 0;
567                 else
568                         tag = ap->link.active_tag;
569                 qc = ata_qc_from_tag(ap, tag);
570 
571                 /* DEV interrupt w/ no active qc? */
572                 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
573                         dev_err(ap->dev,
574                                 "%s interrupt with no active qc qc=%p\n",
575                                 __func__, qc);
576                         ap->ops->sff_check_status(ap);
577                         handled = 1;
578                         goto DONE;
579                 }
580                 status = ap->ops->sff_check_status(ap);
581 
582                 qc->ap->link.active_tag = tag;
583                 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
584 
585                 if (status & ATA_ERR) {
586                         dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
587                         sata_dwc_qc_complete(ap, qc, 1);
588                         handled = 1;
589                         goto DONE;
590                 }
591 
592                 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
593                         __func__, get_prot_descript(qc->tf.protocol));
594 DRVSTILLBUSY:
595                 if (ata_is_dma(qc->tf.protocol)) {
596                         /*
597                          * Each DMA transaction produces 2 interrupts. The DMAC
598                          * transfer complete interrupt and the SATA controller
599                          * operation done interrupt. The command should be
600                          * completed only after both interrupts are seen.
601                          */
602                         hsdevp->dma_interrupt_count++;
603                         if (hsdevp->dma_pending[tag] == \
604                                         SATA_DWC_DMA_PENDING_NONE) {
605                                 dev_err(ap->dev,
606                                         "%s: DMA not pending intpr=0x%08x status=0x%08x pending=%d\n",
607                                         __func__, intpr, status,
608                                         hsdevp->dma_pending[tag]);
609                         }
610 
611                         if ((hsdevp->dma_interrupt_count % 2) == 0)
612                                 sata_dwc_dma_xfer_complete(ap, 1);
613                 } else if (ata_is_pio(qc->tf.protocol)) {
614                         ata_sff_hsm_move(ap, qc, status, 0);
615                         handled = 1;
616                         goto DONE;
617                 } else {
618                         if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
619                                 goto DRVSTILLBUSY;
620                 }
621 
622                 handled = 1;
623                 goto DONE;
624         }
625 
626         /*
627          * This is a NCQ command. At this point we need to figure out for which
628          * tags we have gotten a completion interrupt.  One interrupt may serve
629          * as completion for more than one operation when commands are queued
630          * (NCQ).  We need to process each completed command.
631          */
632 
633          /* process completed commands */
634         sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
635         tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
636 
637         if (sactive != 0 || hsdev->sactive_issued > 1 || tag_mask > 1) {
638                 dev_dbg(ap->dev,
639                         "%s NCQ:sactive=0x%08x  sactive_issued=0x%08x tag_mask=0x%08x\n",
640                         __func__, sactive, hsdev->sactive_issued, tag_mask);
641         }
642 
643         if ((tag_mask | hsdev->sactive_issued) != hsdev->sactive_issued) {
644                 dev_warn(ap->dev,
645                          "Bad tag mask?  sactive=0x%08x sactive_issued=0x%08x  tag_mask=0x%08x\n",
646                          sactive, hsdev->sactive_issued, tag_mask);
647         }
648 
649         /* read just to clear ... not bad if currently still busy */
650         status = ap->ops->sff_check_status(ap);
651         dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
652 
653         tag = 0;
654         num_processed = 0;
655         while (tag_mask) {
656                 num_processed++;
657                 while (!(tag_mask & 0x00000001)) {
658                         tag++;
659                         tag_mask <<= 1;
660                 }
661 
662                 tag_mask &= (~0x00000001);
663                 qc = ata_qc_from_tag(ap, tag);
664 
665                 /* To be picked up by completion functions */
666                 qc->ap->link.active_tag = tag;
667                 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
668 
669                 /* Let libata/scsi layers handle error */
670                 if (status & ATA_ERR) {
671                         dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
672                                 status);
673                         sata_dwc_qc_complete(ap, qc, 1);
674                         handled = 1;
675                         goto DONE;
676                 }
677 
678                 /* Process completed command */
679                 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
680                         get_prot_descript(qc->tf.protocol));
681                 if (ata_is_dma(qc->tf.protocol)) {
682                         hsdevp->dma_interrupt_count++;
683                         if (hsdevp->dma_pending[tag] == \
684                                         SATA_DWC_DMA_PENDING_NONE)
685                                 dev_warn(ap->dev, "%s: DMA not pending?\n",
686                                         __func__);
687                         if ((hsdevp->dma_interrupt_count % 2) == 0)
688                                 sata_dwc_dma_xfer_complete(ap, 1);
689                 } else {
690                         if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
691                                 goto STILLBUSY;
692                 }
693                 continue;
694 
695 STILLBUSY:
696                 ap->stats.idle_irq++;
697                 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
698                         ap->print_id);
699         } /* while tag_mask */
700 
701         /*
702          * Check to see if any commands completed while we were processing our
703          * initial set of completed commands (read status clears interrupts,
704          * so we might miss a completed command interrupt if one came in while
705          * we were processing --we read status as part of processing a completed
706          * command).
707          */
708         sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive2);
709         if (sactive2 != sactive) {
710                 dev_dbg(ap->dev,
711                         "More completed - sactive=0x%x sactive2=0x%x\n",
712                         sactive, sactive2);
713         }
714         handled = 1;
715 
716 DONE:
717         spin_unlock_irqrestore(&host->lock, flags);
718         return IRQ_RETVAL(handled);
719 }
720 
721 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
722 {
723         struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
724         u32 dmacr = sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr);
725 
726         if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
727                 dmacr = SATA_DWC_DMACR_RX_CLEAR(dmacr);
728                 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr);
729         } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
730                 dmacr = SATA_DWC_DMACR_TX_CLEAR(dmacr);
731                 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr);
732         } else {
733                 /*
734                  * This should not happen, it indicates the driver is out of
735                  * sync.  If it does happen, clear dmacr anyway.
736                  */
737                 dev_err(hsdev->dev,
738                         "%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n",
739                         __func__, tag, hsdevp->dma_pending[tag], dmacr);
740                 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
741                                 SATA_DWC_DMACR_TXRXCH_CLEAR);
742         }
743 }
744 
745 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
746 {
747         struct ata_queued_cmd *qc;
748         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
749         struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
750         u8 tag = 0;
751 
752         tag = ap->link.active_tag;
753         qc = ata_qc_from_tag(ap, tag);
754         if (!qc) {
755                 dev_err(ap->dev, "failed to get qc");
756                 return;
757         }
758 
759 #ifdef DEBUG_NCQ
760         if (tag > 0) {
761                 dev_info(ap->dev,
762                          "%s tag=%u cmd=0x%02x dma dir=%s proto=%s dmacr=0x%08x\n",
763                          __func__, qc->tag, qc->tf.command,
764                          get_dma_dir_descript(qc->dma_dir),
765                          get_prot_descript(qc->tf.protocol),
766                          sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
767         }
768 #endif
769 
770         if (ata_is_dma(qc->tf.protocol)) {
771                 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
772                         dev_err(ap->dev,
773                                 "%s DMA protocol RX and TX DMA not pending dmacr: 0x%08x\n",
774                                 __func__,
775                                 sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
776                 }
777 
778                 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
779                 sata_dwc_qc_complete(ap, qc, check_status);
780                 ap->link.active_tag = ATA_TAG_POISON;
781         } else {
782                 sata_dwc_qc_complete(ap, qc, check_status);
783         }
784 }
785 
786 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
787                                 u32 check_status)
788 {
789         u8 status = 0;
790         u32 mask = 0x0;
791         u8 tag = qc->tag;
792         struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
793         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
794         hsdev->sactive_queued = 0;
795         dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
796 
797         if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
798                 dev_err(ap->dev, "TX DMA PENDING\n");
799         else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
800                 dev_err(ap->dev, "RX DMA PENDING\n");
801         dev_dbg(ap->dev,
802                 "QC complete cmd=0x%02x status=0x%02x ata%u: protocol=%d\n",
803                 qc->tf.command, status, ap->print_id, qc->tf.protocol);
804 
805         /* clear active bit */
806         mask = (~(qcmd_tag_to_mask(tag)));
807         hsdev->sactive_queued = hsdev->sactive_queued & mask;
808         hsdev->sactive_issued = hsdev->sactive_issued & mask;
809         ata_qc_complete(qc);
810         return 0;
811 }
812 
813 static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
814 {
815         /* Enable selective interrupts by setting the interrupt maskregister*/
816         sata_dwc_writel(&hsdev->sata_dwc_regs->intmr,
817                         SATA_DWC_INTMR_ERRM |
818                         SATA_DWC_INTMR_NEWFPM |
819                         SATA_DWC_INTMR_PMABRTM |
820                         SATA_DWC_INTMR_DMATM);
821         /*
822          * Unmask the error bits that should trigger an error interrupt by
823          * setting the error mask register.
824          */
825         sata_dwc_writel(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
826 
827         dev_dbg(hsdev->dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
828                  __func__, sata_dwc_readl(&hsdev->sata_dwc_regs->intmr),
829                 sata_dwc_readl(&hsdev->sata_dwc_regs->errmr));
830 }
831 
832 static void sata_dwc_setup_port(struct ata_ioports *port, void __iomem *base)
833 {
834         port->cmd_addr          = base + 0x00;
835         port->data_addr         = base + 0x00;
836 
837         port->error_addr        = base + 0x04;
838         port->feature_addr      = base + 0x04;
839 
840         port->nsect_addr        = base + 0x08;
841 
842         port->lbal_addr         = base + 0x0c;
843         port->lbam_addr         = base + 0x10;
844         port->lbah_addr         = base + 0x14;
845 
846         port->device_addr       = base + 0x18;
847         port->command_addr      = base + 0x1c;
848         port->status_addr       = base + 0x1c;
849 
850         port->altstatus_addr    = base + 0x20;
851         port->ctl_addr          = base + 0x20;
852 }
853 
854 static int sata_dwc_dma_get_channel(struct sata_dwc_device_port *hsdevp)
855 {
856         struct sata_dwc_device *hsdev = hsdevp->hsdev;
857         struct device *dev = hsdev->dev;
858 
859 #ifdef CONFIG_SATA_DWC_OLD_DMA
860         if (!of_find_property(dev->of_node, "dmas", NULL))
861                 return sata_dwc_dma_get_channel_old(hsdevp);
862 #endif
863 
864         hsdevp->chan = dma_request_chan(dev, "sata-dma");
865         if (IS_ERR(hsdevp->chan)) {
866                 dev_err(dev, "failed to allocate dma channel: %ld\n",
867                         PTR_ERR(hsdevp->chan));
868                 return PTR_ERR(hsdevp->chan);
869         }
870 
871         return 0;
872 }
873 
874 /*
875  * Function : sata_dwc_port_start
876  * arguments : struct ata_ioports *port
877  * Return value : returns 0 if success, error code otherwise
878  * This function allocates the scatter gather LLI table for AHB DMA
879  */
880 static int sata_dwc_port_start(struct ata_port *ap)
881 {
882         int err = 0;
883         struct sata_dwc_device *hsdev;
884         struct sata_dwc_device_port *hsdevp = NULL;
885         struct device *pdev;
886         int i;
887 
888         hsdev = HSDEV_FROM_AP(ap);
889 
890         dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
891 
892         hsdev->host = ap->host;
893         pdev = ap->host->dev;
894         if (!pdev) {
895                 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
896                 err = -ENODEV;
897                 goto CLEANUP;
898         }
899 
900         /* Allocate Port Struct */
901         hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
902         if (!hsdevp) {
903                 dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__);
904                 err = -ENOMEM;
905                 goto CLEANUP;
906         }
907         hsdevp->hsdev = hsdev;
908 
909         err = sata_dwc_dma_get_channel(hsdevp);
910         if (err)
911                 goto CLEANUP_ALLOC;
912 
913         err = phy_power_on(hsdev->phy);
914         if (err)
915                 goto CLEANUP_ALLOC;
916 
917         for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
918                 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
919 
920         ap->bmdma_prd = NULL;   /* set these so libata doesn't use them */
921         ap->bmdma_prd_dma = 0;
922 
923         if (ap->port_no == 0)  {
924                 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
925                         __func__);
926                 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
927                                 SATA_DWC_DMACR_TXRXCH_CLEAR);
928 
929                 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
930                          __func__);
931                 sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
932                                 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
933                                  SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
934         }
935 
936         /* Clear any error bits before libata starts issuing commands */
937         clear_serror(ap);
938         ap->private_data = hsdevp;
939         dev_dbg(ap->dev, "%s: done\n", __func__);
940         return 0;
941 
942 CLEANUP_ALLOC:
943         kfree(hsdevp);
944 CLEANUP:
945         dev_dbg(ap->dev, "%s: fail. ap->id = %d\n", __func__, ap->print_id);
946         return err;
947 }
948 
949 static void sata_dwc_port_stop(struct ata_port *ap)
950 {
951         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
952         struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
953 
954         dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
955 
956         dmaengine_terminate_sync(hsdevp->chan);
957         dma_release_channel(hsdevp->chan);
958         phy_power_off(hsdev->phy);
959 
960         kfree(hsdevp);
961         ap->private_data = NULL;
962 }
963 
964 /*
965  * Function : sata_dwc_exec_command_by_tag
966  * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
967  * Return value : None
968  * This function keeps track of individual command tag ids and calls
969  * ata_exec_command in libata
970  */
971 static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
972                                          struct ata_taskfile *tf,
973                                          u8 tag, u32 cmd_issued)
974 {
975         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
976 
977         dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
978                 ata_get_cmd_descript(tf->command), tag);
979 
980         hsdevp->cmd_issued[tag] = cmd_issued;
981 
982         /*
983          * Clear SError before executing a new command.
984          * sata_dwc_scr_write and read can not be used here. Clearing the PM
985          * managed SError register for the disk needs to be done before the
986          * task file is loaded.
987          */
988         clear_serror(ap);
989         ata_sff_exec_command(ap, tf);
990 }
991 
992 static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
993 {
994         sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
995                                      SATA_DWC_CMD_ISSUED_PEND);
996 }
997 
998 static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
999 {
1000         u8 tag = qc->tag;
1001 
1002         if (ata_is_ncq(qc->tf.protocol)) {
1003                 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1004                         __func__, qc->ap->link.sactive, tag);
1005         } else {
1006                 tag = 0;
1007         }
1008         sata_dwc_bmdma_setup_by_tag(qc, tag);
1009 }
1010 
1011 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
1012 {
1013         int start_dma;
1014         u32 reg;
1015         struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
1016         struct ata_port *ap = qc->ap;
1017         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1018         struct dma_async_tx_descriptor *desc = hsdevp->desc[tag];
1019         int dir = qc->dma_dir;
1020 
1021         if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
1022                 start_dma = 1;
1023                 if (dir == DMA_TO_DEVICE)
1024                         hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
1025                 else
1026                         hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
1027         } else {
1028                 dev_err(ap->dev,
1029                         "%s: Command not pending cmd_issued=%d (tag=%d) DMA NOT started\n",
1030                         __func__, hsdevp->cmd_issued[tag], tag);
1031                 start_dma = 0;
1032         }
1033 
1034         dev_dbg(ap->dev,
1035                 "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s start_dma? %x\n",
1036                 __func__, qc, tag, qc->tf.command,
1037                 get_dma_dir_descript(qc->dma_dir), start_dma);
1038         sata_dwc_tf_dump(ap, &qc->tf);
1039 
1040         if (start_dma) {
1041                 sata_dwc_scr_read(&ap->link, SCR_ERROR, &reg);
1042                 if (reg & SATA_DWC_SERROR_ERR_BITS) {
1043                         dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
1044                                 __func__, reg);
1045                 }
1046 
1047                 if (dir == DMA_TO_DEVICE)
1048                         sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1049                                         SATA_DWC_DMACR_TXCHEN);
1050                 else
1051                         sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1052                                         SATA_DWC_DMACR_RXCHEN);
1053 
1054                 /* Enable AHB DMA transfer on the specified channel */
1055                 dmaengine_submit(desc);
1056                 dma_async_issue_pending(hsdevp->chan);
1057         }
1058 }
1059 
1060 static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
1061 {
1062         u8 tag = qc->tag;
1063 
1064         if (ata_is_ncq(qc->tf.protocol)) {
1065                 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1066                         __func__, qc->ap->link.sactive, tag);
1067         } else {
1068                 tag = 0;
1069         }
1070         dev_dbg(qc->ap->dev, "%s\n", __func__);
1071         sata_dwc_bmdma_start_by_tag(qc, tag);
1072 }
1073 
1074 static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1075 {
1076         u32 sactive;
1077         u8 tag = qc->tag;
1078         struct ata_port *ap = qc->ap;
1079         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1080 
1081 #ifdef DEBUG_NCQ
1082         if (qc->tag > 0 || ap->link.sactive > 1)
1083                 dev_info(ap->dev,
1084                          "%s ap id=%d cmd(0x%02x)=%s qc tag=%d prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
1085                          __func__, ap->print_id, qc->tf.command,
1086                          ata_get_cmd_descript(qc->tf.command),
1087                          qc->tag, get_prot_descript(qc->tf.protocol),
1088                          ap->link.active_tag, ap->link.sactive);
1089 #endif
1090 
1091         if (!ata_is_ncq(qc->tf.protocol))
1092                 tag = 0;
1093 
1094         if (ata_is_dma(qc->tf.protocol)) {
1095                 hsdevp->desc[tag] = dma_dwc_xfer_setup(qc);
1096                 if (!hsdevp->desc[tag])
1097                         return AC_ERR_SYSTEM;
1098         } else {
1099                 hsdevp->desc[tag] = NULL;
1100         }
1101 
1102         if (ata_is_ncq(qc->tf.protocol)) {
1103                 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
1104                 sactive |= (0x00000001 << tag);
1105                 sata_dwc_scr_write(&ap->link, SCR_ACTIVE, sactive);
1106 
1107                 dev_dbg(qc->ap->dev,
1108                         "%s: tag=%d ap->link.sactive = 0x%08x sactive=0x%08x\n",
1109                         __func__, tag, qc->ap->link.sactive, sactive);
1110 
1111                 ap->ops->sff_tf_load(ap, &qc->tf);
1112                 sata_dwc_exec_command_by_tag(ap, &qc->tf, tag,
1113                                              SATA_DWC_CMD_ISSUED_PEND);
1114         } else {
1115                 return ata_bmdma_qc_issue(qc);
1116         }
1117         return 0;
1118 }
1119 
1120 static void sata_dwc_error_handler(struct ata_port *ap)
1121 {
1122         ata_sff_error_handler(ap);
1123 }
1124 
1125 static int sata_dwc_hardreset(struct ata_link *link, unsigned int *class,
1126                               unsigned long deadline)
1127 {
1128         struct sata_dwc_device *hsdev = HSDEV_FROM_AP(link->ap);
1129         int ret;
1130 
1131         ret = sata_sff_hardreset(link, class, deadline);
1132 
1133         sata_dwc_enable_interrupts(hsdev);
1134 
1135         /* Reconfigure the DMA control register */
1136         sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1137                         SATA_DWC_DMACR_TXRXCH_CLEAR);
1138 
1139         /* Reconfigure the DMA Burst Transaction Size register */
1140         sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
1141                         SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1142                         SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
1143 
1144         return ret;
1145 }
1146 
1147 static void sata_dwc_dev_select(struct ata_port *ap, unsigned int device)
1148 {
1149         /* SATA DWC is master only */
1150 }
1151 
1152 /*
1153  * scsi mid-layer and libata interface structures
1154  */
1155 static struct scsi_host_template sata_dwc_sht = {
1156         ATA_NCQ_SHT(DRV_NAME),
1157         /*
1158          * test-only: Currently this driver doesn't handle NCQ
1159          * correctly. We enable NCQ but set the queue depth to a
1160          * max of 1. This will get fixed in in a future release.
1161          */
1162         .sg_tablesize           = LIBATA_MAX_PRD,
1163         /* .can_queue           = ATA_MAX_QUEUE, */
1164         /*
1165          * Make sure a LLI block is not created that will span 8K max FIS
1166          * boundary. If the block spans such a FIS boundary, there is a chance
1167          * that a DMA burst will cross that boundary -- this results in an
1168          * error in the host controller.
1169          */
1170         .dma_boundary           = 0x1fff /* ATA_DMA_BOUNDARY */,
1171 };
1172 
1173 static struct ata_port_operations sata_dwc_ops = {
1174         .inherits               = &ata_sff_port_ops,
1175 
1176         .error_handler          = sata_dwc_error_handler,
1177         .hardreset              = sata_dwc_hardreset,
1178 
1179         .qc_issue               = sata_dwc_qc_issue,
1180 
1181         .scr_read               = sata_dwc_scr_read,
1182         .scr_write              = sata_dwc_scr_write,
1183 
1184         .port_start             = sata_dwc_port_start,
1185         .port_stop              = sata_dwc_port_stop,
1186 
1187         .sff_dev_select         = sata_dwc_dev_select,
1188 
1189         .bmdma_setup            = sata_dwc_bmdma_setup,
1190         .bmdma_start            = sata_dwc_bmdma_start,
1191 };
1192 
1193 static const struct ata_port_info sata_dwc_port_info[] = {
1194         {
1195                 .flags          = ATA_FLAG_SATA | ATA_FLAG_NCQ,
1196                 .pio_mask       = ATA_PIO4,
1197                 .udma_mask      = ATA_UDMA6,
1198                 .port_ops       = &sata_dwc_ops,
1199         },
1200 };
1201 
1202 static int sata_dwc_probe(struct platform_device *ofdev)
1203 {
1204         struct sata_dwc_device *hsdev;
1205         u32 idr, versionr;
1206         char *ver = (char *)&versionr;
1207         void __iomem *base;
1208         int err = 0;
1209         int irq;
1210         struct ata_host *host;
1211         struct ata_port_info pi = sata_dwc_port_info[0];
1212         const struct ata_port_info *ppi[] = { &pi, NULL };
1213         struct device_node *np = ofdev->dev.of_node;
1214         struct resource *res;
1215 
1216         /* Allocate DWC SATA device */
1217         host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
1218         hsdev = devm_kzalloc(&ofdev->dev, sizeof(*hsdev), GFP_KERNEL);
1219         if (!host || !hsdev)
1220                 return -ENOMEM;
1221 
1222         host->private_data = hsdev;
1223 
1224         /* Ioremap SATA registers */
1225         res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
1226         base = devm_ioremap_resource(&ofdev->dev, res);
1227         if (IS_ERR(base))
1228                 return PTR_ERR(base);
1229         dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
1230 
1231         /* Synopsys DWC SATA specific Registers */
1232         hsdev->sata_dwc_regs = base + SATA_DWC_REG_OFFSET;
1233         hsdev->dmadr = res->start + SATA_DWC_REG_OFFSET + offsetof(struct sata_dwc_regs, dmadr);
1234 
1235         /* Setup port */
1236         host->ports[0]->ioaddr.cmd_addr = base;
1237         host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
1238         sata_dwc_setup_port(&host->ports[0]->ioaddr, base);
1239 
1240         /* Read the ID and Version Registers */
1241         idr = sata_dwc_readl(&hsdev->sata_dwc_regs->idr);
1242         versionr = sata_dwc_readl(&hsdev->sata_dwc_regs->versionr);
1243         dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
1244                    idr, ver[0], ver[1], ver[2]);
1245 
1246         /* Save dev for later use in dev_xxx() routines */
1247         hsdev->dev = &ofdev->dev;
1248 
1249         /* Enable SATA Interrupts */
1250         sata_dwc_enable_interrupts(hsdev);
1251 
1252         /* Get SATA interrupt number */
1253         irq = irq_of_parse_and_map(np, 0);
1254         if (irq == NO_IRQ) {
1255                 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1256                 err = -ENODEV;
1257                 goto error_out;
1258         }
1259 
1260 #ifdef CONFIG_SATA_DWC_OLD_DMA
1261         if (!of_find_property(np, "dmas", NULL)) {
1262                 err = sata_dwc_dma_init_old(ofdev, hsdev);
1263                 if (err)
1264                         goto error_out;
1265         }
1266 #endif
1267 
1268         hsdev->phy = devm_phy_optional_get(hsdev->dev, "sata-phy");
1269         if (IS_ERR(hsdev->phy)) {
1270                 err = PTR_ERR(hsdev->phy);
1271                 hsdev->phy = NULL;
1272                 goto error_out;
1273         }
1274 
1275         err = phy_init(hsdev->phy);
1276         if (err)
1277                 goto error_out;
1278 
1279         /*
1280          * Now, register with libATA core, this will also initiate the
1281          * device discovery process, invoking our port_start() handler &
1282          * error_handler() to execute a dummy Softreset EH session
1283          */
1284         err = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1285         if (err)
1286                 dev_err(&ofdev->dev, "failed to activate host");
1287 
1288         dev_set_drvdata(&ofdev->dev, host);
1289         return 0;
1290 
1291 error_out:
1292         phy_exit(hsdev->phy);
1293         return err;
1294 }
1295 
1296 static int sata_dwc_remove(struct platform_device *ofdev)
1297 {
1298         struct device *dev = &ofdev->dev;
1299         struct ata_host *host = dev_get_drvdata(dev);
1300         struct sata_dwc_device *hsdev = host->private_data;
1301 
1302         ata_host_detach(host);
1303 
1304         phy_exit(hsdev->phy);
1305 
1306 #ifdef CONFIG_SATA_DWC_OLD_DMA
1307         /* Free SATA DMA resources */
1308         sata_dwc_dma_exit_old(hsdev);
1309 #endif
1310 
1311         dev_dbg(&ofdev->dev, "done\n");
1312         return 0;
1313 }
1314 
1315 static const struct of_device_id sata_dwc_match[] = {
1316         { .compatible = "amcc,sata-460ex", },
1317         {}
1318 };
1319 MODULE_DEVICE_TABLE(of, sata_dwc_match);
1320 
1321 static struct platform_driver sata_dwc_driver = {
1322         .driver = {
1323                 .name = DRV_NAME,
1324                 .of_match_table = sata_dwc_match,
1325         },
1326         .probe = sata_dwc_probe,
1327         .remove = sata_dwc_remove,
1328 };
1329 
1330 module_platform_driver(sata_dwc_driver);
1331 
1332 MODULE_LICENSE("GPL");
1333 MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
1334 MODULE_DESCRIPTION("DesignWare Cores SATA controller low level driver");
1335 MODULE_VERSION(DRV_VERSION);
1336 

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