Version:  2.0.40 2.2.26 2.4.37 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7

Linux/drivers/ata/sata_dwc_460ex.c

  1 /*
  2  * drivers/ata/sata_dwc_460ex.c
  3  *
  4  * Synopsys DesignWare Cores (DWC) SATA host driver
  5  *
  6  * Author: Mark Miesfeld <mmiesfeld@amcc.com>
  7  *
  8  * Ported from 2.6.19.2 to 2.6.25/26 by Stefan Roese <sr@denx.de>
  9  * Copyright 2008 DENX Software Engineering
 10  *
 11  * Based on versions provided by AMCC and Synopsys which are:
 12  *          Copyright 2006 Applied Micro Circuits Corporation
 13  *          COPYRIGHT (C) 2005  SYNOPSYS, INC.  ALL RIGHTS RESERVED
 14  *
 15  * This program is free software; you can redistribute  it and/or modify it
 16  * under  the terms of  the GNU General  Public License as published by the
 17  * Free Software Foundation;  either version 2 of the  License, or (at your
 18  * option) any later version.
 19  */
 20 
 21 #ifdef CONFIG_SATA_DWC_DEBUG
 22 #define DEBUG
 23 #endif
 24 
 25 #ifdef CONFIG_SATA_DWC_VDEBUG
 26 #define VERBOSE_DEBUG
 27 #define DEBUG_NCQ
 28 #endif
 29 
 30 #include <linux/kernel.h>
 31 #include <linux/module.h>
 32 #include <linux/device.h>
 33 #include <linux/dmaengine.h>
 34 #include <linux/of_address.h>
 35 #include <linux/of_irq.h>
 36 #include <linux/of_platform.h>
 37 #include <linux/platform_device.h>
 38 #include <linux/phy/phy.h>
 39 #include <linux/libata.h>
 40 #include <linux/slab.h>
 41 
 42 #include "libata.h"
 43 
 44 #include <scsi/scsi_host.h>
 45 #include <scsi/scsi_cmnd.h>
 46 
 47 /* These two are defined in "libata.h" */
 48 #undef  DRV_NAME
 49 #undef  DRV_VERSION
 50 
 51 #define DRV_NAME        "sata-dwc"
 52 #define DRV_VERSION     "1.3"
 53 
 54 #define sata_dwc_writel(a, v)   writel_relaxed(v, a)
 55 #define sata_dwc_readl(a)       readl_relaxed(a)
 56 
 57 #ifndef NO_IRQ
 58 #define NO_IRQ          0
 59 #endif
 60 
 61 #define AHB_DMA_BRST_DFLT       64      /* 16 data items burst length */
 62 
 63 enum {
 64         SATA_DWC_MAX_PORTS = 1,
 65 
 66         SATA_DWC_SCR_OFFSET = 0x24,
 67         SATA_DWC_REG_OFFSET = 0x64,
 68 };
 69 
 70 /* DWC SATA Registers */
 71 struct sata_dwc_regs {
 72         u32 fptagr;             /* 1st party DMA tag */
 73         u32 fpbor;              /* 1st party DMA buffer offset */
 74         u32 fptcr;              /* 1st party DMA Xfr count */
 75         u32 dmacr;              /* DMA Control */
 76         u32 dbtsr;              /* DMA Burst Transac size */
 77         u32 intpr;              /* Interrupt Pending */
 78         u32 intmr;              /* Interrupt Mask */
 79         u32 errmr;              /* Error Mask */
 80         u32 llcr;               /* Link Layer Control */
 81         u32 phycr;              /* PHY Control */
 82         u32 physr;              /* PHY Status */
 83         u32 rxbistpd;           /* Recvd BIST pattern def register */
 84         u32 rxbistpd1;          /* Recvd BIST data dword1 */
 85         u32 rxbistpd2;          /* Recvd BIST pattern data dword2 */
 86         u32 txbistpd;           /* Trans BIST pattern def register */
 87         u32 txbistpd1;          /* Trans BIST data dword1 */
 88         u32 txbistpd2;          /* Trans BIST data dword2 */
 89         u32 bistcr;             /* BIST Control Register */
 90         u32 bistfctr;           /* BIST FIS Count Register */
 91         u32 bistsr;             /* BIST Status Register */
 92         u32 bistdecr;           /* BIST Dword Error count register */
 93         u32 res[15];            /* Reserved locations */
 94         u32 testr;              /* Test Register */
 95         u32 versionr;           /* Version Register */
 96         u32 idr;                /* ID Register */
 97         u32 unimpl[192];        /* Unimplemented */
 98         u32 dmadr[256];         /* FIFO Locations in DMA Mode */
 99 };
100 
101 enum {
102         SCR_SCONTROL_DET_ENABLE =       0x00000001,
103         SCR_SSTATUS_DET_PRESENT =       0x00000001,
104         SCR_SERROR_DIAG_X       =       0x04000000,
105 /* DWC SATA Register Operations */
106         SATA_DWC_TXFIFO_DEPTH   =       0x01FF,
107         SATA_DWC_RXFIFO_DEPTH   =       0x01FF,
108         SATA_DWC_DMACR_TMOD_TXCHEN =    0x00000004,
109         SATA_DWC_DMACR_TXCHEN   = (0x00000001 | SATA_DWC_DMACR_TMOD_TXCHEN),
110         SATA_DWC_DMACR_RXCHEN   = (0x00000002 | SATA_DWC_DMACR_TMOD_TXCHEN),
111         SATA_DWC_DMACR_TXRXCH_CLEAR =   SATA_DWC_DMACR_TMOD_TXCHEN,
112         SATA_DWC_INTPR_DMAT     =       0x00000001,
113         SATA_DWC_INTPR_NEWFP    =       0x00000002,
114         SATA_DWC_INTPR_PMABRT   =       0x00000004,
115         SATA_DWC_INTPR_ERR      =       0x00000008,
116         SATA_DWC_INTPR_NEWBIST  =       0x00000010,
117         SATA_DWC_INTPR_IPF      =       0x10000000,
118         SATA_DWC_INTMR_DMATM    =       0x00000001,
119         SATA_DWC_INTMR_NEWFPM   =       0x00000002,
120         SATA_DWC_INTMR_PMABRTM  =       0x00000004,
121         SATA_DWC_INTMR_ERRM     =       0x00000008,
122         SATA_DWC_INTMR_NEWBISTM =       0x00000010,
123         SATA_DWC_LLCR_SCRAMEN   =       0x00000001,
124         SATA_DWC_LLCR_DESCRAMEN =       0x00000002,
125         SATA_DWC_LLCR_RPDEN     =       0x00000004,
126 /* This is all error bits, zero's are reserved fields. */
127         SATA_DWC_SERROR_ERR_BITS =      0x0FFF0F03
128 };
129 
130 #define SATA_DWC_SCR0_SPD_GET(v)        (((v) >> 4) & 0x0000000F)
131 #define SATA_DWC_DMACR_TX_CLEAR(v)      (((v) & ~SATA_DWC_DMACR_TXCHEN) |\
132                                                  SATA_DWC_DMACR_TMOD_TXCHEN)
133 #define SATA_DWC_DMACR_RX_CLEAR(v)      (((v) & ~SATA_DWC_DMACR_RXCHEN) |\
134                                                  SATA_DWC_DMACR_TMOD_TXCHEN)
135 #define SATA_DWC_DBTSR_MWR(size)        (((size)/4) & SATA_DWC_TXFIFO_DEPTH)
136 #define SATA_DWC_DBTSR_MRD(size)        ((((size)/4) & SATA_DWC_RXFIFO_DEPTH)\
137                                                  << 16)
138 struct sata_dwc_device {
139         struct device           *dev;           /* generic device struct */
140         struct ata_probe_ent    *pe;            /* ptr to probe-ent */
141         struct ata_host         *host;
142         struct sata_dwc_regs __iomem *sata_dwc_regs;    /* DW SATA specific */
143         u32                     sactive_issued;
144         u32                     sactive_queued;
145         struct phy              *phy;
146         phys_addr_t             dmadr;
147 #ifdef CONFIG_SATA_DWC_OLD_DMA
148         struct dw_dma_chip      *dma;
149 #endif
150 };
151 
152 #define SATA_DWC_QCMD_MAX       32
153 
154 struct sata_dwc_device_port {
155         struct sata_dwc_device  *hsdev;
156         int                     cmd_issued[SATA_DWC_QCMD_MAX];
157         int                     dma_pending[SATA_DWC_QCMD_MAX];
158 
159         /* DMA info */
160         struct dma_chan                 *chan;
161         struct dma_async_tx_descriptor  *desc[SATA_DWC_QCMD_MAX];
162         u32                             dma_interrupt_count;
163 };
164 
165 /*
166  * Commonly used DWC SATA driver macros
167  */
168 #define HSDEV_FROM_HOST(host)   ((struct sata_dwc_device *)(host)->private_data)
169 #define HSDEV_FROM_AP(ap)       ((struct sata_dwc_device *)(ap)->host->private_data)
170 #define HSDEVP_FROM_AP(ap)      ((struct sata_dwc_device_port *)(ap)->private_data)
171 #define HSDEV_FROM_QC(qc)       ((struct sata_dwc_device *)(qc)->ap->host->private_data)
172 #define HSDEV_FROM_HSDEVP(p)    ((struct sata_dwc_device *)(p)->hsdev)
173 
174 enum {
175         SATA_DWC_CMD_ISSUED_NOT         = 0,
176         SATA_DWC_CMD_ISSUED_PEND        = 1,
177         SATA_DWC_CMD_ISSUED_EXEC        = 2,
178         SATA_DWC_CMD_ISSUED_NODATA      = 3,
179 
180         SATA_DWC_DMA_PENDING_NONE       = 0,
181         SATA_DWC_DMA_PENDING_TX         = 1,
182         SATA_DWC_DMA_PENDING_RX         = 2,
183 };
184 
185 /*
186  * Prototypes
187  */
188 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag);
189 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
190                                 u32 check_status);
191 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status);
192 static void sata_dwc_port_stop(struct ata_port *ap);
193 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag);
194 
195 #ifdef CONFIG_SATA_DWC_OLD_DMA
196 
197 #include <linux/platform_data/dma-dw.h>
198 #include <linux/dma/dw.h>
199 
200 static struct dw_dma_slave sata_dwc_dma_dws = {
201         .src_id = 0,
202         .dst_id = 0,
203         .m_master = 1,
204         .p_master = 0,
205 };
206 
207 static bool sata_dwc_dma_filter(struct dma_chan *chan, void *param)
208 {
209         struct dw_dma_slave *dws = &sata_dwc_dma_dws;
210 
211         if (dws->dma_dev != chan->device->dev)
212                 return false;
213 
214         chan->private = dws;
215         return true;
216 }
217 
218 static int sata_dwc_dma_get_channel_old(struct sata_dwc_device_port *hsdevp)
219 {
220         struct sata_dwc_device *hsdev = hsdevp->hsdev;
221         struct dw_dma_slave *dws = &sata_dwc_dma_dws;
222         dma_cap_mask_t mask;
223 
224         dws->dma_dev = hsdev->dev;
225 
226         dma_cap_zero(mask);
227         dma_cap_set(DMA_SLAVE, mask);
228 
229         /* Acquire DMA channel */
230         hsdevp->chan = dma_request_channel(mask, sata_dwc_dma_filter, hsdevp);
231         if (!hsdevp->chan) {
232                 dev_err(hsdev->dev, "%s: dma channel unavailable\n",
233                          __func__);
234                 return -EAGAIN;
235         }
236 
237         return 0;
238 }
239 
240 static int sata_dwc_dma_init_old(struct platform_device *pdev,
241                                  struct sata_dwc_device *hsdev)
242 {
243         struct device_node *np = pdev->dev.of_node;
244         struct resource *res;
245 
246         hsdev->dma = devm_kzalloc(&pdev->dev, sizeof(*hsdev->dma), GFP_KERNEL);
247         if (!hsdev->dma)
248                 return -ENOMEM;
249 
250         hsdev->dma->dev = &pdev->dev;
251 
252         /* Get SATA DMA interrupt number */
253         hsdev->dma->irq = irq_of_parse_and_map(np, 1);
254         if (hsdev->dma->irq == NO_IRQ) {
255                 dev_err(&pdev->dev, "no SATA DMA irq\n");
256                 return -ENODEV;
257         }
258 
259         /* Get physical SATA DMA register base address */
260         res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
261         hsdev->dma->regs = devm_ioremap_resource(&pdev->dev, res);
262         if (IS_ERR(hsdev->dma->regs)) {
263                 dev_err(&pdev->dev,
264                         "ioremap failed for AHBDMA register address\n");
265                 return PTR_ERR(hsdev->dma->regs);
266         }
267 
268         /* Initialize AHB DMAC */
269         return dw_dma_probe(hsdev->dma);
270 }
271 
272 static void sata_dwc_dma_exit_old(struct sata_dwc_device *hsdev)
273 {
274         if (!hsdev->dma)
275                 return;
276 
277         dw_dma_remove(hsdev->dma);
278 }
279 
280 #endif
281 
282 static const char *get_prot_descript(u8 protocol)
283 {
284         switch ((enum ata_tf_protocols)protocol) {
285         case ATA_PROT_NODATA:
286                 return "ATA no data";
287         case ATA_PROT_PIO:
288                 return "ATA PIO";
289         case ATA_PROT_DMA:
290                 return "ATA DMA";
291         case ATA_PROT_NCQ:
292                 return "ATA NCQ";
293         case ATAPI_PROT_NODATA:
294                 return "ATAPI no data";
295         case ATAPI_PROT_PIO:
296                 return "ATAPI PIO";
297         case ATAPI_PROT_DMA:
298                 return "ATAPI DMA";
299         default:
300                 return "unknown";
301         }
302 }
303 
304 static const char *get_dma_dir_descript(int dma_dir)
305 {
306         switch ((enum dma_data_direction)dma_dir) {
307         case DMA_BIDIRECTIONAL:
308                 return "bidirectional";
309         case DMA_TO_DEVICE:
310                 return "to device";
311         case DMA_FROM_DEVICE:
312                 return "from device";
313         default:
314                 return "none";
315         }
316 }
317 
318 static void sata_dwc_tf_dump(struct ata_port *ap, struct ata_taskfile *tf)
319 {
320         dev_vdbg(ap->dev,
321                 "taskfile cmd: 0x%02x protocol: %s flags: 0x%lx device: %x\n",
322                 tf->command, get_prot_descript(tf->protocol), tf->flags,
323                 tf->device);
324         dev_vdbg(ap->dev,
325                 "feature: 0x%02x nsect: 0x%x lbal: 0x%x lbam: 0x%x lbah: 0x%x\n",
326                 tf->feature, tf->nsect, tf->lbal, tf->lbam, tf->lbah);
327         dev_vdbg(ap->dev,
328                 "hob_feature: 0x%02x hob_nsect: 0x%x hob_lbal: 0x%x hob_lbam: 0x%x hob_lbah: 0x%x\n",
329                 tf->hob_feature, tf->hob_nsect, tf->hob_lbal, tf->hob_lbam,
330                 tf->hob_lbah);
331 }
332 
333 static void dma_dwc_xfer_done(void *hsdev_instance)
334 {
335         unsigned long flags;
336         struct sata_dwc_device *hsdev = hsdev_instance;
337         struct ata_host *host = (struct ata_host *)hsdev->host;
338         struct ata_port *ap;
339         struct sata_dwc_device_port *hsdevp;
340         u8 tag = 0;
341         unsigned int port = 0;
342 
343         spin_lock_irqsave(&host->lock, flags);
344         ap = host->ports[port];
345         hsdevp = HSDEVP_FROM_AP(ap);
346         tag = ap->link.active_tag;
347 
348         /*
349          * Each DMA command produces 2 interrupts.  Only
350          * complete the command after both interrupts have been
351          * seen. (See sata_dwc_isr())
352          */
353         hsdevp->dma_interrupt_count++;
354         sata_dwc_clear_dmacr(hsdevp, tag);
355 
356         if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
357                 dev_err(ap->dev, "DMA not pending tag=0x%02x pending=%d\n",
358                         tag, hsdevp->dma_pending[tag]);
359         }
360 
361         if ((hsdevp->dma_interrupt_count % 2) == 0)
362                 sata_dwc_dma_xfer_complete(ap, 1);
363 
364         spin_unlock_irqrestore(&host->lock, flags);
365 }
366 
367 static struct dma_async_tx_descriptor *dma_dwc_xfer_setup(struct ata_queued_cmd *qc)
368 {
369         struct ata_port *ap = qc->ap;
370         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
371         struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
372         struct dma_slave_config sconf;
373         struct dma_async_tx_descriptor *desc;
374 
375         if (qc->dma_dir == DMA_DEV_TO_MEM) {
376                 sconf.src_addr = hsdev->dmadr;
377                 sconf.device_fc = false;
378         } else {        /* DMA_MEM_TO_DEV */
379                 sconf.dst_addr = hsdev->dmadr;
380                 sconf.device_fc = false;
381         }
382 
383         sconf.direction = qc->dma_dir;
384         sconf.src_maxburst = AHB_DMA_BRST_DFLT / 4;     /* in items */
385         sconf.dst_maxburst = AHB_DMA_BRST_DFLT / 4;     /* in items */
386         sconf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
387         sconf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
388 
389         dmaengine_slave_config(hsdevp->chan, &sconf);
390 
391         /* Convert SG list to linked list of items (LLIs) for AHB DMA */
392         desc = dmaengine_prep_slave_sg(hsdevp->chan, qc->sg, qc->n_elem,
393                                        qc->dma_dir,
394                                        DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
395 
396         if (!desc)
397                 return NULL;
398 
399         desc->callback = dma_dwc_xfer_done;
400         desc->callback_param = hsdev;
401 
402         dev_dbg(hsdev->dev, "%s sg: 0x%p, count: %d addr: %pa\n", __func__,
403                 qc->sg, qc->n_elem, &hsdev->dmadr);
404 
405         return desc;
406 }
407 
408 static int sata_dwc_scr_read(struct ata_link *link, unsigned int scr, u32 *val)
409 {
410         if (scr > SCR_NOTIFICATION) {
411                 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
412                         __func__, scr);
413                 return -EINVAL;
414         }
415 
416         *val = sata_dwc_readl(link->ap->ioaddr.scr_addr + (scr * 4));
417         dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=0x%08x\n", __func__,
418                 link->ap->print_id, scr, *val);
419 
420         return 0;
421 }
422 
423 static int sata_dwc_scr_write(struct ata_link *link, unsigned int scr, u32 val)
424 {
425         dev_dbg(link->ap->dev, "%s: id=%d reg=%d val=0x%08x\n", __func__,
426                 link->ap->print_id, scr, val);
427         if (scr > SCR_NOTIFICATION) {
428                 dev_err(link->ap->dev, "%s: Incorrect SCR offset 0x%02x\n",
429                          __func__, scr);
430                 return -EINVAL;
431         }
432         sata_dwc_writel(link->ap->ioaddr.scr_addr + (scr * 4), val);
433 
434         return 0;
435 }
436 
437 static void clear_serror(struct ata_port *ap)
438 {
439         u32 val;
440         sata_dwc_scr_read(&ap->link, SCR_ERROR, &val);
441         sata_dwc_scr_write(&ap->link, SCR_ERROR, val);
442 }
443 
444 static void clear_interrupt_bit(struct sata_dwc_device *hsdev, u32 bit)
445 {
446         sata_dwc_writel(&hsdev->sata_dwc_regs->intpr,
447                         sata_dwc_readl(&hsdev->sata_dwc_regs->intpr));
448 }
449 
450 static u32 qcmd_tag_to_mask(u8 tag)
451 {
452         return 0x00000001 << (tag & 0x1f);
453 }
454 
455 /* See ahci.c */
456 static void sata_dwc_error_intr(struct ata_port *ap,
457                                 struct sata_dwc_device *hsdev, uint intpr)
458 {
459         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
460         struct ata_eh_info *ehi = &ap->link.eh_info;
461         unsigned int err_mask = 0, action = 0;
462         struct ata_queued_cmd *qc;
463         u32 serror;
464         u8 status, tag;
465 
466         ata_ehi_clear_desc(ehi);
467 
468         sata_dwc_scr_read(&ap->link, SCR_ERROR, &serror);
469         status = ap->ops->sff_check_status(ap);
470 
471         tag = ap->link.active_tag;
472 
473         dev_err(ap->dev,
474                 "%s SCR_ERROR=0x%08x intpr=0x%08x status=0x%08x dma_intp=%d pending=%d issued=%d",
475                 __func__, serror, intpr, status, hsdevp->dma_interrupt_count,
476                 hsdevp->dma_pending[tag], hsdevp->cmd_issued[tag]);
477 
478         /* Clear error register and interrupt bit */
479         clear_serror(ap);
480         clear_interrupt_bit(hsdev, SATA_DWC_INTPR_ERR);
481 
482         /* This is the only error happening now.  TODO check for exact error */
483 
484         err_mask |= AC_ERR_HOST_BUS;
485         action |= ATA_EH_RESET;
486 
487         /* Pass this on to EH */
488         ehi->serror |= serror;
489         ehi->action |= action;
490 
491         qc = ata_qc_from_tag(ap, tag);
492         if (qc)
493                 qc->err_mask |= err_mask;
494         else
495                 ehi->err_mask |= err_mask;
496 
497         ata_port_abort(ap);
498 }
499 
500 /*
501  * Function : sata_dwc_isr
502  * arguments : irq, void *dev_instance, struct pt_regs *regs
503  * Return value : irqreturn_t - status of IRQ
504  * This Interrupt handler called via port ops registered function.
505  * .irq_handler = sata_dwc_isr
506  */
507 static irqreturn_t sata_dwc_isr(int irq, void *dev_instance)
508 {
509         struct ata_host *host = (struct ata_host *)dev_instance;
510         struct sata_dwc_device *hsdev = HSDEV_FROM_HOST(host);
511         struct ata_port *ap;
512         struct ata_queued_cmd *qc;
513         unsigned long flags;
514         u8 status, tag;
515         int handled, num_processed, port = 0;
516         uint intpr, sactive, sactive2, tag_mask;
517         struct sata_dwc_device_port *hsdevp;
518         hsdev->sactive_issued = 0;
519 
520         spin_lock_irqsave(&host->lock, flags);
521 
522         /* Read the interrupt register */
523         intpr = sata_dwc_readl(&hsdev->sata_dwc_regs->intpr);
524 
525         ap = host->ports[port];
526         hsdevp = HSDEVP_FROM_AP(ap);
527 
528         dev_dbg(ap->dev, "%s intpr=0x%08x active_tag=%d\n", __func__, intpr,
529                 ap->link.active_tag);
530 
531         /* Check for error interrupt */
532         if (intpr & SATA_DWC_INTPR_ERR) {
533                 sata_dwc_error_intr(ap, hsdev, intpr);
534                 handled = 1;
535                 goto DONE;
536         }
537 
538         /* Check for DMA SETUP FIS (FP DMA) interrupt */
539         if (intpr & SATA_DWC_INTPR_NEWFP) {
540                 clear_interrupt_bit(hsdev, SATA_DWC_INTPR_NEWFP);
541 
542                 tag = (u8)(sata_dwc_readl(&hsdev->sata_dwc_regs->fptagr));
543                 dev_dbg(ap->dev, "%s: NEWFP tag=%d\n", __func__, tag);
544                 if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_PEND)
545                         dev_warn(ap->dev, "CMD tag=%d not pending?\n", tag);
546 
547                 hsdev->sactive_issued |= qcmd_tag_to_mask(tag);
548 
549                 qc = ata_qc_from_tag(ap, tag);
550                 /*
551                  * Start FP DMA for NCQ command.  At this point the tag is the
552                  * active tag.  It is the tag that matches the command about to
553                  * be completed.
554                  */
555                 qc->ap->link.active_tag = tag;
556                 sata_dwc_bmdma_start_by_tag(qc, tag);
557 
558                 handled = 1;
559                 goto DONE;
560         }
561         sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
562         tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
563 
564         /* If no sactive issued and tag_mask is zero then this is not NCQ */
565         if (hsdev->sactive_issued == 0 && tag_mask == 0) {
566                 if (ap->link.active_tag == ATA_TAG_POISON)
567                         tag = 0;
568                 else
569                         tag = ap->link.active_tag;
570                 qc = ata_qc_from_tag(ap, tag);
571 
572                 /* DEV interrupt w/ no active qc? */
573                 if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) {
574                         dev_err(ap->dev,
575                                 "%s interrupt with no active qc qc=%p\n",
576                                 __func__, qc);
577                         ap->ops->sff_check_status(ap);
578                         handled = 1;
579                         goto DONE;
580                 }
581                 status = ap->ops->sff_check_status(ap);
582 
583                 qc->ap->link.active_tag = tag;
584                 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
585 
586                 if (status & ATA_ERR) {
587                         dev_dbg(ap->dev, "interrupt ATA_ERR (0x%x)\n", status);
588                         sata_dwc_qc_complete(ap, qc, 1);
589                         handled = 1;
590                         goto DONE;
591                 }
592 
593                 dev_dbg(ap->dev, "%s non-NCQ cmd interrupt, protocol: %s\n",
594                         __func__, get_prot_descript(qc->tf.protocol));
595 DRVSTILLBUSY:
596                 if (ata_is_dma(qc->tf.protocol)) {
597                         /*
598                          * Each DMA transaction produces 2 interrupts. The DMAC
599                          * transfer complete interrupt and the SATA controller
600                          * operation done interrupt. The command should be
601                          * completed only after both interrupts are seen.
602                          */
603                         hsdevp->dma_interrupt_count++;
604                         if (hsdevp->dma_pending[tag] == \
605                                         SATA_DWC_DMA_PENDING_NONE) {
606                                 dev_err(ap->dev,
607                                         "%s: DMA not pending intpr=0x%08x status=0x%08x pending=%d\n",
608                                         __func__, intpr, status,
609                                         hsdevp->dma_pending[tag]);
610                         }
611 
612                         if ((hsdevp->dma_interrupt_count % 2) == 0)
613                                 sata_dwc_dma_xfer_complete(ap, 1);
614                 } else if (ata_is_pio(qc->tf.protocol)) {
615                         ata_sff_hsm_move(ap, qc, status, 0);
616                         handled = 1;
617                         goto DONE;
618                 } else {
619                         if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
620                                 goto DRVSTILLBUSY;
621                 }
622 
623                 handled = 1;
624                 goto DONE;
625         }
626 
627         /*
628          * This is a NCQ command. At this point we need to figure out for which
629          * tags we have gotten a completion interrupt.  One interrupt may serve
630          * as completion for more than one operation when commands are queued
631          * (NCQ).  We need to process each completed command.
632          */
633 
634          /* process completed commands */
635         sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
636         tag_mask = (hsdev->sactive_issued | sactive) ^ sactive;
637 
638         if (sactive != 0 || hsdev->sactive_issued > 1 || tag_mask > 1) {
639                 dev_dbg(ap->dev,
640                         "%s NCQ:sactive=0x%08x  sactive_issued=0x%08x tag_mask=0x%08x\n",
641                         __func__, sactive, hsdev->sactive_issued, tag_mask);
642         }
643 
644         if ((tag_mask | hsdev->sactive_issued) != hsdev->sactive_issued) {
645                 dev_warn(ap->dev,
646                          "Bad tag mask?  sactive=0x%08x sactive_issued=0x%08x  tag_mask=0x%08x\n",
647                          sactive, hsdev->sactive_issued, tag_mask);
648         }
649 
650         /* read just to clear ... not bad if currently still busy */
651         status = ap->ops->sff_check_status(ap);
652         dev_dbg(ap->dev, "%s ATA status register=0x%x\n", __func__, status);
653 
654         tag = 0;
655         num_processed = 0;
656         while (tag_mask) {
657                 num_processed++;
658                 while (!(tag_mask & 0x00000001)) {
659                         tag++;
660                         tag_mask <<= 1;
661                 }
662 
663                 tag_mask &= (~0x00000001);
664                 qc = ata_qc_from_tag(ap, tag);
665 
666                 /* To be picked up by completion functions */
667                 qc->ap->link.active_tag = tag;
668                 hsdevp->cmd_issued[tag] = SATA_DWC_CMD_ISSUED_NOT;
669 
670                 /* Let libata/scsi layers handle error */
671                 if (status & ATA_ERR) {
672                         dev_dbg(ap->dev, "%s ATA_ERR (0x%x)\n", __func__,
673                                 status);
674                         sata_dwc_qc_complete(ap, qc, 1);
675                         handled = 1;
676                         goto DONE;
677                 }
678 
679                 /* Process completed command */
680                 dev_dbg(ap->dev, "%s NCQ command, protocol: %s\n", __func__,
681                         get_prot_descript(qc->tf.protocol));
682                 if (ata_is_dma(qc->tf.protocol)) {
683                         hsdevp->dma_interrupt_count++;
684                         if (hsdevp->dma_pending[tag] == \
685                                         SATA_DWC_DMA_PENDING_NONE)
686                                 dev_warn(ap->dev, "%s: DMA not pending?\n",
687                                         __func__);
688                         if ((hsdevp->dma_interrupt_count % 2) == 0)
689                                 sata_dwc_dma_xfer_complete(ap, 1);
690                 } else {
691                         if (unlikely(sata_dwc_qc_complete(ap, qc, 1)))
692                                 goto STILLBUSY;
693                 }
694                 continue;
695 
696 STILLBUSY:
697                 ap->stats.idle_irq++;
698                 dev_warn(ap->dev, "STILL BUSY IRQ ata%d: irq trap\n",
699                         ap->print_id);
700         } /* while tag_mask */
701 
702         /*
703          * Check to see if any commands completed while we were processing our
704          * initial set of completed commands (read status clears interrupts,
705          * so we might miss a completed command interrupt if one came in while
706          * we were processing --we read status as part of processing a completed
707          * command).
708          */
709         sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive2);
710         if (sactive2 != sactive) {
711                 dev_dbg(ap->dev,
712                         "More completed - sactive=0x%x sactive2=0x%x\n",
713                         sactive, sactive2);
714         }
715         handled = 1;
716 
717 DONE:
718         spin_unlock_irqrestore(&host->lock, flags);
719         return IRQ_RETVAL(handled);
720 }
721 
722 static void sata_dwc_clear_dmacr(struct sata_dwc_device_port *hsdevp, u8 tag)
723 {
724         struct sata_dwc_device *hsdev = HSDEV_FROM_HSDEVP(hsdevp);
725         u32 dmacr = sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr);
726 
727         if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX) {
728                 dmacr = SATA_DWC_DMACR_RX_CLEAR(dmacr);
729                 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr);
730         } else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX) {
731                 dmacr = SATA_DWC_DMACR_TX_CLEAR(dmacr);
732                 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr, dmacr);
733         } else {
734                 /*
735                  * This should not happen, it indicates the driver is out of
736                  * sync.  If it does happen, clear dmacr anyway.
737                  */
738                 dev_err(hsdev->dev,
739                         "%s DMA protocol RX and TX DMA not pending tag=0x%02x pending=%d dmacr: 0x%08x\n",
740                         __func__, tag, hsdevp->dma_pending[tag], dmacr);
741                 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
742                                 SATA_DWC_DMACR_TXRXCH_CLEAR);
743         }
744 }
745 
746 static void sata_dwc_dma_xfer_complete(struct ata_port *ap, u32 check_status)
747 {
748         struct ata_queued_cmd *qc;
749         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
750         struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
751         u8 tag = 0;
752 
753         tag = ap->link.active_tag;
754         qc = ata_qc_from_tag(ap, tag);
755         if (!qc) {
756                 dev_err(ap->dev, "failed to get qc");
757                 return;
758         }
759 
760 #ifdef DEBUG_NCQ
761         if (tag > 0) {
762                 dev_info(ap->dev,
763                          "%s tag=%u cmd=0x%02x dma dir=%s proto=%s dmacr=0x%08x\n",
764                          __func__, qc->tag, qc->tf.command,
765                          get_dma_dir_descript(qc->dma_dir),
766                          get_prot_descript(qc->tf.protocol),
767                          sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
768         }
769 #endif
770 
771         if (ata_is_dma(qc->tf.protocol)) {
772                 if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_NONE) {
773                         dev_err(ap->dev,
774                                 "%s DMA protocol RX and TX DMA not pending dmacr: 0x%08x\n",
775                                 __func__,
776                                 sata_dwc_readl(&hsdev->sata_dwc_regs->dmacr));
777                 }
778 
779                 hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_NONE;
780                 sata_dwc_qc_complete(ap, qc, check_status);
781                 ap->link.active_tag = ATA_TAG_POISON;
782         } else {
783                 sata_dwc_qc_complete(ap, qc, check_status);
784         }
785 }
786 
787 static int sata_dwc_qc_complete(struct ata_port *ap, struct ata_queued_cmd *qc,
788                                 u32 check_status)
789 {
790         u8 status = 0;
791         u32 mask = 0x0;
792         u8 tag = qc->tag;
793         struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
794         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
795         hsdev->sactive_queued = 0;
796         dev_dbg(ap->dev, "%s checkstatus? %x\n", __func__, check_status);
797 
798         if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_TX)
799                 dev_err(ap->dev, "TX DMA PENDING\n");
800         else if (hsdevp->dma_pending[tag] == SATA_DWC_DMA_PENDING_RX)
801                 dev_err(ap->dev, "RX DMA PENDING\n");
802         dev_dbg(ap->dev,
803                 "QC complete cmd=0x%02x status=0x%02x ata%u: protocol=%d\n",
804                 qc->tf.command, status, ap->print_id, qc->tf.protocol);
805 
806         /* clear active bit */
807         mask = (~(qcmd_tag_to_mask(tag)));
808         hsdev->sactive_queued = hsdev->sactive_queued & mask;
809         hsdev->sactive_issued = hsdev->sactive_issued & mask;
810         ata_qc_complete(qc);
811         return 0;
812 }
813 
814 static void sata_dwc_enable_interrupts(struct sata_dwc_device *hsdev)
815 {
816         /* Enable selective interrupts by setting the interrupt maskregister*/
817         sata_dwc_writel(&hsdev->sata_dwc_regs->intmr,
818                         SATA_DWC_INTMR_ERRM |
819                         SATA_DWC_INTMR_NEWFPM |
820                         SATA_DWC_INTMR_PMABRTM |
821                         SATA_DWC_INTMR_DMATM);
822         /*
823          * Unmask the error bits that should trigger an error interrupt by
824          * setting the error mask register.
825          */
826         sata_dwc_writel(&hsdev->sata_dwc_regs->errmr, SATA_DWC_SERROR_ERR_BITS);
827 
828         dev_dbg(hsdev->dev, "%s: INTMR = 0x%08x, ERRMR = 0x%08x\n",
829                  __func__, sata_dwc_readl(&hsdev->sata_dwc_regs->intmr),
830                 sata_dwc_readl(&hsdev->sata_dwc_regs->errmr));
831 }
832 
833 static void sata_dwc_setup_port(struct ata_ioports *port, void __iomem *base)
834 {
835         port->cmd_addr          = base + 0x00;
836         port->data_addr         = base + 0x00;
837 
838         port->error_addr        = base + 0x04;
839         port->feature_addr      = base + 0x04;
840 
841         port->nsect_addr        = base + 0x08;
842 
843         port->lbal_addr         = base + 0x0c;
844         port->lbam_addr         = base + 0x10;
845         port->lbah_addr         = base + 0x14;
846 
847         port->device_addr       = base + 0x18;
848         port->command_addr      = base + 0x1c;
849         port->status_addr       = base + 0x1c;
850 
851         port->altstatus_addr    = base + 0x20;
852         port->ctl_addr          = base + 0x20;
853 }
854 
855 static int sata_dwc_dma_get_channel(struct sata_dwc_device_port *hsdevp)
856 {
857         struct sata_dwc_device *hsdev = hsdevp->hsdev;
858         struct device *dev = hsdev->dev;
859 
860 #ifdef CONFIG_SATA_DWC_OLD_DMA
861         if (!of_find_property(dev->of_node, "dmas", NULL))
862                 return sata_dwc_dma_get_channel_old(hsdevp);
863 #endif
864 
865         hsdevp->chan = dma_request_chan(dev, "sata-dma");
866         if (IS_ERR(hsdevp->chan)) {
867                 dev_err(dev, "failed to allocate dma channel: %ld\n",
868                         PTR_ERR(hsdevp->chan));
869                 return PTR_ERR(hsdevp->chan);
870         }
871 
872         return 0;
873 }
874 
875 /*
876  * Function : sata_dwc_port_start
877  * arguments : struct ata_ioports *port
878  * Return value : returns 0 if success, error code otherwise
879  * This function allocates the scatter gather LLI table for AHB DMA
880  */
881 static int sata_dwc_port_start(struct ata_port *ap)
882 {
883         int err = 0;
884         struct sata_dwc_device *hsdev;
885         struct sata_dwc_device_port *hsdevp = NULL;
886         struct device *pdev;
887         int i;
888 
889         hsdev = HSDEV_FROM_AP(ap);
890 
891         dev_dbg(ap->dev, "%s: port_no=%d\n", __func__, ap->port_no);
892 
893         hsdev->host = ap->host;
894         pdev = ap->host->dev;
895         if (!pdev) {
896                 dev_err(ap->dev, "%s: no ap->host->dev\n", __func__);
897                 err = -ENODEV;
898                 goto CLEANUP;
899         }
900 
901         /* Allocate Port Struct */
902         hsdevp = kzalloc(sizeof(*hsdevp), GFP_KERNEL);
903         if (!hsdevp) {
904                 dev_err(ap->dev, "%s: kmalloc failed for hsdevp\n", __func__);
905                 err = -ENOMEM;
906                 goto CLEANUP;
907         }
908         hsdevp->hsdev = hsdev;
909 
910         err = sata_dwc_dma_get_channel(hsdevp);
911         if (err)
912                 goto CLEANUP_ALLOC;
913 
914         err = phy_power_on(hsdev->phy);
915         if (err)
916                 goto CLEANUP_ALLOC;
917 
918         for (i = 0; i < SATA_DWC_QCMD_MAX; i++)
919                 hsdevp->cmd_issued[i] = SATA_DWC_CMD_ISSUED_NOT;
920 
921         ap->bmdma_prd = NULL;   /* set these so libata doesn't use them */
922         ap->bmdma_prd_dma = 0;
923 
924         if (ap->port_no == 0)  {
925                 dev_dbg(ap->dev, "%s: clearing TXCHEN, RXCHEN in DMAC\n",
926                         __func__);
927                 sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
928                                 SATA_DWC_DMACR_TXRXCH_CLEAR);
929 
930                 dev_dbg(ap->dev, "%s: setting burst size in DBTSR\n",
931                          __func__);
932                 sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
933                                 (SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
934                                  SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT)));
935         }
936 
937         /* Clear any error bits before libata starts issuing commands */
938         clear_serror(ap);
939         ap->private_data = hsdevp;
940         dev_dbg(ap->dev, "%s: done\n", __func__);
941         return 0;
942 
943 CLEANUP_ALLOC:
944         kfree(hsdevp);
945 CLEANUP:
946         dev_dbg(ap->dev, "%s: fail. ap->id = %d\n", __func__, ap->print_id);
947         return err;
948 }
949 
950 static void sata_dwc_port_stop(struct ata_port *ap)
951 {
952         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
953         struct sata_dwc_device *hsdev = HSDEV_FROM_AP(ap);
954 
955         dev_dbg(ap->dev, "%s: ap->id = %d\n", __func__, ap->print_id);
956 
957         dmaengine_terminate_sync(hsdevp->chan);
958         dma_release_channel(hsdevp->chan);
959         phy_power_off(hsdev->phy);
960 
961         kfree(hsdevp);
962         ap->private_data = NULL;
963 }
964 
965 /*
966  * Function : sata_dwc_exec_command_by_tag
967  * arguments : ata_port *ap, ata_taskfile *tf, u8 tag, u32 cmd_issued
968  * Return value : None
969  * This function keeps track of individual command tag ids and calls
970  * ata_exec_command in libata
971  */
972 static void sata_dwc_exec_command_by_tag(struct ata_port *ap,
973                                          struct ata_taskfile *tf,
974                                          u8 tag, u32 cmd_issued)
975 {
976         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
977 
978         dev_dbg(ap->dev, "%s cmd(0x%02x): %s tag=%d\n", __func__, tf->command,
979                 ata_get_cmd_descript(tf->command), tag);
980 
981         hsdevp->cmd_issued[tag] = cmd_issued;
982 
983         /*
984          * Clear SError before executing a new command.
985          * sata_dwc_scr_write and read can not be used here. Clearing the PM
986          * managed SError register for the disk needs to be done before the
987          * task file is loaded.
988          */
989         clear_serror(ap);
990         ata_sff_exec_command(ap, tf);
991 }
992 
993 static void sata_dwc_bmdma_setup_by_tag(struct ata_queued_cmd *qc, u8 tag)
994 {
995         sata_dwc_exec_command_by_tag(qc->ap, &qc->tf, tag,
996                                      SATA_DWC_CMD_ISSUED_PEND);
997 }
998 
999 static void sata_dwc_bmdma_setup(struct ata_queued_cmd *qc)
1000 {
1001         u8 tag = qc->tag;
1002 
1003         if (ata_is_ncq(qc->tf.protocol)) {
1004                 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1005                         __func__, qc->ap->link.sactive, tag);
1006         } else {
1007                 tag = 0;
1008         }
1009         sata_dwc_bmdma_setup_by_tag(qc, tag);
1010 }
1011 
1012 static void sata_dwc_bmdma_start_by_tag(struct ata_queued_cmd *qc, u8 tag)
1013 {
1014         int start_dma;
1015         u32 reg;
1016         struct sata_dwc_device *hsdev = HSDEV_FROM_QC(qc);
1017         struct ata_port *ap = qc->ap;
1018         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1019         struct dma_async_tx_descriptor *desc = hsdevp->desc[tag];
1020         int dir = qc->dma_dir;
1021 
1022         if (hsdevp->cmd_issued[tag] != SATA_DWC_CMD_ISSUED_NOT) {
1023                 start_dma = 1;
1024                 if (dir == DMA_TO_DEVICE)
1025                         hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_TX;
1026                 else
1027                         hsdevp->dma_pending[tag] = SATA_DWC_DMA_PENDING_RX;
1028         } else {
1029                 dev_err(ap->dev,
1030                         "%s: Command not pending cmd_issued=%d (tag=%d) DMA NOT started\n",
1031                         __func__, hsdevp->cmd_issued[tag], tag);
1032                 start_dma = 0;
1033         }
1034 
1035         dev_dbg(ap->dev,
1036                 "%s qc=%p tag: %x cmd: 0x%02x dma_dir: %s start_dma? %x\n",
1037                 __func__, qc, tag, qc->tf.command,
1038                 get_dma_dir_descript(qc->dma_dir), start_dma);
1039         sata_dwc_tf_dump(ap, &qc->tf);
1040 
1041         if (start_dma) {
1042                 sata_dwc_scr_read(&ap->link, SCR_ERROR, &reg);
1043                 if (reg & SATA_DWC_SERROR_ERR_BITS) {
1044                         dev_err(ap->dev, "%s: ****** SError=0x%08x ******\n",
1045                                 __func__, reg);
1046                 }
1047 
1048                 if (dir == DMA_TO_DEVICE)
1049                         sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1050                                         SATA_DWC_DMACR_TXCHEN);
1051                 else
1052                         sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1053                                         SATA_DWC_DMACR_RXCHEN);
1054 
1055                 /* Enable AHB DMA transfer on the specified channel */
1056                 dmaengine_submit(desc);
1057                 dma_async_issue_pending(hsdevp->chan);
1058         }
1059 }
1060 
1061 static void sata_dwc_bmdma_start(struct ata_queued_cmd *qc)
1062 {
1063         u8 tag = qc->tag;
1064 
1065         if (ata_is_ncq(qc->tf.protocol)) {
1066                 dev_dbg(qc->ap->dev, "%s: ap->link.sactive=0x%08x tag=%d\n",
1067                         __func__, qc->ap->link.sactive, tag);
1068         } else {
1069                 tag = 0;
1070         }
1071         dev_dbg(qc->ap->dev, "%s\n", __func__);
1072         sata_dwc_bmdma_start_by_tag(qc, tag);
1073 }
1074 
1075 static unsigned int sata_dwc_qc_issue(struct ata_queued_cmd *qc)
1076 {
1077         u32 sactive;
1078         u8 tag = qc->tag;
1079         struct ata_port *ap = qc->ap;
1080         struct sata_dwc_device_port *hsdevp = HSDEVP_FROM_AP(ap);
1081 
1082 #ifdef DEBUG_NCQ
1083         if (qc->tag > 0 || ap->link.sactive > 1)
1084                 dev_info(ap->dev,
1085                          "%s ap id=%d cmd(0x%02x)=%s qc tag=%d prot=%s ap active_tag=0x%08x ap sactive=0x%08x\n",
1086                          __func__, ap->print_id, qc->tf.command,
1087                          ata_get_cmd_descript(qc->tf.command),
1088                          qc->tag, get_prot_descript(qc->tf.protocol),
1089                          ap->link.active_tag, ap->link.sactive);
1090 #endif
1091 
1092         if (!ata_is_ncq(qc->tf.protocol))
1093                 tag = 0;
1094 
1095         if (ata_is_dma(qc->tf.protocol)) {
1096                 hsdevp->desc[tag] = dma_dwc_xfer_setup(qc);
1097                 if (!hsdevp->desc[tag])
1098                         return AC_ERR_SYSTEM;
1099         } else {
1100                 hsdevp->desc[tag] = NULL;
1101         }
1102 
1103         if (ata_is_ncq(qc->tf.protocol)) {
1104                 sata_dwc_scr_read(&ap->link, SCR_ACTIVE, &sactive);
1105                 sactive |= (0x00000001 << tag);
1106                 sata_dwc_scr_write(&ap->link, SCR_ACTIVE, sactive);
1107 
1108                 dev_dbg(qc->ap->dev,
1109                         "%s: tag=%d ap->link.sactive = 0x%08x sactive=0x%08x\n",
1110                         __func__, tag, qc->ap->link.sactive, sactive);
1111 
1112                 ap->ops->sff_tf_load(ap, &qc->tf);
1113                 sata_dwc_exec_command_by_tag(ap, &qc->tf, tag,
1114                                              SATA_DWC_CMD_ISSUED_PEND);
1115         } else {
1116                 return ata_bmdma_qc_issue(qc);
1117         }
1118         return 0;
1119 }
1120 
1121 static void sata_dwc_error_handler(struct ata_port *ap)
1122 {
1123         ata_sff_error_handler(ap);
1124 }
1125 
1126 static int sata_dwc_hardreset(struct ata_link *link, unsigned int *class,
1127                               unsigned long deadline)
1128 {
1129         struct sata_dwc_device *hsdev = HSDEV_FROM_AP(link->ap);
1130         int ret;
1131 
1132         ret = sata_sff_hardreset(link, class, deadline);
1133 
1134         sata_dwc_enable_interrupts(hsdev);
1135 
1136         /* Reconfigure the DMA control register */
1137         sata_dwc_writel(&hsdev->sata_dwc_regs->dmacr,
1138                         SATA_DWC_DMACR_TXRXCH_CLEAR);
1139 
1140         /* Reconfigure the DMA Burst Transaction Size register */
1141         sata_dwc_writel(&hsdev->sata_dwc_regs->dbtsr,
1142                         SATA_DWC_DBTSR_MWR(AHB_DMA_BRST_DFLT) |
1143                         SATA_DWC_DBTSR_MRD(AHB_DMA_BRST_DFLT));
1144 
1145         return ret;
1146 }
1147 
1148 static void sata_dwc_dev_select(struct ata_port *ap, unsigned int device)
1149 {
1150         /* SATA DWC is master only */
1151 }
1152 
1153 /*
1154  * scsi mid-layer and libata interface structures
1155  */
1156 static struct scsi_host_template sata_dwc_sht = {
1157         ATA_NCQ_SHT(DRV_NAME),
1158         /*
1159          * test-only: Currently this driver doesn't handle NCQ
1160          * correctly. We enable NCQ but set the queue depth to a
1161          * max of 1. This will get fixed in in a future release.
1162          */
1163         .sg_tablesize           = LIBATA_MAX_PRD,
1164         /* .can_queue           = ATA_MAX_QUEUE, */
1165         /*
1166          * Make sure a LLI block is not created that will span 8K max FIS
1167          * boundary. If the block spans such a FIS boundary, there is a chance
1168          * that a DMA burst will cross that boundary -- this results in an
1169          * error in the host controller.
1170          */
1171         .dma_boundary           = 0x1fff /* ATA_DMA_BOUNDARY */,
1172 };
1173 
1174 static struct ata_port_operations sata_dwc_ops = {
1175         .inherits               = &ata_sff_port_ops,
1176 
1177         .error_handler          = sata_dwc_error_handler,
1178         .hardreset              = sata_dwc_hardreset,
1179 
1180         .qc_issue               = sata_dwc_qc_issue,
1181 
1182         .scr_read               = sata_dwc_scr_read,
1183         .scr_write              = sata_dwc_scr_write,
1184 
1185         .port_start             = sata_dwc_port_start,
1186         .port_stop              = sata_dwc_port_stop,
1187 
1188         .sff_dev_select         = sata_dwc_dev_select,
1189 
1190         .bmdma_setup            = sata_dwc_bmdma_setup,
1191         .bmdma_start            = sata_dwc_bmdma_start,
1192 };
1193 
1194 static const struct ata_port_info sata_dwc_port_info[] = {
1195         {
1196                 .flags          = ATA_FLAG_SATA | ATA_FLAG_NCQ,
1197                 .pio_mask       = ATA_PIO4,
1198                 .udma_mask      = ATA_UDMA6,
1199                 .port_ops       = &sata_dwc_ops,
1200         },
1201 };
1202 
1203 static int sata_dwc_probe(struct platform_device *ofdev)
1204 {
1205         struct sata_dwc_device *hsdev;
1206         u32 idr, versionr;
1207         char *ver = (char *)&versionr;
1208         void __iomem *base;
1209         int err = 0;
1210         int irq;
1211         struct ata_host *host;
1212         struct ata_port_info pi = sata_dwc_port_info[0];
1213         const struct ata_port_info *ppi[] = { &pi, NULL };
1214         struct device_node *np = ofdev->dev.of_node;
1215         struct resource *res;
1216 
1217         /* Allocate DWC SATA device */
1218         host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_DWC_MAX_PORTS);
1219         hsdev = devm_kzalloc(&ofdev->dev, sizeof(*hsdev), GFP_KERNEL);
1220         if (!host || !hsdev)
1221                 return -ENOMEM;
1222 
1223         host->private_data = hsdev;
1224 
1225         /* Ioremap SATA registers */
1226         res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
1227         base = devm_ioremap_resource(&ofdev->dev, res);
1228         if (IS_ERR(base)) {
1229                 dev_err(&ofdev->dev,
1230                         "ioremap failed for SATA register address\n");
1231                 return PTR_ERR(base);
1232         }
1233         dev_dbg(&ofdev->dev, "ioremap done for SATA register address\n");
1234 
1235         /* Synopsys DWC SATA specific Registers */
1236         hsdev->sata_dwc_regs = base + SATA_DWC_REG_OFFSET;
1237         hsdev->dmadr = res->start + SATA_DWC_REG_OFFSET + offsetof(struct sata_dwc_regs, dmadr);
1238 
1239         /* Setup port */
1240         host->ports[0]->ioaddr.cmd_addr = base;
1241         host->ports[0]->ioaddr.scr_addr = base + SATA_DWC_SCR_OFFSET;
1242         sata_dwc_setup_port(&host->ports[0]->ioaddr, base);
1243 
1244         /* Read the ID and Version Registers */
1245         idr = sata_dwc_readl(&hsdev->sata_dwc_regs->idr);
1246         versionr = sata_dwc_readl(&hsdev->sata_dwc_regs->versionr);
1247         dev_notice(&ofdev->dev, "id %d, controller version %c.%c%c\n",
1248                    idr, ver[0], ver[1], ver[2]);
1249 
1250         /* Save dev for later use in dev_xxx() routines */
1251         hsdev->dev = &ofdev->dev;
1252 
1253         /* Enable SATA Interrupts */
1254         sata_dwc_enable_interrupts(hsdev);
1255 
1256         /* Get SATA interrupt number */
1257         irq = irq_of_parse_and_map(np, 0);
1258         if (irq == NO_IRQ) {
1259                 dev_err(&ofdev->dev, "no SATA DMA irq\n");
1260                 err = -ENODEV;
1261                 goto error_out;
1262         }
1263 
1264 #ifdef CONFIG_SATA_DWC_OLD_DMA
1265         if (!of_find_property(np, "dmas", NULL)) {
1266                 err = sata_dwc_dma_init_old(ofdev, hsdev);
1267                 if (err)
1268                         goto error_out;
1269         }
1270 #endif
1271 
1272         hsdev->phy = devm_phy_optional_get(hsdev->dev, "sata-phy");
1273         if (IS_ERR(hsdev->phy)) {
1274                 err = PTR_ERR(hsdev->phy);
1275                 hsdev->phy = NULL;
1276                 goto error_out;
1277         }
1278 
1279         err = phy_init(hsdev->phy);
1280         if (err)
1281                 goto error_out;
1282 
1283         /*
1284          * Now, register with libATA core, this will also initiate the
1285          * device discovery process, invoking our port_start() handler &
1286          * error_handler() to execute a dummy Softreset EH session
1287          */
1288         err = ata_host_activate(host, irq, sata_dwc_isr, 0, &sata_dwc_sht);
1289         if (err)
1290                 dev_err(&ofdev->dev, "failed to activate host");
1291 
1292         dev_set_drvdata(&ofdev->dev, host);
1293         return 0;
1294 
1295 error_out:
1296         phy_exit(hsdev->phy);
1297         return err;
1298 }
1299 
1300 static int sata_dwc_remove(struct platform_device *ofdev)
1301 {
1302         struct device *dev = &ofdev->dev;
1303         struct ata_host *host = dev_get_drvdata(dev);
1304         struct sata_dwc_device *hsdev = host->private_data;
1305 
1306         ata_host_detach(host);
1307 
1308         phy_exit(hsdev->phy);
1309 
1310 #ifdef CONFIG_SATA_DWC_OLD_DMA
1311         /* Free SATA DMA resources */
1312         sata_dwc_dma_exit_old(hsdev);
1313 #endif
1314 
1315         dev_dbg(&ofdev->dev, "done\n");
1316         return 0;
1317 }
1318 
1319 static const struct of_device_id sata_dwc_match[] = {
1320         { .compatible = "amcc,sata-460ex", },
1321         {}
1322 };
1323 MODULE_DEVICE_TABLE(of, sata_dwc_match);
1324 
1325 static struct platform_driver sata_dwc_driver = {
1326         .driver = {
1327                 .name = DRV_NAME,
1328                 .of_match_table = sata_dwc_match,
1329         },
1330         .probe = sata_dwc_probe,
1331         .remove = sata_dwc_remove,
1332 };
1333 
1334 module_platform_driver(sata_dwc_driver);
1335 
1336 MODULE_LICENSE("GPL");
1337 MODULE_AUTHOR("Mark Miesfeld <mmiesfeld@amcc.com>");
1338 MODULE_DESCRIPTION("DesignWare Cores SATA controller low level driver");
1339 MODULE_VERSION(DRV_VERSION);
1340 

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