Version:  2.0.40 2.2.26 2.4.37 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16

Linux/drivers/ata/pata_scc.c

  1 /*
  2  * Support for IDE interfaces on Celleb platform
  3  *
  4  * (C) Copyright 2006 TOSHIBA CORPORATION
  5  *
  6  * This code is based on drivers/ata/ata_piix.c:
  7  *  Copyright 2003-2005 Red Hat Inc
  8  *  Copyright 2003-2005 Jeff Garzik
  9  *  Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
 10  *  Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
 11  *  Copyright (C) 2003 Red Hat Inc
 12  *
 13  * and drivers/ata/ahci.c:
 14  *  Copyright 2004-2005 Red Hat, Inc.
 15  *
 16  * and drivers/ata/libata-core.c:
 17  *  Copyright 2003-2004 Red Hat, Inc.  All rights reserved.
 18  *  Copyright 2003-2004 Jeff Garzik
 19  *
 20  * This program is free software; you can redistribute it and/or modify
 21  * it under the terms of the GNU General Public License as published by
 22  * the Free Software Foundation; either version 2 of the License, or
 23  * (at your option) any later version.
 24  *
 25  * This program is distributed in the hope that it will be useful,
 26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
 27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 28  * GNU General Public License for more details.
 29  *
 30  * You should have received a copy of the GNU General Public License along
 31  * with this program; if not, write to the Free Software Foundation, Inc.,
 32  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
 33  */
 34 
 35 #include <linux/kernel.h>
 36 #include <linux/module.h>
 37 #include <linux/pci.h>
 38 #include <linux/blkdev.h>
 39 #include <linux/delay.h>
 40 #include <linux/device.h>
 41 #include <scsi/scsi_host.h>
 42 #include <linux/libata.h>
 43 
 44 #define DRV_NAME                "pata_scc"
 45 #define DRV_VERSION             "0.3"
 46 
 47 #define PCI_DEVICE_ID_TOSHIBA_SCC_ATA           0x01b4
 48 
 49 /* PCI BARs */
 50 #define SCC_CTRL_BAR            0
 51 #define SCC_BMID_BAR            1
 52 
 53 /* offset of CTRL registers */
 54 #define SCC_CTL_PIOSHT          0x000
 55 #define SCC_CTL_PIOCT           0x004
 56 #define SCC_CTL_MDMACT          0x008
 57 #define SCC_CTL_MCRCST          0x00C
 58 #define SCC_CTL_SDMACT          0x010
 59 #define SCC_CTL_SCRCST          0x014
 60 #define SCC_CTL_UDENVT          0x018
 61 #define SCC_CTL_TDVHSEL         0x020
 62 #define SCC_CTL_MODEREG         0x024
 63 #define SCC_CTL_ECMODE          0xF00
 64 #define SCC_CTL_MAEA0           0xF50
 65 #define SCC_CTL_MAEC0           0xF54
 66 #define SCC_CTL_CCKCTRL         0xFF0
 67 
 68 /* offset of BMID registers */
 69 #define SCC_DMA_CMD             0x000
 70 #define SCC_DMA_STATUS          0x004
 71 #define SCC_DMA_TABLE_OFS       0x008
 72 #define SCC_DMA_INTMASK         0x010
 73 #define SCC_DMA_INTST           0x014
 74 #define SCC_DMA_PTERADD         0x018
 75 #define SCC_REG_CMD_ADDR        0x020
 76 #define SCC_REG_DATA            0x000
 77 #define SCC_REG_ERR             0x004
 78 #define SCC_REG_FEATURE         0x004
 79 #define SCC_REG_NSECT           0x008
 80 #define SCC_REG_LBAL            0x00C
 81 #define SCC_REG_LBAM            0x010
 82 #define SCC_REG_LBAH            0x014
 83 #define SCC_REG_DEVICE          0x018
 84 #define SCC_REG_STATUS          0x01C
 85 #define SCC_REG_CMD             0x01C
 86 #define SCC_REG_ALTSTATUS       0x020
 87 
 88 /* register value */
 89 #define TDVHSEL_MASTER          0x00000001
 90 #define TDVHSEL_SLAVE           0x00000004
 91 
 92 #define MODE_JCUSFEN            0x00000080
 93 
 94 #define ECMODE_VALUE            0x01
 95 
 96 #define CCKCTRL_ATARESET        0x00040000
 97 #define CCKCTRL_BUFCNT          0x00020000
 98 #define CCKCTRL_CRST            0x00010000
 99 #define CCKCTRL_OCLKEN          0x00000100
100 #define CCKCTRL_ATACLKOEN       0x00000002
101 #define CCKCTRL_LCLKEN          0x00000001
102 
103 #define QCHCD_IOS_SS            0x00000001
104 
105 #define QCHSD_STPDIAG           0x00020000
106 
107 #define INTMASK_MSK             0xD1000012
108 #define INTSTS_SERROR           0x80000000
109 #define INTSTS_PRERR            0x40000000
110 #define INTSTS_RERR             0x10000000
111 #define INTSTS_ICERR            0x01000000
112 #define INTSTS_BMSINT           0x00000010
113 #define INTSTS_BMHE             0x00000008
114 #define INTSTS_IOIRQS           0x00000004
115 #define INTSTS_INTRQ            0x00000002
116 #define INTSTS_ACTEINT          0x00000001
117 
118 
119 /* PIO transfer mode table */
120 /* JCHST */
121 static const unsigned long JCHSTtbl[2][7] = {
122         {0x0E, 0x05, 0x02, 0x03, 0x02, 0x00, 0x00},     /* 100MHz */
123         {0x13, 0x07, 0x04, 0x04, 0x03, 0x00, 0x00}      /* 133MHz */
124 };
125 
126 /* JCHHT */
127 static const unsigned long JCHHTtbl[2][7] = {
128         {0x0E, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00},     /* 100MHz */
129         {0x13, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00}      /* 133MHz */
130 };
131 
132 /* JCHCT */
133 static const unsigned long JCHCTtbl[2][7] = {
134         {0x1D, 0x1D, 0x1C, 0x0B, 0x06, 0x00, 0x00},     /* 100MHz */
135         {0x27, 0x26, 0x26, 0x0E, 0x09, 0x00, 0x00}      /* 133MHz */
136 };
137 
138 /* DMA transfer mode  table */
139 /* JCHDCTM/JCHDCTS */
140 static const unsigned long JCHDCTxtbl[2][7] = {
141         {0x0A, 0x06, 0x04, 0x03, 0x01, 0x00, 0x00},     /* 100MHz */
142         {0x0E, 0x09, 0x06, 0x04, 0x02, 0x01, 0x00}      /* 133MHz */
143 };
144 
145 /* JCSTWTM/JCSTWTS  */
146 static const unsigned long JCSTWTxtbl[2][7] = {
147         {0x06, 0x04, 0x03, 0x02, 0x02, 0x02, 0x00},     /* 100MHz */
148         {0x09, 0x06, 0x04, 0x02, 0x02, 0x02, 0x02}      /* 133MHz */
149 };
150 
151 /* JCTSS */
152 static const unsigned long JCTSStbl[2][7] = {
153         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x00},     /* 100MHz */
154         {0x05, 0x05, 0x05, 0x05, 0x05, 0x05, 0x05}      /* 133MHz */
155 };
156 
157 /* JCENVT */
158 static const unsigned long JCENVTtbl[2][7] = {
159         {0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00},     /* 100MHz */
160         {0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02}      /* 133MHz */
161 };
162 
163 /* JCACTSELS/JCACTSELM */
164 static const unsigned long JCACTSELtbl[2][7] = {
165         {0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x00},     /* 100MHz */
166         {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01}      /* 133MHz */
167 };
168 
169 static const struct pci_device_id scc_pci_tbl[] = {
170         { PCI_VDEVICE(TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_SCC_ATA), 0},
171         { }     /* terminate list */
172 };
173 
174 /**
175  *      scc_set_piomode - Initialize host controller PATA PIO timings
176  *      @ap: Port whose timings we are configuring
177  *      @adev: um
178  *
179  *      Set PIO mode for device.
180  *
181  *      LOCKING:
182  *      None (inherited from caller).
183  */
184 
185 static void scc_set_piomode (struct ata_port *ap, struct ata_device *adev)
186 {
187         unsigned int pio = adev->pio_mode - XFER_PIO_0;
188         void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
189         void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
190         void __iomem *piosht_port = ctrl_base + SCC_CTL_PIOSHT;
191         void __iomem *pioct_port = ctrl_base + SCC_CTL_PIOCT;
192         unsigned long reg;
193         int offset;
194 
195         reg = in_be32(cckctrl_port);
196         if (reg & CCKCTRL_ATACLKOEN)
197                 offset = 1;     /* 133MHz */
198         else
199                 offset = 0;     /* 100MHz */
200 
201         reg = JCHSTtbl[offset][pio] << 16 | JCHHTtbl[offset][pio];
202         out_be32(piosht_port, reg);
203         reg = JCHCTtbl[offset][pio];
204         out_be32(pioct_port, reg);
205 }
206 
207 /**
208  *      scc_set_dmamode - Initialize host controller PATA DMA timings
209  *      @ap: Port whose timings we are configuring
210  *      @adev: um
211  *
212  *      Set UDMA mode for device.
213  *
214  *      LOCKING:
215  *      None (inherited from caller).
216  */
217 
218 static void scc_set_dmamode (struct ata_port *ap, struct ata_device *adev)
219 {
220         unsigned int udma = adev->dma_mode;
221         unsigned int is_slave = (adev->devno != 0);
222         u8 speed = udma;
223         void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
224         void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
225         void __iomem *mdmact_port = ctrl_base + SCC_CTL_MDMACT;
226         void __iomem *mcrcst_port = ctrl_base + SCC_CTL_MCRCST;
227         void __iomem *sdmact_port = ctrl_base + SCC_CTL_SDMACT;
228         void __iomem *scrcst_port = ctrl_base + SCC_CTL_SCRCST;
229         void __iomem *udenvt_port = ctrl_base + SCC_CTL_UDENVT;
230         void __iomem *tdvhsel_port = ctrl_base + SCC_CTL_TDVHSEL;
231         int offset, idx;
232 
233         if (in_be32(cckctrl_port) & CCKCTRL_ATACLKOEN)
234                 offset = 1;     /* 133MHz */
235         else
236                 offset = 0;     /* 100MHz */
237 
238         if (speed >= XFER_UDMA_0)
239                 idx = speed - XFER_UDMA_0;
240         else
241                 return;
242 
243         if (is_slave) {
244                 out_be32(sdmact_port, JCHDCTxtbl[offset][idx]);
245                 out_be32(scrcst_port, JCSTWTxtbl[offset][idx]);
246                 out_be32(tdvhsel_port,
247                          (in_be32(tdvhsel_port) & ~TDVHSEL_SLAVE) | (JCACTSELtbl[offset][idx] << 2));
248         } else {
249                 out_be32(mdmact_port, JCHDCTxtbl[offset][idx]);
250                 out_be32(mcrcst_port, JCSTWTxtbl[offset][idx]);
251                 out_be32(tdvhsel_port,
252                          (in_be32(tdvhsel_port) & ~TDVHSEL_MASTER) | JCACTSELtbl[offset][idx]);
253         }
254         out_be32(udenvt_port,
255                  JCTSStbl[offset][idx] << 16 | JCENVTtbl[offset][idx]);
256 }
257 
258 unsigned long scc_mode_filter(struct ata_device *adev, unsigned long mask)
259 {
260         /* errata A308 workaround: limit ATAPI UDMA mode to UDMA4 */
261         if (adev->class == ATA_DEV_ATAPI &&
262             (mask & (0xE0 << ATA_SHIFT_UDMA))) {
263                 printk(KERN_INFO "%s: limit ATAPI UDMA to UDMA4\n", DRV_NAME);
264                 mask &= ~(0xE0 << ATA_SHIFT_UDMA);
265         }
266         return mask;
267 }
268 
269 /**
270  *      scc_tf_load - send taskfile registers to host controller
271  *      @ap: Port to which output is sent
272  *      @tf: ATA taskfile register set
273  *
274  *      Note: Original code is ata_sff_tf_load().
275  */
276 
277 static void scc_tf_load (struct ata_port *ap, const struct ata_taskfile *tf)
278 {
279         struct ata_ioports *ioaddr = &ap->ioaddr;
280         unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
281 
282         if (tf->ctl != ap->last_ctl) {
283                 out_be32(ioaddr->ctl_addr, tf->ctl);
284                 ap->last_ctl = tf->ctl;
285                 ata_wait_idle(ap);
286         }
287 
288         if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
289                 out_be32(ioaddr->feature_addr, tf->hob_feature);
290                 out_be32(ioaddr->nsect_addr, tf->hob_nsect);
291                 out_be32(ioaddr->lbal_addr, tf->hob_lbal);
292                 out_be32(ioaddr->lbam_addr, tf->hob_lbam);
293                 out_be32(ioaddr->lbah_addr, tf->hob_lbah);
294                 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
295                         tf->hob_feature,
296                         tf->hob_nsect,
297                         tf->hob_lbal,
298                         tf->hob_lbam,
299                         tf->hob_lbah);
300         }
301 
302         if (is_addr) {
303                 out_be32(ioaddr->feature_addr, tf->feature);
304                 out_be32(ioaddr->nsect_addr, tf->nsect);
305                 out_be32(ioaddr->lbal_addr, tf->lbal);
306                 out_be32(ioaddr->lbam_addr, tf->lbam);
307                 out_be32(ioaddr->lbah_addr, tf->lbah);
308                 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
309                         tf->feature,
310                         tf->nsect,
311                         tf->lbal,
312                         tf->lbam,
313                         tf->lbah);
314         }
315 
316         if (tf->flags & ATA_TFLAG_DEVICE) {
317                 out_be32(ioaddr->device_addr, tf->device);
318                 VPRINTK("device 0x%X\n", tf->device);
319         }
320 
321         ata_wait_idle(ap);
322 }
323 
324 /**
325  *      scc_check_status - Read device status reg & clear interrupt
326  *      @ap: port where the device is
327  *
328  *      Note: Original code is ata_check_status().
329  */
330 
331 static u8 scc_check_status (struct ata_port *ap)
332 {
333         return in_be32(ap->ioaddr.status_addr);
334 }
335 
336 /**
337  *      scc_tf_read - input device's ATA taskfile shadow registers
338  *      @ap: Port from which input is read
339  *      @tf: ATA taskfile register set for storing input
340  *
341  *      Note: Original code is ata_sff_tf_read().
342  */
343 
344 static void scc_tf_read (struct ata_port *ap, struct ata_taskfile *tf)
345 {
346         struct ata_ioports *ioaddr = &ap->ioaddr;
347 
348         tf->command = scc_check_status(ap);
349         tf->feature = in_be32(ioaddr->error_addr);
350         tf->nsect = in_be32(ioaddr->nsect_addr);
351         tf->lbal = in_be32(ioaddr->lbal_addr);
352         tf->lbam = in_be32(ioaddr->lbam_addr);
353         tf->lbah = in_be32(ioaddr->lbah_addr);
354         tf->device = in_be32(ioaddr->device_addr);
355 
356         if (tf->flags & ATA_TFLAG_LBA48) {
357                 out_be32(ioaddr->ctl_addr, tf->ctl | ATA_HOB);
358                 tf->hob_feature = in_be32(ioaddr->error_addr);
359                 tf->hob_nsect = in_be32(ioaddr->nsect_addr);
360                 tf->hob_lbal = in_be32(ioaddr->lbal_addr);
361                 tf->hob_lbam = in_be32(ioaddr->lbam_addr);
362                 tf->hob_lbah = in_be32(ioaddr->lbah_addr);
363                 out_be32(ioaddr->ctl_addr, tf->ctl);
364                 ap->last_ctl = tf->ctl;
365         }
366 }
367 
368 /**
369  *      scc_exec_command - issue ATA command to host controller
370  *      @ap: port to which command is being issued
371  *      @tf: ATA taskfile register set
372  *
373  *      Note: Original code is ata_sff_exec_command().
374  */
375 
376 static void scc_exec_command (struct ata_port *ap,
377                               const struct ata_taskfile *tf)
378 {
379         DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
380 
381         out_be32(ap->ioaddr.command_addr, tf->command);
382         ata_sff_pause(ap);
383 }
384 
385 /**
386  *      scc_check_altstatus - Read device alternate status reg
387  *      @ap: port where the device is
388  */
389 
390 static u8 scc_check_altstatus (struct ata_port *ap)
391 {
392         return in_be32(ap->ioaddr.altstatus_addr);
393 }
394 
395 /**
396  *      scc_dev_select - Select device 0/1 on ATA bus
397  *      @ap: ATA channel to manipulate
398  *      @device: ATA device (numbered from zero) to select
399  *
400  *      Note: Original code is ata_sff_dev_select().
401  */
402 
403 static void scc_dev_select (struct ata_port *ap, unsigned int device)
404 {
405         u8 tmp;
406 
407         if (device == 0)
408                 tmp = ATA_DEVICE_OBS;
409         else
410                 tmp = ATA_DEVICE_OBS | ATA_DEV1;
411 
412         out_be32(ap->ioaddr.device_addr, tmp);
413         ata_sff_pause(ap);
414 }
415 
416 /**
417  *      scc_set_devctl - Write device control reg
418  *      @ap: port where the device is
419  *      @ctl: value to write
420  */
421 
422 static void scc_set_devctl(struct ata_port *ap, u8 ctl)
423 {
424         out_be32(ap->ioaddr.ctl_addr, ctl);
425 }
426 
427 /**
428  *      scc_bmdma_setup - Set up PCI IDE BMDMA transaction
429  *      @qc: Info associated with this ATA transaction.
430  *
431  *      Note: Original code is ata_bmdma_setup().
432  */
433 
434 static void scc_bmdma_setup (struct ata_queued_cmd *qc)
435 {
436         struct ata_port *ap = qc->ap;
437         unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
438         u8 dmactl;
439         void __iomem *mmio = ap->ioaddr.bmdma_addr;
440 
441         /* load PRD table addr */
442         out_be32(mmio + SCC_DMA_TABLE_OFS, ap->bmdma_prd_dma);
443 
444         /* specify data direction, triple-check start bit is clear */
445         dmactl = in_be32(mmio + SCC_DMA_CMD);
446         dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
447         if (!rw)
448                 dmactl |= ATA_DMA_WR;
449         out_be32(mmio + SCC_DMA_CMD, dmactl);
450 
451         /* issue r/w command */
452         ap->ops->sff_exec_command(ap, &qc->tf);
453 }
454 
455 /**
456  *      scc_bmdma_start - Start a PCI IDE BMDMA transaction
457  *      @qc: Info associated with this ATA transaction.
458  *
459  *      Note: Original code is ata_bmdma_start().
460  */
461 
462 static void scc_bmdma_start (struct ata_queued_cmd *qc)
463 {
464         struct ata_port *ap = qc->ap;
465         u8 dmactl;
466         void __iomem *mmio = ap->ioaddr.bmdma_addr;
467 
468         /* start host DMA transaction */
469         dmactl = in_be32(mmio + SCC_DMA_CMD);
470         out_be32(mmio + SCC_DMA_CMD, dmactl | ATA_DMA_START);
471 }
472 
473 /**
474  *      scc_devchk - PATA device presence detection
475  *      @ap: ATA channel to examine
476  *      @device: Device to examine (starting at zero)
477  *
478  *      Note: Original code is ata_devchk().
479  */
480 
481 static unsigned int scc_devchk (struct ata_port *ap,
482                                 unsigned int device)
483 {
484         struct ata_ioports *ioaddr = &ap->ioaddr;
485         u8 nsect, lbal;
486 
487         ap->ops->sff_dev_select(ap, device);
488 
489         out_be32(ioaddr->nsect_addr, 0x55);
490         out_be32(ioaddr->lbal_addr, 0xaa);
491 
492         out_be32(ioaddr->nsect_addr, 0xaa);
493         out_be32(ioaddr->lbal_addr, 0x55);
494 
495         out_be32(ioaddr->nsect_addr, 0x55);
496         out_be32(ioaddr->lbal_addr, 0xaa);
497 
498         nsect = in_be32(ioaddr->nsect_addr);
499         lbal = in_be32(ioaddr->lbal_addr);
500 
501         if ((nsect == 0x55) && (lbal == 0xaa))
502                 return 1;       /* we found a device */
503 
504         return 0;               /* nothing found */
505 }
506 
507 /**
508  *      scc_wait_after_reset - wait for devices to become ready after reset
509  *
510  *      Note: Original code is ata_sff_wait_after_reset
511  */
512 
513 static int scc_wait_after_reset(struct ata_link *link, unsigned int devmask,
514                                 unsigned long deadline)
515 {
516         struct ata_port *ap = link->ap;
517         struct ata_ioports *ioaddr = &ap->ioaddr;
518         unsigned int dev0 = devmask & (1 << 0);
519         unsigned int dev1 = devmask & (1 << 1);
520         int rc, ret = 0;
521 
522         /* Spec mandates ">= 2ms" before checking status.  We wait
523          * 150ms, because that was the magic delay used for ATAPI
524          * devices in Hale Landis's ATADRVR, for the period of time
525          * between when the ATA command register is written, and then
526          * status is checked.  Because waiting for "a while" before
527          * checking status is fine, post SRST, we perform this magic
528          * delay here as well.
529          *
530          * Old drivers/ide uses the 2mS rule and then waits for ready.
531          */
532         ata_msleep(ap, 150);
533 
534         /* always check readiness of the master device */
535         rc = ata_sff_wait_ready(link, deadline);
536         /* -ENODEV means the odd clown forgot the D7 pulldown resistor
537          * and TF status is 0xff, bail out on it too.
538          */
539         if (rc)
540                 return rc;
541 
542         /* if device 1 was found in ata_devchk, wait for register
543          * access briefly, then wait for BSY to clear.
544          */
545         if (dev1) {
546                 int i;
547 
548                 ap->ops->sff_dev_select(ap, 1);
549 
550                 /* Wait for register access.  Some ATAPI devices fail
551                  * to set nsect/lbal after reset, so don't waste too
552                  * much time on it.  We're gonna wait for !BSY anyway.
553                  */
554                 for (i = 0; i < 2; i++) {
555                         u8 nsect, lbal;
556 
557                         nsect = in_be32(ioaddr->nsect_addr);
558                         lbal = in_be32(ioaddr->lbal_addr);
559                         if ((nsect == 1) && (lbal == 1))
560                                 break;
561                         ata_msleep(ap, 50);     /* give drive a breather */
562                 }
563 
564                 rc = ata_sff_wait_ready(link, deadline);
565                 if (rc) {
566                         if (rc != -ENODEV)
567                                 return rc;
568                         ret = rc;
569                 }
570         }
571 
572         /* is all this really necessary? */
573         ap->ops->sff_dev_select(ap, 0);
574         if (dev1)
575                 ap->ops->sff_dev_select(ap, 1);
576         if (dev0)
577                 ap->ops->sff_dev_select(ap, 0);
578 
579         return ret;
580 }
581 
582 /**
583  *      scc_bus_softreset - PATA device software reset
584  *
585  *      Note: Original code is ata_bus_softreset().
586  */
587 
588 static unsigned int scc_bus_softreset(struct ata_port *ap, unsigned int devmask,
589                                       unsigned long deadline)
590 {
591         struct ata_ioports *ioaddr = &ap->ioaddr;
592 
593         DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
594 
595         /* software reset.  causes dev0 to be selected */
596         out_be32(ioaddr->ctl_addr, ap->ctl);
597         udelay(20);
598         out_be32(ioaddr->ctl_addr, ap->ctl | ATA_SRST);
599         udelay(20);
600         out_be32(ioaddr->ctl_addr, ap->ctl);
601 
602         scc_wait_after_reset(&ap->link, devmask, deadline);
603 
604         return 0;
605 }
606 
607 /**
608  *      scc_softreset - reset host port via ATA SRST
609  *      @ap: port to reset
610  *      @classes: resulting classes of attached devices
611  *      @deadline: deadline jiffies for the operation
612  *
613  *      Note: Original code is ata_sff_softreset().
614  */
615 
616 static int scc_softreset(struct ata_link *link, unsigned int *classes,
617                          unsigned long deadline)
618 {
619         struct ata_port *ap = link->ap;
620         unsigned int slave_possible = ap->flags & ATA_FLAG_SLAVE_POSS;
621         unsigned int devmask = 0, err_mask;
622         u8 err;
623 
624         DPRINTK("ENTER\n");
625 
626         /* determine if device 0/1 are present */
627         if (scc_devchk(ap, 0))
628                 devmask |= (1 << 0);
629         if (slave_possible && scc_devchk(ap, 1))
630                 devmask |= (1 << 1);
631 
632         /* select device 0 again */
633         ap->ops->sff_dev_select(ap, 0);
634 
635         /* issue bus reset */
636         DPRINTK("about to softreset, devmask=%x\n", devmask);
637         err_mask = scc_bus_softreset(ap, devmask, deadline);
638         if (err_mask) {
639                 ata_port_err(ap, "SRST failed (err_mask=0x%x)\n", err_mask);
640                 return -EIO;
641         }
642 
643         /* determine by signature whether we have ATA or ATAPI devices */
644         classes[0] = ata_sff_dev_classify(&ap->link.device[0],
645                                           devmask & (1 << 0), &err);
646         if (slave_possible && err != 0x81)
647                 classes[1] = ata_sff_dev_classify(&ap->link.device[1],
648                                                   devmask & (1 << 1), &err);
649 
650         DPRINTK("EXIT, classes[0]=%u [1]=%u\n", classes[0], classes[1]);
651         return 0;
652 }
653 
654 /**
655  *      scc_bmdma_stop - Stop PCI IDE BMDMA transfer
656  *      @qc: Command we are ending DMA for
657  */
658 
659 static void scc_bmdma_stop (struct ata_queued_cmd *qc)
660 {
661         struct ata_port *ap = qc->ap;
662         void __iomem *ctrl_base = ap->host->iomap[SCC_CTRL_BAR];
663         void __iomem *bmid_base = ap->host->iomap[SCC_BMID_BAR];
664         u32 reg;
665 
666         while (1) {
667                 reg = in_be32(bmid_base + SCC_DMA_INTST);
668 
669                 if (reg & INTSTS_SERROR) {
670                         printk(KERN_WARNING "%s: SERROR\n", DRV_NAME);
671                         out_be32(bmid_base + SCC_DMA_INTST, INTSTS_SERROR|INTSTS_BMSINT);
672                         out_be32(bmid_base + SCC_DMA_CMD,
673                                  in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
674                         continue;
675                 }
676 
677                 if (reg & INTSTS_PRERR) {
678                         u32 maea0, maec0;
679                         maea0 = in_be32(ctrl_base + SCC_CTL_MAEA0);
680                         maec0 = in_be32(ctrl_base + SCC_CTL_MAEC0);
681                         printk(KERN_WARNING "%s: PRERR [addr:%x cmd:%x]\n", DRV_NAME, maea0, maec0);
682                         out_be32(bmid_base + SCC_DMA_INTST, INTSTS_PRERR|INTSTS_BMSINT);
683                         out_be32(bmid_base + SCC_DMA_CMD,
684                                  in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
685                         continue;
686                 }
687 
688                 if (reg & INTSTS_RERR) {
689                         printk(KERN_WARNING "%s: Response Error\n", DRV_NAME);
690                         out_be32(bmid_base + SCC_DMA_INTST, INTSTS_RERR|INTSTS_BMSINT);
691                         out_be32(bmid_base + SCC_DMA_CMD,
692                                  in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
693                         continue;
694                 }
695 
696                 if (reg & INTSTS_ICERR) {
697                         out_be32(bmid_base + SCC_DMA_CMD,
698                                  in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
699                         printk(KERN_WARNING "%s: Illegal Configuration\n", DRV_NAME);
700                         out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ICERR|INTSTS_BMSINT);
701                         continue;
702                 }
703 
704                 if (reg & INTSTS_BMSINT) {
705                         unsigned int classes;
706                         unsigned long deadline = ata_deadline(jiffies, ATA_TMOUT_BOOT);
707                         printk(KERN_WARNING "%s: Internal Bus Error\n", DRV_NAME);
708                         out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMSINT);
709                         /* TBD: SW reset */
710                         scc_softreset(&ap->link, &classes, deadline);
711                         continue;
712                 }
713 
714                 if (reg & INTSTS_BMHE) {
715                         out_be32(bmid_base + SCC_DMA_INTST, INTSTS_BMHE);
716                         continue;
717                 }
718 
719                 if (reg & INTSTS_ACTEINT) {
720                         out_be32(bmid_base + SCC_DMA_INTST, INTSTS_ACTEINT);
721                         continue;
722                 }
723 
724                 if (reg & INTSTS_IOIRQS) {
725                         out_be32(bmid_base + SCC_DMA_INTST, INTSTS_IOIRQS);
726                         continue;
727                 }
728                 break;
729         }
730 
731         /* clear start/stop bit */
732         out_be32(bmid_base + SCC_DMA_CMD,
733                  in_be32(bmid_base + SCC_DMA_CMD) & ~ATA_DMA_START);
734 
735         /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
736         ata_sff_dma_pause(ap);  /* dummy read */
737 }
738 
739 /**
740  *      scc_bmdma_status - Read PCI IDE BMDMA status
741  *      @ap: Port associated with this ATA transaction.
742  */
743 
744 static u8 scc_bmdma_status (struct ata_port *ap)
745 {
746         void __iomem *mmio = ap->ioaddr.bmdma_addr;
747         u8 host_stat = in_be32(mmio + SCC_DMA_STATUS);
748         u32 int_status = in_be32(mmio + SCC_DMA_INTST);
749         struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
750         static int retry = 0;
751 
752         /* return if IOS_SS is cleared */
753         if (!(in_be32(mmio + SCC_DMA_CMD) & ATA_DMA_START))
754                 return host_stat;
755 
756         /* errata A252,A308 workaround: Step4 */
757         if ((scc_check_altstatus(ap) & ATA_ERR)
758                                         && (int_status & INTSTS_INTRQ))
759                 return (host_stat | ATA_DMA_INTR);
760 
761         /* errata A308 workaround Step5 */
762         if (int_status & INTSTS_IOIRQS) {
763                 host_stat |= ATA_DMA_INTR;
764 
765                 /* We don't check ATAPI DMA because it is limited to UDMA4 */
766                 if ((qc->tf.protocol == ATA_PROT_DMA &&
767                      qc->dev->xfer_mode > XFER_UDMA_4)) {
768                         if (!(int_status & INTSTS_ACTEINT)) {
769                                 printk(KERN_WARNING "ata%u: operation failed (transfer data loss)\n",
770                                        ap->print_id);
771                                 host_stat |= ATA_DMA_ERR;
772                                 if (retry++)
773                                         ap->udma_mask &= ~(1 << qc->dev->xfer_mode);
774                         } else
775                                 retry = 0;
776                 }
777         }
778 
779         return host_stat;
780 }
781 
782 /**
783  *      scc_data_xfer - Transfer data by PIO
784  *      @dev: device for this I/O
785  *      @buf: data buffer
786  *      @buflen: buffer length
787  *      @rw: read/write
788  *
789  *      Note: Original code is ata_sff_data_xfer().
790  */
791 
792 static unsigned int scc_data_xfer (struct ata_device *dev, unsigned char *buf,
793                                    unsigned int buflen, int rw)
794 {
795         struct ata_port *ap = dev->link->ap;
796         unsigned int words = buflen >> 1;
797         unsigned int i;
798         __le16 *buf16 = (__le16 *) buf;
799         void __iomem *mmio = ap->ioaddr.data_addr;
800 
801         /* Transfer multiple of 2 bytes */
802         if (rw == READ)
803                 for (i = 0; i < words; i++)
804                         buf16[i] = cpu_to_le16(in_be32(mmio));
805         else
806                 for (i = 0; i < words; i++)
807                         out_be32(mmio, le16_to_cpu(buf16[i]));
808 
809         /* Transfer trailing 1 byte, if any. */
810         if (unlikely(buflen & 0x01)) {
811                 __le16 align_buf[1] = { 0 };
812                 unsigned char *trailing_buf = buf + buflen - 1;
813 
814                 if (rw == READ) {
815                         align_buf[0] = cpu_to_le16(in_be32(mmio));
816                         memcpy(trailing_buf, align_buf, 1);
817                 } else {
818                         memcpy(align_buf, trailing_buf, 1);
819                         out_be32(mmio, le16_to_cpu(align_buf[0]));
820                 }
821                 words++;
822         }
823 
824         return words << 1;
825 }
826 
827 /**
828  *      scc_postreset - standard postreset callback
829  *      @ap: the target ata_port
830  *      @classes: classes of attached devices
831  *
832  *      Note: Original code is ata_sff_postreset().
833  */
834 
835 static void scc_postreset(struct ata_link *link, unsigned int *classes)
836 {
837         struct ata_port *ap = link->ap;
838 
839         DPRINTK("ENTER\n");
840 
841         /* is double-select really necessary? */
842         if (classes[0] != ATA_DEV_NONE)
843                 ap->ops->sff_dev_select(ap, 1);
844         if (classes[1] != ATA_DEV_NONE)
845                 ap->ops->sff_dev_select(ap, 0);
846 
847         /* bail out if no device is present */
848         if (classes[0] == ATA_DEV_NONE && classes[1] == ATA_DEV_NONE) {
849                 DPRINTK("EXIT, no device\n");
850                 return;
851         }
852 
853         /* set up device control */
854         out_be32(ap->ioaddr.ctl_addr, ap->ctl);
855 
856         DPRINTK("EXIT\n");
857 }
858 
859 /**
860  *      scc_irq_clear - Clear PCI IDE BMDMA interrupt.
861  *      @ap: Port associated with this ATA transaction.
862  *
863  *      Note: Original code is ata_bmdma_irq_clear().
864  */
865 
866 static void scc_irq_clear (struct ata_port *ap)
867 {
868         void __iomem *mmio = ap->ioaddr.bmdma_addr;
869 
870         if (!mmio)
871                 return;
872 
873         out_be32(mmio + SCC_DMA_STATUS, in_be32(mmio + SCC_DMA_STATUS));
874 }
875 
876 /**
877  *      scc_port_start - Set port up for dma.
878  *      @ap: Port to initialize
879  *
880  *      Allocate space for PRD table using ata_bmdma_port_start().
881  *      Set PRD table address for PTERADD. (PRD Transfer End Read)
882  */
883 
884 static int scc_port_start (struct ata_port *ap)
885 {
886         void __iomem *mmio = ap->ioaddr.bmdma_addr;
887         int rc;
888 
889         rc = ata_bmdma_port_start(ap);
890         if (rc)
891                 return rc;
892 
893         out_be32(mmio + SCC_DMA_PTERADD, ap->bmdma_prd_dma);
894         return 0;
895 }
896 
897 /**
898  *      scc_port_stop - Undo scc_port_start()
899  *      @ap: Port to shut down
900  *
901  *      Reset PTERADD.
902  */
903 
904 static void scc_port_stop (struct ata_port *ap)
905 {
906         void __iomem *mmio = ap->ioaddr.bmdma_addr;
907 
908         out_be32(mmio + SCC_DMA_PTERADD, 0);
909 }
910 
911 static struct scsi_host_template scc_sht = {
912         ATA_BMDMA_SHT(DRV_NAME),
913 };
914 
915 static struct ata_port_operations scc_pata_ops = {
916         .inherits               = &ata_bmdma_port_ops,
917 
918         .set_piomode            = scc_set_piomode,
919         .set_dmamode            = scc_set_dmamode,
920         .mode_filter            = scc_mode_filter,
921 
922         .sff_tf_load            = scc_tf_load,
923         .sff_tf_read            = scc_tf_read,
924         .sff_exec_command       = scc_exec_command,
925         .sff_check_status       = scc_check_status,
926         .sff_check_altstatus    = scc_check_altstatus,
927         .sff_dev_select         = scc_dev_select,
928         .sff_set_devctl         = scc_set_devctl,
929 
930         .bmdma_setup            = scc_bmdma_setup,
931         .bmdma_start            = scc_bmdma_start,
932         .bmdma_stop             = scc_bmdma_stop,
933         .bmdma_status           = scc_bmdma_status,
934         .sff_data_xfer          = scc_data_xfer,
935 
936         .cable_detect           = ata_cable_80wire,
937         .softreset              = scc_softreset,
938         .postreset              = scc_postreset,
939 
940         .sff_irq_clear          = scc_irq_clear,
941 
942         .port_start             = scc_port_start,
943         .port_stop              = scc_port_stop,
944 };
945 
946 static struct ata_port_info scc_port_info[] = {
947         {
948                 .flags          = ATA_FLAG_SLAVE_POSS,
949                 .pio_mask       = ATA_PIO4,
950                 /* No MWDMA */
951                 .udma_mask      = ATA_UDMA6,
952                 .port_ops       = &scc_pata_ops,
953         },
954 };
955 
956 /**
957  *      scc_reset_controller - initialize SCC PATA controller.
958  */
959 
960 static int scc_reset_controller(struct ata_host *host)
961 {
962         void __iomem *ctrl_base = host->iomap[SCC_CTRL_BAR];
963         void __iomem *bmid_base = host->iomap[SCC_BMID_BAR];
964         void __iomem *cckctrl_port = ctrl_base + SCC_CTL_CCKCTRL;
965         void __iomem *mode_port = ctrl_base + SCC_CTL_MODEREG;
966         void __iomem *ecmode_port = ctrl_base + SCC_CTL_ECMODE;
967         void __iomem *intmask_port = bmid_base + SCC_DMA_INTMASK;
968         void __iomem *dmastatus_port = bmid_base + SCC_DMA_STATUS;
969         u32 reg = 0;
970 
971         out_be32(cckctrl_port, reg);
972         reg |= CCKCTRL_ATACLKOEN;
973         out_be32(cckctrl_port, reg);
974         reg |= CCKCTRL_LCLKEN | CCKCTRL_OCLKEN;
975         out_be32(cckctrl_port, reg);
976         reg |= CCKCTRL_CRST;
977         out_be32(cckctrl_port, reg);
978 
979         for (;;) {
980                 reg = in_be32(cckctrl_port);
981                 if (reg & CCKCTRL_CRST)
982                         break;
983                 udelay(5000);
984         }
985 
986         reg |= CCKCTRL_ATARESET;
987         out_be32(cckctrl_port, reg);
988         out_be32(ecmode_port, ECMODE_VALUE);
989         out_be32(mode_port, MODE_JCUSFEN);
990         out_be32(intmask_port, INTMASK_MSK);
991 
992         if (in_be32(dmastatus_port) & QCHSD_STPDIAG) {
993                 printk(KERN_WARNING "%s: failed to detect 80c cable. (PDIAG# is high)\n", DRV_NAME);
994                 return -EIO;
995         }
996 
997         return 0;
998 }
999 
1000 /**
1001  *      scc_setup_ports - initialize ioaddr with SCC PATA port offsets.
1002  *      @ioaddr: IO address structure to be initialized
1003  *      @base: base address of BMID region
1004  */
1005 
1006 static void scc_setup_ports (struct ata_ioports *ioaddr, void __iomem *base)
1007 {
1008         ioaddr->cmd_addr = base + SCC_REG_CMD_ADDR;
1009         ioaddr->altstatus_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1010         ioaddr->ctl_addr = ioaddr->cmd_addr + SCC_REG_ALTSTATUS;
1011         ioaddr->bmdma_addr = base;
1012         ioaddr->data_addr = ioaddr->cmd_addr + SCC_REG_DATA;
1013         ioaddr->error_addr = ioaddr->cmd_addr + SCC_REG_ERR;
1014         ioaddr->feature_addr = ioaddr->cmd_addr + SCC_REG_FEATURE;
1015         ioaddr->nsect_addr = ioaddr->cmd_addr + SCC_REG_NSECT;
1016         ioaddr->lbal_addr = ioaddr->cmd_addr + SCC_REG_LBAL;
1017         ioaddr->lbam_addr = ioaddr->cmd_addr + SCC_REG_LBAM;
1018         ioaddr->lbah_addr = ioaddr->cmd_addr + SCC_REG_LBAH;
1019         ioaddr->device_addr = ioaddr->cmd_addr + SCC_REG_DEVICE;
1020         ioaddr->status_addr = ioaddr->cmd_addr + SCC_REG_STATUS;
1021         ioaddr->command_addr = ioaddr->cmd_addr + SCC_REG_CMD;
1022 }
1023 
1024 static int scc_host_init(struct ata_host *host)
1025 {
1026         struct pci_dev *pdev = to_pci_dev(host->dev);
1027         int rc;
1028 
1029         rc = scc_reset_controller(host);
1030         if (rc)
1031                 return rc;
1032 
1033         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1034         if (rc)
1035                 return rc;
1036         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1037         if (rc)
1038                 return rc;
1039 
1040         scc_setup_ports(&host->ports[0]->ioaddr, host->iomap[SCC_BMID_BAR]);
1041 
1042         pci_set_master(pdev);
1043 
1044         return 0;
1045 }
1046 
1047 /**
1048  *      scc_init_one - Register SCC PATA device with kernel services
1049  *      @pdev: PCI device to register
1050  *      @ent: Entry in scc_pci_tbl matching with @pdev
1051  *
1052  *      LOCKING:
1053  *      Inherited from PCI layer (may sleep).
1054  *
1055  *      RETURNS:
1056  *      Zero on success, or -ERRNO value.
1057  */
1058 
1059 static int scc_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1060 {
1061         unsigned int board_idx = (unsigned int) ent->driver_data;
1062         const struct ata_port_info *ppi[] = { &scc_port_info[board_idx], NULL };
1063         struct ata_host *host;
1064         int rc;
1065 
1066         ata_print_version_once(&pdev->dev, DRV_VERSION);
1067 
1068         host = ata_host_alloc_pinfo(&pdev->dev, ppi, 1);
1069         if (!host)
1070                 return -ENOMEM;
1071 
1072         rc = pcim_enable_device(pdev);
1073         if (rc)
1074                 return rc;
1075 
1076         rc = pcim_iomap_regions(pdev, (1 << SCC_CTRL_BAR) | (1 << SCC_BMID_BAR), DRV_NAME);
1077         if (rc == -EBUSY)
1078                 pcim_pin_device(pdev);
1079         if (rc)
1080                 return rc;
1081         host->iomap = pcim_iomap_table(pdev);
1082 
1083         ata_port_pbar_desc(host->ports[0], SCC_CTRL_BAR, -1, "ctrl");
1084         ata_port_pbar_desc(host->ports[0], SCC_BMID_BAR, -1, "bmid");
1085 
1086         rc = scc_host_init(host);
1087         if (rc)
1088                 return rc;
1089 
1090         return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
1091                                  IRQF_SHARED, &scc_sht);
1092 }
1093 
1094 static struct pci_driver scc_pci_driver = {
1095         .name                   = DRV_NAME,
1096         .id_table               = scc_pci_tbl,
1097         .probe                  = scc_init_one,
1098         .remove                 = ata_pci_remove_one,
1099 #ifdef CONFIG_PM_SLEEP
1100         .suspend                = ata_pci_device_suspend,
1101         .resume                 = ata_pci_device_resume,
1102 #endif
1103 };
1104 
1105 module_pci_driver(scc_pci_driver);
1106 
1107 MODULE_AUTHOR("Toshiba corp");
1108 MODULE_DESCRIPTION("SCSI low-level driver for Toshiba SCC PATA controller");
1109 MODULE_LICENSE("GPL");
1110 MODULE_DEVICE_TABLE(pci, scc_pci_tbl);
1111 MODULE_VERSION(DRV_VERSION);
1112 

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