Version:  2.6.34 2.6.35 2.6.36 2.6.37 2.6.38 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14

Linux/drivers/ata/pata_pdc2027x.c

  1 /*
  2  *  Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
  3  *
  4  *  This program is free software; you can redistribute it and/or
  5  *  modify it under the terms of the GNU General Public License
  6  *  as published by the Free Software Foundation; either version
  7  *  2 of the License, or (at your option) any later version.
  8  *
  9  *  Ported to libata by:
 10  *  Albert Lee <albertcc@tw.ibm.com> IBM Corporation
 11  *
 12  *  Copyright (C) 1998-2002             Andre Hedrick <andre@linux-ide.org>
 13  *  Portions Copyright (C) 1999 Promise Technology, Inc.
 14  *
 15  *  Author: Frank Tiernan (frankt@promise.com)
 16  *  Released under terms of General Public License
 17  *
 18  *
 19  *  libata documentation is available via 'make {ps|pdf}docs',
 20  *  as Documentation/DocBook/libata.*
 21  *
 22  *  Hardware information only available under NDA.
 23  *
 24  */
 25 #include <linux/kernel.h>
 26 #include <linux/module.h>
 27 #include <linux/pci.h>
 28 #include <linux/init.h>
 29 #include <linux/blkdev.h>
 30 #include <linux/delay.h>
 31 #include <linux/device.h>
 32 #include <scsi/scsi.h>
 33 #include <scsi/scsi_host.h>
 34 #include <scsi/scsi_cmnd.h>
 35 #include <linux/libata.h>
 36 
 37 #define DRV_NAME        "pata_pdc2027x"
 38 #define DRV_VERSION     "1.0"
 39 #undef PDC_DEBUG
 40 
 41 #ifdef PDC_DEBUG
 42 #define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
 43 #else
 44 #define PDPRINTK(fmt, args...)
 45 #endif
 46 
 47 enum {
 48         PDC_MMIO_BAR            = 5,
 49 
 50         PDC_UDMA_100            = 0,
 51         PDC_UDMA_133            = 1,
 52 
 53         PDC_100_MHZ             = 100000000,
 54         PDC_133_MHZ             = 133333333,
 55 
 56         PDC_SYS_CTL             = 0x1100,
 57         PDC_ATA_CTL             = 0x1104,
 58         PDC_GLOBAL_CTL          = 0x1108,
 59         PDC_CTCR0               = 0x110C,
 60         PDC_CTCR1               = 0x1110,
 61         PDC_BYTE_COUNT          = 0x1120,
 62         PDC_PLL_CTL             = 0x1202,
 63 };
 64 
 65 static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
 66 #ifdef CONFIG_PM
 67 static int pdc2027x_reinit_one(struct pci_dev *pdev);
 68 #endif
 69 static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline);
 70 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
 71 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
 72 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
 73 static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask);
 74 static int pdc2027x_cable_detect(struct ata_port *ap);
 75 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed);
 76 
 77 /*
 78  * ATA Timing Tables based on 133MHz controller clock.
 79  * These tables are only used when the controller is in 133MHz clock.
 80  * If the controller is in 100MHz clock, the ASIC hardware will
 81  * set the timing registers automatically when "set feature" command
 82  * is issued to the device. However, if the controller clock is 133MHz,
 83  * the following tables must be used.
 84  */
 85 static struct pdc2027x_pio_timing {
 86         u8 value0, value1, value2;
 87 } pdc2027x_pio_timing_tbl [] = {
 88         { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
 89         { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
 90         { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
 91         { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
 92         { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
 93 };
 94 
 95 static struct pdc2027x_mdma_timing {
 96         u8 value0, value1;
 97 } pdc2027x_mdma_timing_tbl [] = {
 98         { 0xdf, 0x5f }, /* MDMA mode 0 */
 99         { 0x6b, 0x27 }, /* MDMA mode 1 */
100         { 0x69, 0x25 }, /* MDMA mode 2 */
101 };
102 
103 static struct pdc2027x_udma_timing {
104         u8 value0, value1, value2;
105 } pdc2027x_udma_timing_tbl [] = {
106         { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
107         { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
108         { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
109         { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
110         { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
111         { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
112         { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
113 };
114 
115 static const struct pci_device_id pdc2027x_pci_tbl[] = {
116         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 },
117         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 },
118         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 },
119         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 },
120         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 },
121         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 },
122         { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 },
123 
124         { }     /* terminate list */
125 };
126 
127 static struct pci_driver pdc2027x_pci_driver = {
128         .name                   = DRV_NAME,
129         .id_table               = pdc2027x_pci_tbl,
130         .probe                  = pdc2027x_init_one,
131         .remove                 = ata_pci_remove_one,
132 #ifdef CONFIG_PM
133         .suspend                = ata_pci_device_suspend,
134         .resume                 = pdc2027x_reinit_one,
135 #endif
136 };
137 
138 static struct scsi_host_template pdc2027x_sht = {
139         ATA_BMDMA_SHT(DRV_NAME),
140 };
141 
142 static struct ata_port_operations pdc2027x_pata100_ops = {
143         .inherits               = &ata_bmdma_port_ops,
144         .check_atapi_dma        = pdc2027x_check_atapi_dma,
145         .cable_detect           = pdc2027x_cable_detect,
146         .prereset               = pdc2027x_prereset,
147 };
148 
149 static struct ata_port_operations pdc2027x_pata133_ops = {
150         .inherits               = &pdc2027x_pata100_ops,
151         .mode_filter            = pdc2027x_mode_filter,
152         .set_piomode            = pdc2027x_set_piomode,
153         .set_dmamode            = pdc2027x_set_dmamode,
154         .set_mode               = pdc2027x_set_mode,
155 };
156 
157 static struct ata_port_info pdc2027x_port_info[] = {
158         /* PDC_UDMA_100 */
159         {
160                 .flags          = ATA_FLAG_SLAVE_POSS,
161                 .pio_mask       = ATA_PIO4,
162                 .mwdma_mask     = ATA_MWDMA2,
163                 .udma_mask      = ATA_UDMA5,
164                 .port_ops       = &pdc2027x_pata100_ops,
165         },
166         /* PDC_UDMA_133 */
167         {
168                 .flags          = ATA_FLAG_SLAVE_POSS,
169                 .pio_mask       = ATA_PIO4,
170                 .mwdma_mask     = ATA_MWDMA2,
171                 .udma_mask      = ATA_UDMA6,
172                 .port_ops       = &pdc2027x_pata133_ops,
173         },
174 };
175 
176 MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
177 MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
178 MODULE_LICENSE("GPL");
179 MODULE_VERSION(DRV_VERSION);
180 MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
181 
182 /**
183  *      port_mmio - Get the MMIO address of PDC2027x extended registers
184  *      @ap: Port
185  *      @offset: offset from mmio base
186  */
187 static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset)
188 {
189         return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset;
190 }
191 
192 /**
193  *      dev_mmio - Get the MMIO address of PDC2027x extended registers
194  *      @ap: Port
195  *      @adev: device
196  *      @offset: offset from mmio base
197  */
198 static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
199 {
200         u8 adj = (adev->devno) ? 0x08 : 0x00;
201         return port_mmio(ap, offset) + adj;
202 }
203 
204 /**
205  *      pdc2027x_pata_cable_detect - Probe host controller cable detect info
206  *      @ap: Port for which cable detect info is desired
207  *
208  *      Read 80c cable indicator from Promise extended register.
209  *      This register is latched when the system is reset.
210  *
211  *      LOCKING:
212  *      None (inherited from caller).
213  */
214 static int pdc2027x_cable_detect(struct ata_port *ap)
215 {
216         u32 cgcr;
217 
218         /* check cable detect results */
219         cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL));
220         if (cgcr & (1 << 26))
221                 goto cbl40;
222 
223         PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
224 
225         return ATA_CBL_PATA80;
226 cbl40:
227         printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
228         return ATA_CBL_PATA40;
229 }
230 
231 /**
232  * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
233  * @ap: Port to check
234  */
235 static inline int pdc2027x_port_enabled(struct ata_port *ap)
236 {
237         return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
238 }
239 
240 /**
241  *      pdc2027x_prereset - prereset for PATA host controller
242  *      @link: Target link
243  *      @deadline: deadline jiffies for the operation
244  *
245  *      Probeinit including cable detection.
246  *
247  *      LOCKING:
248  *      None (inherited from caller).
249  */
250 
251 static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline)
252 {
253         /* Check whether port enabled */
254         if (!pdc2027x_port_enabled(link->ap))
255                 return -ENOENT;
256         return ata_sff_prereset(link, deadline);
257 }
258 
259 /**
260  *      pdc2720x_mode_filter    -       mode selection filter
261  *      @adev: ATA device
262  *      @mask: list of modes proposed
263  *
264  *      Block UDMA on devices that cause trouble with this controller.
265  */
266 
267 static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask)
268 {
269         unsigned char model_num[ATA_ID_PROD_LEN + 1];
270         struct ata_device *pair = ata_dev_pair(adev);
271 
272         if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL)
273                 return mask;
274 
275         /* Check for slave of a Maxtor at UDMA6 */
276         ata_id_c_string(pair->id, model_num, ATA_ID_PROD,
277                           ATA_ID_PROD_LEN + 1);
278         /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */
279         if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6)
280                 mask &= ~ (1 << (6 + ATA_SHIFT_UDMA));
281 
282         return mask;
283 }
284 
285 /**
286  *      pdc2027x_set_piomode - Initialize host controller PATA PIO timings
287  *      @ap: Port to configure
288  *      @adev: um
289  *
290  *      Set PIO mode for device.
291  *
292  *      LOCKING:
293  *      None (inherited from caller).
294  */
295 
296 static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
297 {
298         unsigned int pio = adev->pio_mode - XFER_PIO_0;
299         u32 ctcr0, ctcr1;
300 
301         PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
302 
303         /* Sanity check */
304         if (pio > 4) {
305                 printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
306                 return;
307 
308         }
309 
310         /* Set the PIO timing registers using value table for 133MHz */
311         PDPRINTK("Set pio regs... \n");
312 
313         ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
314         ctcr0 &= 0xffff0000;
315         ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
316                 (pdc2027x_pio_timing_tbl[pio].value1 << 8);
317         iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
318 
319         ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
320         ctcr1 &= 0x00ffffff;
321         ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
322         iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
323 
324         PDPRINTK("Set pio regs done\n");
325 
326         PDPRINTK("Set to pio mode[%u] \n", pio);
327 }
328 
329 /**
330  *      pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
331  *      @ap: Port to configure
332  *      @adev: um
333  *
334  *      Set UDMA mode for device.
335  *
336  *      LOCKING:
337  *      None (inherited from caller).
338  */
339 static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
340 {
341         unsigned int dma_mode = adev->dma_mode;
342         u32 ctcr0, ctcr1;
343 
344         if ((dma_mode >= XFER_UDMA_0) &&
345            (dma_mode <= XFER_UDMA_6)) {
346                 /* Set the UDMA timing registers with value table for 133MHz */
347                 unsigned int udma_mode = dma_mode & 0x07;
348 
349                 if (dma_mode == XFER_UDMA_2) {
350                         /*
351                          * Turn off tHOLD.
352                          * If tHOLD is '1', the hardware will add half clock for data hold time.
353                          * This code segment seems to be no effect. tHOLD will be overwritten below.
354                          */
355                         ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
356                         iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
357                 }
358 
359                 PDPRINTK("Set udma regs... \n");
360 
361                 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
362                 ctcr1 &= 0xff000000;
363                 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
364                         (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
365                         (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
366                 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
367 
368                 PDPRINTK("Set udma regs done\n");
369 
370                 PDPRINTK("Set to udma mode[%u] \n", udma_mode);
371 
372         } else  if ((dma_mode >= XFER_MW_DMA_0) &&
373                    (dma_mode <= XFER_MW_DMA_2)) {
374                 /* Set the MDMA timing registers with value table for 133MHz */
375                 unsigned int mdma_mode = dma_mode & 0x07;
376 
377                 PDPRINTK("Set mdma regs... \n");
378                 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
379 
380                 ctcr0 &= 0x0000ffff;
381                 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
382                         (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
383 
384                 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
385                 PDPRINTK("Set mdma regs done\n");
386 
387                 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
388         } else {
389                 printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
390         }
391 }
392 
393 /**
394  *      pdc2027x_set_mode - Set the timing registers back to correct values.
395  *      @link: link to configure
396  *      @r_failed: Returned device for failure
397  *
398  *      The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
399  *      automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
400  *      This function overwrites the possibly incorrect values set by the hardware to be correct.
401  */
402 static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed)
403 {
404         struct ata_port *ap = link->ap;
405         struct ata_device *dev;
406         int rc;
407 
408         rc = ata_do_set_mode(link, r_failed);
409         if (rc < 0)
410                 return rc;
411 
412         ata_for_each_dev(dev, link, ENABLED) {
413                 pdc2027x_set_piomode(ap, dev);
414 
415                 /*
416                  * Enable prefetch if the device support PIO only.
417                  */
418                 if (dev->xfer_shift == ATA_SHIFT_PIO) {
419                         u32 ctcr1 = ioread32(dev_mmio(ap, dev, PDC_CTCR1));
420                         ctcr1 |= (1 << 25);
421                         iowrite32(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
422 
423                         PDPRINTK("Turn on prefetch\n");
424                 } else {
425                         pdc2027x_set_dmamode(ap, dev);
426                 }
427         }
428         return 0;
429 }
430 
431 /**
432  *      pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
433  *      @qc: Metadata associated with taskfile to check
434  *
435  *      LOCKING:
436  *      None (inherited from caller).
437  *
438  *      RETURNS: 0 when ATAPI DMA can be used
439  *               1 otherwise
440  */
441 static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
442 {
443         struct scsi_cmnd *cmd = qc->scsicmd;
444         u8 *scsicmd = cmd->cmnd;
445         int rc = 1; /* atapi dma off by default */
446 
447         /*
448          * This workaround is from Promise's GPL driver.
449          * If ATAPI DMA is used for commands not in the
450          * following white list, say MODE_SENSE and REQUEST_SENSE,
451          * pdc2027x might hit the irq lost problem.
452          */
453         switch (scsicmd[0]) {
454         case READ_10:
455         case WRITE_10:
456         case READ_12:
457         case WRITE_12:
458         case READ_6:
459         case WRITE_6:
460         case 0xad: /* READ_DVD_STRUCTURE */
461         case 0xbe: /* READ_CD */
462                 /* ATAPI DMA is ok */
463                 rc = 0;
464                 break;
465         default:
466                 ;
467         }
468 
469         return rc;
470 }
471 
472 /**
473  * pdc_read_counter - Read the ctr counter
474  * @host: target ATA host
475  */
476 
477 static long pdc_read_counter(struct ata_host *host)
478 {
479         void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
480         long counter;
481         int retry = 1;
482         u32 bccrl, bccrh, bccrlv, bccrhv;
483 
484 retry:
485         bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
486         bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
487 
488         /* Read the counter values again for verification */
489         bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
490         bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
491 
492         counter = (bccrh << 15) | bccrl;
493 
494         PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh,  bccrl);
495         PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
496 
497         /*
498          * The 30-bit decreasing counter are read by 2 pieces.
499          * Incorrect value may be read when both bccrh and bccrl are changing.
500          * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
501          */
502         if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
503                 retry--;
504                 PDPRINTK("rereading counter\n");
505                 goto retry;
506         }
507 
508         return counter;
509 }
510 
511 /**
512  * adjust_pll - Adjust the PLL input clock in Hz.
513  *
514  * @pdc_controller: controller specific information
515  * @host: target ATA host
516  * @pll_clock: The input of PLL in HZ
517  */
518 static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx)
519 {
520         void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
521         u16 pll_ctl;
522         long pll_clock_khz = pll_clock / 1000;
523         long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
524         long ratio = pout_required / pll_clock_khz;
525         int F, R;
526 
527         /* Sanity check */
528         if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
529                 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
530                 return;
531         }
532 
533 #ifdef PDC_DEBUG
534         PDPRINTK("pout_required is %ld\n", pout_required);
535 
536         /* Show the current clock value of PLL control register
537          * (maybe already configured by the firmware)
538          */
539         pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
540 
541         PDPRINTK("pll_ctl[%X]\n", pll_ctl);
542 #endif
543 
544         /*
545          * Calculate the ratio of F, R and OD
546          * POUT = (F + 2) / (( R + 2) * NO)
547          */
548         if (ratio < 8600L) { /* 8.6x */
549                 /* Using NO = 0x01, R = 0x0D */
550                 R = 0x0d;
551         } else if (ratio < 12900L) { /* 12.9x */
552                 /* Using NO = 0x01, R = 0x08 */
553                 R = 0x08;
554         } else if (ratio < 16100L) { /* 16.1x */
555                 /* Using NO = 0x01, R = 0x06 */
556                 R = 0x06;
557         } else if (ratio < 64000L) { /* 64x */
558                 R = 0x00;
559         } else {
560                 /* Invalid ratio */
561                 printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
562                 return;
563         }
564 
565         F = (ratio * (R+2)) / 1000 - 2;
566 
567         if (unlikely(F < 0 || F > 127)) {
568                 /* Invalid F */
569                 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
570                 return;
571         }
572 
573         PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
574 
575         pll_ctl = (R << 8) | F;
576 
577         PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
578 
579         iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL);
580         ioread16(mmio_base + PDC_PLL_CTL); /* flush */
581 
582         /* Wait the PLL circuit to be stable */
583         mdelay(30);
584 
585 #ifdef PDC_DEBUG
586         /*
587          *  Show the current clock value of PLL control register
588          * (maybe configured by the firmware)
589          */
590         pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
591 
592         PDPRINTK("pll_ctl[%X]\n", pll_ctl);
593 #endif
594 
595         return;
596 }
597 
598 /**
599  * detect_pll_input_clock - Detect the PLL input clock in Hz.
600  * @host: target ATA host
601  * Ex. 16949000 on 33MHz PCI bus for pdc20275.
602  *     Half of the PCI clock.
603  */
604 static long pdc_detect_pll_input_clock(struct ata_host *host)
605 {
606         void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
607         u32 scr;
608         long start_count, end_count;
609         struct timeval start_time, end_time;
610         long pll_clock, usec_elapsed;
611 
612         /* Start the test mode */
613         scr = ioread32(mmio_base + PDC_SYS_CTL);
614         PDPRINTK("scr[%X]\n", scr);
615         iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
616         ioread32(mmio_base + PDC_SYS_CTL); /* flush */
617 
618         /* Read current counter value */
619         start_count = pdc_read_counter(host);
620         do_gettimeofday(&start_time);
621 
622         /* Let the counter run for 100 ms. */
623         mdelay(100);
624 
625         /* Read the counter values again */
626         end_count = pdc_read_counter(host);
627         do_gettimeofday(&end_time);
628 
629         /* Stop the test mode */
630         scr = ioread32(mmio_base + PDC_SYS_CTL);
631         PDPRINTK("scr[%X]\n", scr);
632         iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
633         ioread32(mmio_base + PDC_SYS_CTL); /* flush */
634 
635         /* calculate the input clock in Hz */
636         usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
637                 (end_time.tv_usec - start_time.tv_usec);
638 
639         pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 *
640                 (100000000 / usec_elapsed);
641 
642         PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
643         PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
644 
645         return pll_clock;
646 }
647 
648 /**
649  * pdc_hardware_init - Initialize the hardware.
650  * @host: target ATA host
651  * @board_idx: board identifier
652  */
653 static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
654 {
655         long pll_clock;
656 
657         /*
658          * Detect PLL input clock rate.
659          * On some system, where PCI bus is running at non-standard clock rate.
660          * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
661          * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
662          */
663         pll_clock = pdc_detect_pll_input_clock(host);
664 
665         dev_info(host->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
666 
667         /* Adjust PLL control register */
668         pdc_adjust_pll(host, pll_clock, board_idx);
669 
670         return 0;
671 }
672 
673 /**
674  * pdc_ata_setup_port - setup the mmio address
675  * @port: ata ioports to setup
676  * @base: base address
677  */
678 static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base)
679 {
680         port->cmd_addr          =
681         port->data_addr         = base;
682         port->feature_addr      =
683         port->error_addr        = base + 0x05;
684         port->nsect_addr        = base + 0x0a;
685         port->lbal_addr         = base + 0x0f;
686         port->lbam_addr         = base + 0x10;
687         port->lbah_addr         = base + 0x15;
688         port->device_addr       = base + 0x1a;
689         port->command_addr      =
690         port->status_addr       = base + 0x1f;
691         port->altstatus_addr    =
692         port->ctl_addr          = base + 0x81a;
693 }
694 
695 /**
696  * pdc2027x_init_one - PCI probe function
697  * Called when an instance of PCI adapter is inserted.
698  * This function checks whether the hardware is supported,
699  * initialize hardware and register an instance of ata_host to
700  * libata.  (implements struct pci_driver.probe() )
701  *
702  * @pdev: instance of pci_dev found
703  * @ent:  matching entry in the id_tbl[]
704  */
705 static int pdc2027x_init_one(struct pci_dev *pdev,
706                              const struct pci_device_id *ent)
707 {
708         static const unsigned long cmd_offset[] = { 0x17c0, 0x15c0 };
709         static const unsigned long bmdma_offset[] = { 0x1000, 0x1008 };
710         unsigned int board_idx = (unsigned int) ent->driver_data;
711         const struct ata_port_info *ppi[] =
712                 { &pdc2027x_port_info[board_idx], NULL };
713         struct ata_host *host;
714         void __iomem *mmio_base;
715         int i, rc;
716 
717         ata_print_version_once(&pdev->dev, DRV_VERSION);
718 
719         /* alloc host */
720         host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
721         if (!host)
722                 return -ENOMEM;
723 
724         /* acquire resources and fill host */
725         rc = pcim_enable_device(pdev);
726         if (rc)
727                 return rc;
728 
729         rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
730         if (rc)
731                 return rc;
732         host->iomap = pcim_iomap_table(pdev);
733 
734         rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
735         if (rc)
736                 return rc;
737 
738         rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
739         if (rc)
740                 return rc;
741 
742         mmio_base = host->iomap[PDC_MMIO_BAR];
743 
744         for (i = 0; i < 2; i++) {
745                 struct ata_port *ap = host->ports[i];
746 
747                 pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]);
748                 ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i];
749 
750                 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
751                 ata_port_pbar_desc(ap, PDC_MMIO_BAR, cmd_offset[i], "cmd");
752         }
753 
754         //pci_enable_intx(pdev);
755 
756         /* initialize adapter */
757         if (pdc_hardware_init(host, board_idx) != 0)
758                 return -EIO;
759 
760         pci_set_master(pdev);
761         return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
762                                  IRQF_SHARED, &pdc2027x_sht);
763 }
764 
765 #ifdef CONFIG_PM
766 static int pdc2027x_reinit_one(struct pci_dev *pdev)
767 {
768         struct ata_host *host = pci_get_drvdata(pdev);
769         unsigned int board_idx;
770         int rc;
771 
772         rc = ata_pci_device_do_resume(pdev);
773         if (rc)
774                 return rc;
775 
776         if (pdev->device == PCI_DEVICE_ID_PROMISE_20268 ||
777             pdev->device == PCI_DEVICE_ID_PROMISE_20270)
778                 board_idx = PDC_UDMA_100;
779         else
780                 board_idx = PDC_UDMA_133;
781 
782         if (pdc_hardware_init(host, board_idx))
783                 return -EIO;
784 
785         ata_host_resume(host);
786         return 0;
787 }
788 #endif
789 
790 module_pci_driver(pdc2027x_pci_driver);
791 

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