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Linux/drivers/ata/pata_ninja32.c

  1 /*
  2  * pata_ninja32.c       - Ninja32 PATA for new ATA layer
  3  *                        (C) 2007 Red Hat Inc
  4  *
  5  * Note: The controller like many controllers has shared timings for
  6  * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
  7  * in the dma_stop function. Thus we actually don't need a set_dmamode
  8  * method as the PIO method is always called and will set the right PIO
  9  * timing parameters.
 10  *
 11  * The Ninja32 Cardbus is not a generic SFF controller. Instead it is
 12  * laid out as follows off BAR 0. This is based upon Mark Lord's delkin
 13  * driver and the extensive analysis done by the BSD developers, notably
 14  * ITOH Yasufumi.
 15  *
 16  *      Base + 0x00 IRQ Status
 17  *      Base + 0x01 IRQ control
 18  *      Base + 0x02 Chipset control
 19  *      Base + 0x03 Unknown
 20  *      Base + 0x04 VDMA and reset control + wait bits
 21  *      Base + 0x08 BMIMBA
 22  *      Base + 0x0C DMA Length
 23  *      Base + 0x10 Taskfile
 24  *      Base + 0x18 BMDMA Status ?
 25  *      Base + 0x1C
 26  *      Base + 0x1D Bus master control
 27  *              bit 0 = enable
 28  *              bit 1 = 0 write/1 read
 29  *              bit 2 = 1 sgtable
 30  *              bit 3 = go
 31  *              bit 4-6 wait bits
 32  *              bit 7 = done
 33  *      Base + 0x1E AltStatus
 34  *      Base + 0x1F timing register
 35  */
 36 
 37 #include <linux/kernel.h>
 38 #include <linux/module.h>
 39 #include <linux/pci.h>
 40 #include <linux/init.h>
 41 #include <linux/blkdev.h>
 42 #include <linux/delay.h>
 43 #include <scsi/scsi_host.h>
 44 #include <linux/libata.h>
 45 
 46 #define DRV_NAME "pata_ninja32"
 47 #define DRV_VERSION "0.1.5"
 48 
 49 
 50 /**
 51  *      ninja32_set_piomode     -       set initial PIO mode data
 52  *      @ap: ATA interface
 53  *      @adev: ATA device
 54  *
 55  *      Called to do the PIO mode setup. Our timing registers are shared
 56  *      but we want to set the PIO timing by default.
 57  */
 58 
 59 static void ninja32_set_piomode(struct ata_port *ap, struct ata_device *adev)
 60 {
 61         static u16 pio_timing[5] = {
 62                 0xd6, 0x85, 0x44, 0x33, 0x13
 63         };
 64         iowrite8(pio_timing[adev->pio_mode - XFER_PIO_0],
 65                  ap->ioaddr.bmdma_addr + 0x1f);
 66         ap->private_data = adev;
 67 }
 68 
 69 
 70 static void ninja32_dev_select(struct ata_port *ap, unsigned int device)
 71 {
 72         struct ata_device *adev = &ap->link.device[device];
 73         if (ap->private_data != adev) {
 74                 iowrite8(0xd6, ap->ioaddr.bmdma_addr + 0x1f);
 75                 ata_sff_dev_select(ap, device);
 76                 ninja32_set_piomode(ap, adev);
 77         }
 78 }
 79 
 80 static struct scsi_host_template ninja32_sht = {
 81         ATA_BMDMA_SHT(DRV_NAME),
 82 };
 83 
 84 static struct ata_port_operations ninja32_port_ops = {
 85         .inherits       = &ata_bmdma_port_ops,
 86         .sff_dev_select = ninja32_dev_select,
 87         .cable_detect   = ata_cable_40wire,
 88         .set_piomode    = ninja32_set_piomode,
 89         .sff_data_xfer  = ata_sff_data_xfer32
 90 };
 91 
 92 static void ninja32_program(void __iomem *base)
 93 {
 94         iowrite8(0x05, base + 0x01);    /* Enable interrupt lines */
 95         iowrite8(0xBE, base + 0x02);    /* Burst, ?? setup */
 96         iowrite8(0x01, base + 0x03);    /* Unknown */
 97         iowrite8(0x20, base + 0x04);    /* WAIT0 */
 98         iowrite8(0x8f, base + 0x05);    /* Unknown */
 99         iowrite8(0xa4, base + 0x1c);    /* Unknown */
100         iowrite8(0x83, base + 0x1d);    /* BMDMA control: WAIT0 */
101 }
102 
103 static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id)
104 {
105         struct ata_host *host;
106         struct ata_port *ap;
107         void __iomem *base;
108         int rc;
109 
110         host = ata_host_alloc(&dev->dev, 1);
111         if (!host)
112                 return -ENOMEM;
113         ap = host->ports[0];
114 
115         /* Set up the PCI device */
116         rc = pcim_enable_device(dev);
117         if (rc)
118                 return rc;
119         rc = pcim_iomap_regions(dev, 1 << 0, DRV_NAME);
120         if (rc == -EBUSY)
121                 pcim_pin_device(dev);
122         if (rc)
123                 return rc;
124 
125         host->iomap = pcim_iomap_table(dev);
126         rc = pci_set_dma_mask(dev, ATA_DMA_MASK);
127         if (rc)
128                 return rc;
129         rc = pci_set_consistent_dma_mask(dev, ATA_DMA_MASK);
130         if (rc)
131                 return rc;
132         pci_set_master(dev);
133 
134         /* Set up the register mappings. We use the I/O mapping as only the
135            older chips also have MMIO on BAR 1 */
136         base = host->iomap[0];
137         if (!base)
138                 return -ENOMEM;
139         ap->ops = &ninja32_port_ops;
140         ap->pio_mask = ATA_PIO4;
141         ap->flags |= ATA_FLAG_SLAVE_POSS;
142 
143         ap->ioaddr.cmd_addr = base + 0x10;
144         ap->ioaddr.ctl_addr = base + 0x1E;
145         ap->ioaddr.altstatus_addr = base + 0x1E;
146         ap->ioaddr.bmdma_addr = base;
147         ata_sff_std_ports(&ap->ioaddr);
148         ap->pflags = ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
149 
150         ninja32_program(base);
151         /* FIXME: Should we disable them at remove ? */
152         return ata_host_activate(host, dev->irq, ata_bmdma_interrupt,
153                                  IRQF_SHARED, &ninja32_sht);
154 }
155 
156 #ifdef CONFIG_PM
157 
158 static int ninja32_reinit_one(struct pci_dev *pdev)
159 {
160         struct ata_host *host = pci_get_drvdata(pdev);
161         int rc;
162 
163         rc = ata_pci_device_do_resume(pdev);
164         if (rc)
165                 return rc;
166         ninja32_program(host->iomap[0]);
167         ata_host_resume(host);
168         return 0;
169 }
170 #endif
171 
172 static const struct pci_device_id ninja32[] = {
173         { 0x10FC, 0x0003, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
174         { 0x1145, 0x8008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
175         { 0x1145, 0xf008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
176         { 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
177         { 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
178         { 0x1145, 0xf02C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
179         { },
180 };
181 
182 static struct pci_driver ninja32_pci_driver = {
183         .name           = DRV_NAME,
184         .id_table       = ninja32,
185         .probe          = ninja32_init_one,
186         .remove         = ata_pci_remove_one,
187 #ifdef CONFIG_PM
188         .suspend        = ata_pci_device_suspend,
189         .resume         = ninja32_reinit_one,
190 #endif
191 };
192 
193 module_pci_driver(ninja32_pci_driver);
194 
195 MODULE_AUTHOR("Alan Cox");
196 MODULE_DESCRIPTION("low-level driver for Ninja32 ATA");
197 MODULE_LICENSE("GPL");
198 MODULE_DEVICE_TABLE(pci, ninja32);
199 MODULE_VERSION(DRV_VERSION);
200 

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