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Linux/drivers/ata/pata_ninja32.c

  1 /*
  2  * pata_ninja32.c       - Ninja32 PATA for new ATA layer
  3  *                        (C) 2007 Red Hat Inc
  4  *
  5  * Note: The controller like many controllers has shared timings for
  6  * PIO and DMA. We thus flip to the DMA timings in dma_start and flip back
  7  * in the dma_stop function. Thus we actually don't need a set_dmamode
  8  * method as the PIO method is always called and will set the right PIO
  9  * timing parameters.
 10  *
 11  * The Ninja32 Cardbus is not a generic SFF controller. Instead it is
 12  * laid out as follows off BAR 0. This is based upon Mark Lord's delkin
 13  * driver and the extensive analysis done by the BSD developers, notably
 14  * ITOH Yasufumi.
 15  *
 16  *      Base + 0x00 IRQ Status
 17  *      Base + 0x01 IRQ control
 18  *      Base + 0x02 Chipset control
 19  *      Base + 0x03 Unknown
 20  *      Base + 0x04 VDMA and reset control + wait bits
 21  *      Base + 0x08 BMIMBA
 22  *      Base + 0x0C DMA Length
 23  *      Base + 0x10 Taskfile
 24  *      Base + 0x18 BMDMA Status ?
 25  *      Base + 0x1C
 26  *      Base + 0x1D Bus master control
 27  *              bit 0 = enable
 28  *              bit 1 = 0 write/1 read
 29  *              bit 2 = 1 sgtable
 30  *              bit 3 = go
 31  *              bit 4-6 wait bits
 32  *              bit 7 = done
 33  *      Base + 0x1E AltStatus
 34  *      Base + 0x1F timing register
 35  */
 36 
 37 #include <linux/kernel.h>
 38 #include <linux/module.h>
 39 #include <linux/pci.h>
 40 #include <linux/blkdev.h>
 41 #include <linux/delay.h>
 42 #include <scsi/scsi_host.h>
 43 #include <linux/libata.h>
 44 
 45 #define DRV_NAME "pata_ninja32"
 46 #define DRV_VERSION "0.1.5"
 47 
 48 
 49 /**
 50  *      ninja32_set_piomode     -       set initial PIO mode data
 51  *      @ap: ATA interface
 52  *      @adev: ATA device
 53  *
 54  *      Called to do the PIO mode setup. Our timing registers are shared
 55  *      but we want to set the PIO timing by default.
 56  */
 57 
 58 static void ninja32_set_piomode(struct ata_port *ap, struct ata_device *adev)
 59 {
 60         static u16 pio_timing[5] = {
 61                 0xd6, 0x85, 0x44, 0x33, 0x13
 62         };
 63         iowrite8(pio_timing[adev->pio_mode - XFER_PIO_0],
 64                  ap->ioaddr.bmdma_addr + 0x1f);
 65         ap->private_data = adev;
 66 }
 67 
 68 
 69 static void ninja32_dev_select(struct ata_port *ap, unsigned int device)
 70 {
 71         struct ata_device *adev = &ap->link.device[device];
 72         if (ap->private_data != adev) {
 73                 iowrite8(0xd6, ap->ioaddr.bmdma_addr + 0x1f);
 74                 ata_sff_dev_select(ap, device);
 75                 ninja32_set_piomode(ap, adev);
 76         }
 77 }
 78 
 79 static struct scsi_host_template ninja32_sht = {
 80         ATA_BMDMA_SHT(DRV_NAME),
 81 };
 82 
 83 static struct ata_port_operations ninja32_port_ops = {
 84         .inherits       = &ata_bmdma_port_ops,
 85         .sff_dev_select = ninja32_dev_select,
 86         .cable_detect   = ata_cable_40wire,
 87         .set_piomode    = ninja32_set_piomode,
 88         .sff_data_xfer  = ata_sff_data_xfer32
 89 };
 90 
 91 static void ninja32_program(void __iomem *base)
 92 {
 93         iowrite8(0x05, base + 0x01);    /* Enable interrupt lines */
 94         iowrite8(0xBE, base + 0x02);    /* Burst, ?? setup */
 95         iowrite8(0x01, base + 0x03);    /* Unknown */
 96         iowrite8(0x20, base + 0x04);    /* WAIT0 */
 97         iowrite8(0x8f, base + 0x05);    /* Unknown */
 98         iowrite8(0xa4, base + 0x1c);    /* Unknown */
 99         iowrite8(0x83, base + 0x1d);    /* BMDMA control: WAIT0 */
100 }
101 
102 static int ninja32_init_one(struct pci_dev *dev, const struct pci_device_id *id)
103 {
104         struct ata_host *host;
105         struct ata_port *ap;
106         void __iomem *base;
107         int rc;
108 
109         host = ata_host_alloc(&dev->dev, 1);
110         if (!host)
111                 return -ENOMEM;
112         ap = host->ports[0];
113 
114         /* Set up the PCI device */
115         rc = pcim_enable_device(dev);
116         if (rc)
117                 return rc;
118         rc = pcim_iomap_regions(dev, 1 << 0, DRV_NAME);
119         if (rc == -EBUSY)
120                 pcim_pin_device(dev);
121         if (rc)
122                 return rc;
123 
124         host->iomap = pcim_iomap_table(dev);
125         rc = pci_set_dma_mask(dev, ATA_DMA_MASK);
126         if (rc)
127                 return rc;
128         rc = pci_set_consistent_dma_mask(dev, ATA_DMA_MASK);
129         if (rc)
130                 return rc;
131         pci_set_master(dev);
132 
133         /* Set up the register mappings. We use the I/O mapping as only the
134            older chips also have MMIO on BAR 1 */
135         base = host->iomap[0];
136         if (!base)
137                 return -ENOMEM;
138         ap->ops = &ninja32_port_ops;
139         ap->pio_mask = ATA_PIO4;
140         ap->flags |= ATA_FLAG_SLAVE_POSS;
141 
142         ap->ioaddr.cmd_addr = base + 0x10;
143         ap->ioaddr.ctl_addr = base + 0x1E;
144         ap->ioaddr.altstatus_addr = base + 0x1E;
145         ap->ioaddr.bmdma_addr = base;
146         ata_sff_std_ports(&ap->ioaddr);
147         ap->pflags = ATA_PFLAG_PIO32 | ATA_PFLAG_PIO32CHANGE;
148 
149         ninja32_program(base);
150         /* FIXME: Should we disable them at remove ? */
151         return ata_host_activate(host, dev->irq, ata_bmdma_interrupt,
152                                  IRQF_SHARED, &ninja32_sht);
153 }
154 
155 #ifdef CONFIG_PM_SLEEP
156 static int ninja32_reinit_one(struct pci_dev *pdev)
157 {
158         struct ata_host *host = pci_get_drvdata(pdev);
159         int rc;
160 
161         rc = ata_pci_device_do_resume(pdev);
162         if (rc)
163                 return rc;
164         ninja32_program(host->iomap[0]);
165         ata_host_resume(host);
166         return 0;
167 }
168 #endif
169 
170 static const struct pci_device_id ninja32[] = {
171         { 0x10FC, 0x0003, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
172         { 0x1145, 0x8008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
173         { 0x1145, 0xf008, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
174         { 0x1145, 0xf021, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
175         { 0x1145, 0xf024, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
176         { 0x1145, 0xf02C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
177         { },
178 };
179 
180 static struct pci_driver ninja32_pci_driver = {
181         .name           = DRV_NAME,
182         .id_table       = ninja32,
183         .probe          = ninja32_init_one,
184         .remove         = ata_pci_remove_one,
185 #ifdef CONFIG_PM_SLEEP
186         .suspend        = ata_pci_device_suspend,
187         .resume         = ninja32_reinit_one,
188 #endif
189 };
190 
191 module_pci_driver(ninja32_pci_driver);
192 
193 MODULE_AUTHOR("Alan Cox");
194 MODULE_DESCRIPTION("low-level driver for Ninja32 ATA");
195 MODULE_LICENSE("GPL");
196 MODULE_DEVICE_TABLE(pci, ninja32);
197 MODULE_VERSION(DRV_VERSION);
198 

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