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Linux/drivers/ata/pata_mpiix.c

  1 /*
  2  * pata_mpiix.c         - Intel MPIIX PATA for new ATA layer
  3  *                        (C) 2005-2006 Red Hat Inc
  4  *                        Alan Cox <alan@lxorguk.ukuu.org.uk>
  5  *
  6  * The MPIIX is different enough to the PIIX4 and friends that we give it
  7  * a separate driver. The old ide/pci code handles this by just not tuning
  8  * MPIIX at all.
  9  *
 10  * The MPIIX also differs in another important way from the majority of PIIX
 11  * devices. The chip is a bridge (pardon the pun) between the old world of
 12  * ISA IDE and PCI IDE. Although the ATA timings are PCI configured the actual
 13  * IDE controller is not decoded in PCI space and the chip does not claim to
 14  * be IDE class PCI. This requires slightly non-standard probe logic compared
 15  * with PCI IDE and also that we do not disable the device when our driver is
 16  * unloaded (as it has many other functions).
 17  *
 18  * The driver consciously keeps this logic internally to avoid pushing quirky
 19  * PATA history into the clean libata layer.
 20  *
 21  * Thinkpad specific note: If you boot an MPIIX using a thinkpad with a PCMCIA
 22  * hard disk present this driver will not detect it. This is not a bug. In this
 23  * configuration the secondary port of the MPIIX is disabled and the addresses
 24  * are decoded by the PCMCIA bridge and therefore are for a generic IDE driver
 25  * to operate.
 26  */
 27 
 28 #include <linux/kernel.h>
 29 #include <linux/module.h>
 30 #include <linux/pci.h>
 31 #include <linux/blkdev.h>
 32 #include <linux/delay.h>
 33 #include <scsi/scsi_host.h>
 34 #include <linux/libata.h>
 35 
 36 #define DRV_NAME "pata_mpiix"
 37 #define DRV_VERSION "0.7.7"
 38 
 39 enum {
 40         IDETIM = 0x6C,          /* IDE control register */
 41         IORDY = (1 << 1),
 42         PPE = (1 << 2),
 43         FTIM = (1 << 0),
 44         ENABLED = (1 << 15),
 45         SECONDARY = (1 << 14)
 46 };
 47 
 48 static int mpiix_pre_reset(struct ata_link *link, unsigned long deadline)
 49 {
 50         struct ata_port *ap = link->ap;
 51         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 52         static const struct pci_bits mpiix_enable_bits = { 0x6D, 1, 0x80, 0x80 };
 53 
 54         if (!pci_test_config_bits(pdev, &mpiix_enable_bits))
 55                 return -ENOENT;
 56 
 57         return ata_sff_prereset(link, deadline);
 58 }
 59 
 60 /**
 61  *      mpiix_set_piomode       -       set initial PIO mode data
 62  *      @ap: ATA interface
 63  *      @adev: ATA device
 64  *
 65  *      Called to do the PIO mode setup. The MPIIX allows us to program the
 66  *      IORDY sample point (2-5 clocks), recovery (1-4 clocks) and whether
 67  *      prefetching or IORDY are used.
 68  *
 69  *      This would get very ugly because we can only program timing for one
 70  *      device at a time, the other gets PIO0. Fortunately libata calls
 71  *      our qc_issue command before a command is issued so we can flip the
 72  *      timings back and forth to reduce the pain.
 73  */
 74 
 75 static void mpiix_set_piomode(struct ata_port *ap, struct ata_device *adev)
 76 {
 77         int control = 0;
 78         int pio = adev->pio_mode - XFER_PIO_0;
 79         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 80         u16 idetim;
 81         static const     /* ISP  RTC */
 82         u8 timings[][2] = { { 0, 0 },
 83                             { 0, 0 },
 84                             { 1, 0 },
 85                             { 2, 1 },
 86                             { 2, 3 }, };
 87 
 88         pci_read_config_word(pdev, IDETIM, &idetim);
 89 
 90         /* Mask the IORDY/TIME/PPE for this device */
 91         if (adev->class == ATA_DEV_ATA)
 92                 control |= PPE;         /* Enable prefetch/posting for disk */
 93         if (ata_pio_need_iordy(adev))
 94                 control |= IORDY;
 95         if (pio > 1)
 96                 control |= FTIM;        /* This drive is on the fast timing bank */
 97 
 98         /* Mask out timing and clear both TIME bank selects */
 99         idetim &= 0xCCEE;
100         idetim &= ~(0x07  << (4 * adev->devno));
101         idetim |= control << (4 * adev->devno);
102 
103         idetim |= (timings[pio][0] << 12) | (timings[pio][1] << 8);
104         pci_write_config_word(pdev, IDETIM, idetim);
105 
106         /* We use ap->private_data as a pointer to the device currently
107            loaded for timing */
108         ap->private_data = adev;
109 }
110 
111 /**
112  *      mpiix_qc_issue          -       command issue
113  *      @qc: command pending
114  *
115  *      Called when the libata layer is about to issue a command. We wrap
116  *      this interface so that we can load the correct ATA timings if
117  *      necessary. Our logic also clears TIME0/TIME1 for the other device so
118  *      that, even if we get this wrong, cycles to the other device will
119  *      be made PIO0.
120  */
121 
122 static unsigned int mpiix_qc_issue(struct ata_queued_cmd *qc)
123 {
124         struct ata_port *ap = qc->ap;
125         struct ata_device *adev = qc->dev;
126 
127         /* If modes have been configured and the channel data is not loaded
128            then load it. We have to check if pio_mode is set as the core code
129            does not set adev->pio_mode to XFER_PIO_0 while probing as would be
130            logical */
131 
132         if (adev->pio_mode && adev != ap->private_data)
133                 mpiix_set_piomode(ap, adev);
134 
135         return ata_sff_qc_issue(qc);
136 }
137 
138 static struct scsi_host_template mpiix_sht = {
139         ATA_PIO_SHT(DRV_NAME),
140 };
141 
142 static struct ata_port_operations mpiix_port_ops = {
143         .inherits       = &ata_sff_port_ops,
144         .qc_issue       = mpiix_qc_issue,
145         .cable_detect   = ata_cable_40wire,
146         .set_piomode    = mpiix_set_piomode,
147         .prereset       = mpiix_pre_reset,
148         .sff_data_xfer  = ata_sff_data_xfer32,
149 };
150 
151 static int mpiix_init_one(struct pci_dev *dev, const struct pci_device_id *id)
152 {
153         /* Single threaded by the PCI probe logic */
154         struct ata_host *host;
155         struct ata_port *ap;
156         void __iomem *cmd_addr, *ctl_addr;
157         u16 idetim;
158         int cmd, ctl, irq;
159 
160         ata_print_version_once(&dev->dev, DRV_VERSION);
161 
162         host = ata_host_alloc(&dev->dev, 1);
163         if (!host)
164                 return -ENOMEM;
165         ap = host->ports[0];
166 
167         /* MPIIX has many functions which can be turned on or off according
168            to other devices present. Make sure IDE is enabled before we try
169            and use it */
170 
171         pci_read_config_word(dev, IDETIM, &idetim);
172         if (!(idetim & ENABLED))
173                 return -ENODEV;
174 
175         /* See if it's primary or secondary channel... */
176         if (!(idetim & SECONDARY)) {
177                 cmd = 0x1F0;
178                 ctl = 0x3F6;
179                 irq = 14;
180         } else {
181                 cmd = 0x170;
182                 ctl = 0x376;
183                 irq = 15;
184         }
185 
186         cmd_addr = devm_ioport_map(&dev->dev, cmd, 8);
187         ctl_addr = devm_ioport_map(&dev->dev, ctl, 1);
188         if (!cmd_addr || !ctl_addr)
189                 return -ENOMEM;
190 
191         ata_port_desc(ap, "cmd 0x%x ctl 0x%x", cmd, ctl);
192 
193         /* We do our own plumbing to avoid leaking special cases for whacko
194            ancient hardware into the core code. There are two issues to
195            worry about.  #1 The chip is a bridge so if in legacy mode and
196            without BARs set fools the setup.  #2 If you pci_disable_device
197            the MPIIX your box goes castors up */
198 
199         ap->ops = &mpiix_port_ops;
200         ap->pio_mask = ATA_PIO4;
201         ap->flags |= ATA_FLAG_SLAVE_POSS;
202 
203         ap->ioaddr.cmd_addr = cmd_addr;
204         ap->ioaddr.ctl_addr = ctl_addr;
205         ap->ioaddr.altstatus_addr = ctl_addr;
206 
207         /* Let libata fill in the port details */
208         ata_sff_std_ports(&ap->ioaddr);
209 
210         /* activate host */
211         return ata_host_activate(host, irq, ata_sff_interrupt, IRQF_SHARED,
212                                  &mpiix_sht);
213 }
214 
215 static const struct pci_device_id mpiix[] = {
216         { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_82371MX), },
217 
218         { },
219 };
220 
221 static struct pci_driver mpiix_pci_driver = {
222         .name           = DRV_NAME,
223         .id_table       = mpiix,
224         .probe          = mpiix_init_one,
225         .remove         = ata_pci_remove_one,
226 #ifdef CONFIG_PM_SLEEP
227         .suspend        = ata_pci_device_suspend,
228         .resume         = ata_pci_device_resume,
229 #endif
230 };
231 
232 module_pci_driver(mpiix_pci_driver);
233 
234 MODULE_AUTHOR("Alan Cox");
235 MODULE_DESCRIPTION("low-level driver for Intel MPIIX");
236 MODULE_LICENSE("GPL");
237 MODULE_DEVICE_TABLE(pci, mpiix);
238 MODULE_VERSION(DRV_VERSION);
239 

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