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Linux/drivers/ata/pata_hpt3x2n.c

  1 /*
  2  * Libata driver for the HighPoint 371N, 372N, and 302N UDMA66 ATA controllers.
  3  *
  4  * This driver is heavily based upon:
  5  *
  6  * linux/drivers/ide/pci/hpt366.c               Version 0.36    April 25, 2003
  7  *
  8  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
  9  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
 10  * Portions Copyright (C) 2003          Red Hat Inc
 11  * Portions Copyright (C) 2005-2010     MontaVista Software, Inc.
 12  *
 13  *
 14  * TODO
 15  *      Work out best PLL policy
 16  */
 17 
 18 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 19 
 20 #include <linux/kernel.h>
 21 #include <linux/module.h>
 22 #include <linux/pci.h>
 23 #include <linux/init.h>
 24 #include <linux/blkdev.h>
 25 #include <linux/delay.h>
 26 #include <scsi/scsi_host.h>
 27 #include <linux/libata.h>
 28 
 29 #define DRV_NAME        "pata_hpt3x2n"
 30 #define DRV_VERSION     "0.3.15"
 31 
 32 enum {
 33         HPT_PCI_FAST    =       (1 << 31),
 34         PCI66           =       (1 << 1),
 35         USE_DPLL        =       (1 << 0)
 36 };
 37 
 38 struct hpt_clock {
 39         u8      xfer_speed;
 40         u32     timing;
 41 };
 42 
 43 struct hpt_chip {
 44         const char *name;
 45         struct hpt_clock *clocks[3];
 46 };
 47 
 48 /* key for bus clock timings
 49  * bit
 50  * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 51  *        cycles = value + 1
 52  * 4:8    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 53  *        cycles = value + 1
 54  * 9:12   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 55  *        register access.
 56  * 13:17  cmd_low_time. Active time of DIOW_/DIOR_ during task file
 57  *        register access.
 58  * 18:20  udma_cycle_time. Clock cycles for UDMA xfer.
 59  * 21     CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock.
 60  * 22:24  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
 61  * 25:27  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
 62  *        register access.
 63  * 28     UDMA enable.
 64  * 29     DMA  enable.
 65  * 30     PIO_MST enable. If set, the chip is in bus master mode during
 66  *        PIO xfer.
 67  * 31     FIFO enable. Only for PIO.
 68  */
 69 
 70 /* 66MHz DPLL clocks */
 71 
 72 static struct hpt_clock hpt3x2n_clocks[] = {
 73         {       XFER_UDMA_7,    0x1c869c62      },
 74         {       XFER_UDMA_6,    0x1c869c62      },
 75         {       XFER_UDMA_5,    0x1c8a9c62      },
 76         {       XFER_UDMA_4,    0x1c8a9c62      },
 77         {       XFER_UDMA_3,    0x1c8e9c62      },
 78         {       XFER_UDMA_2,    0x1c929c62      },
 79         {       XFER_UDMA_1,    0x1c9a9c62      },
 80         {       XFER_UDMA_0,    0x1c829c62      },
 81 
 82         {       XFER_MW_DMA_2,  0x2c829c62      },
 83         {       XFER_MW_DMA_1,  0x2c829c66      },
 84         {       XFER_MW_DMA_0,  0x2c829d2e      },
 85 
 86         {       XFER_PIO_4,     0x0c829c62      },
 87         {       XFER_PIO_3,     0x0c829c84      },
 88         {       XFER_PIO_2,     0x0c829ca6      },
 89         {       XFER_PIO_1,     0x0d029d26      },
 90         {       XFER_PIO_0,     0x0d029d5e      },
 91 };
 92 
 93 /**
 94  *      hpt3x2n_find_mode       -       reset the hpt3x2n bus
 95  *      @ap: ATA port
 96  *      @speed: transfer mode
 97  *
 98  *      Return the 32bit register programming information for this channel
 99  *      that matches the speed provided. For the moment the clocks table
100  *      is hard coded but easy to change. This will be needed if we use
101  *      different DPLLs
102  */
103 
104 static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed)
105 {
106         struct hpt_clock *clocks = hpt3x2n_clocks;
107 
108         while (clocks->xfer_speed) {
109                 if (clocks->xfer_speed == speed)
110                         return clocks->timing;
111                 clocks++;
112         }
113         BUG();
114         return 0xffffffffU;     /* silence compiler warning */
115 }
116 
117 /**
118  *      hpt372n_filter  -       mode selection filter
119  *      @adev: ATA device
120  *      @mask: mode mask
121  *
122  *      The Marvell bridge chips used on the HighPoint SATA cards do not seem
123  *      to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes...
124  */
125 static unsigned long hpt372n_filter(struct ata_device *adev, unsigned long mask)
126 {
127         if (ata_id_is_sata(adev->id))
128                 mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA);
129 
130         return mask;
131 }
132 
133 /**
134  *      hpt3x2n_cable_detect    -       Detect the cable type
135  *      @ap: ATA port to detect on
136  *
137  *      Return the cable type attached to this port
138  */
139 
140 static int hpt3x2n_cable_detect(struct ata_port *ap)
141 {
142         u8 scr2, ata66;
143         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
144 
145         pci_read_config_byte(pdev, 0x5B, &scr2);
146         pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01);
147 
148         udelay(10); /* debounce */
149 
150         /* Cable register now active */
151         pci_read_config_byte(pdev, 0x5A, &ata66);
152         /* Restore state */
153         pci_write_config_byte(pdev, 0x5B, scr2);
154 
155         if (ata66 & (2 >> ap->port_no))
156                 return ATA_CBL_PATA40;
157         else
158                 return ATA_CBL_PATA80;
159 }
160 
161 /**
162  *      hpt3x2n_pre_reset       -       reset the hpt3x2n bus
163  *      @link: ATA link to reset
164  *      @deadline: deadline jiffies for the operation
165  *
166  *      Perform the initial reset handling for the 3x2n series controllers.
167  *      Reset the hardware and state machine,
168  */
169 
170 static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline)
171 {
172         struct ata_port *ap = link->ap;
173         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
174 
175         /* Reset the state machine */
176         pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37);
177         udelay(100);
178 
179         return ata_sff_prereset(link, deadline);
180 }
181 
182 static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev,
183                              u8 mode)
184 {
185         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
186         u32 addr1, addr2;
187         u32 reg, timing, mask;
188         u8 fast;
189 
190         addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no);
191         addr2 = 0x51 + 4 * ap->port_no;
192 
193         /* Fast interrupt prediction disable, hold off interrupt disable */
194         pci_read_config_byte(pdev, addr2, &fast);
195         fast &= ~0x07;
196         pci_write_config_byte(pdev, addr2, fast);
197 
198         /* Determine timing mask and find matching mode entry */
199         if (mode < XFER_MW_DMA_0)
200                 mask = 0xcfc3ffff;
201         else if (mode < XFER_UDMA_0)
202                 mask = 0x31c001ff;
203         else
204                 mask = 0x303c0000;
205 
206         timing = hpt3x2n_find_mode(ap, mode);
207 
208         pci_read_config_dword(pdev, addr1, &reg);
209         reg = (reg & ~mask) | (timing & mask);
210         pci_write_config_dword(pdev, addr1, reg);
211 }
212 
213 /**
214  *      hpt3x2n_set_piomode             -       PIO setup
215  *      @ap: ATA interface
216  *      @adev: device on the interface
217  *
218  *      Perform PIO mode setup.
219  */
220 
221 static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev)
222 {
223         hpt3x2n_set_mode(ap, adev, adev->pio_mode);
224 }
225 
226 /**
227  *      hpt3x2n_set_dmamode             -       DMA timing setup
228  *      @ap: ATA interface
229  *      @adev: Device being configured
230  *
231  *      Set up the channel for MWDMA or UDMA modes.
232  */
233 
234 static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev)
235 {
236         hpt3x2n_set_mode(ap, adev, adev->dma_mode);
237 }
238 
239 /**
240  *      hpt3x2n_bmdma_end               -       DMA engine stop
241  *      @qc: ATA command
242  *
243  *      Clean up after the HPT3x2n and later DMA engine
244  */
245 
246 static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc)
247 {
248         struct ata_port *ap = qc->ap;
249         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
250         int mscreg = 0x50 + 2 * ap->port_no;
251         u8 bwsr_stat, msc_stat;
252 
253         pci_read_config_byte(pdev, 0x6A, &bwsr_stat);
254         pci_read_config_byte(pdev, mscreg, &msc_stat);
255         if (bwsr_stat & (1 << ap->port_no))
256                 pci_write_config_byte(pdev, mscreg, msc_stat | 0x30);
257         ata_bmdma_stop(qc);
258 }
259 
260 /**
261  *      hpt3x2n_set_clock       -       clock control
262  *      @ap: ATA port
263  *      @source: 0x21 or 0x23 for PLL or PCI sourced clock
264  *
265  *      Switch the ATA bus clock between the PLL and PCI clock sources
266  *      while correctly isolating the bus and resetting internal logic
267  *
268  *      We must use the DPLL for
269  *      -       writing
270  *      -       second channel UDMA7 (SATA ports) or higher
271  *      -       66MHz PCI
272  *
273  *      or we will underclock the device and get reduced performance.
274  */
275 
276 static void hpt3x2n_set_clock(struct ata_port *ap, int source)
277 {
278         void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8;
279 
280         /* Tristate the bus */
281         iowrite8(0x80, bmdma+0x73);
282         iowrite8(0x80, bmdma+0x77);
283 
284         /* Switch clock and reset channels */
285         iowrite8(source, bmdma+0x7B);
286         iowrite8(0xC0, bmdma+0x79);
287 
288         /* Reset state machines, avoid enabling the disabled channels */
289         iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70);
290         iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74);
291 
292         /* Complete reset */
293         iowrite8(0x00, bmdma+0x79);
294 
295         /* Reconnect channels to bus */
296         iowrite8(0x00, bmdma+0x73);
297         iowrite8(0x00, bmdma+0x77);
298 }
299 
300 static int hpt3x2n_use_dpll(struct ata_port *ap, int writing)
301 {
302         long flags = (long)ap->host->private_data;
303 
304         /* See if we should use the DPLL */
305         if (writing)
306                 return USE_DPLL;        /* Needed for write */
307         if (flags & PCI66)
308                 return USE_DPLL;        /* Needed at 66Mhz */
309         return 0;
310 }
311 
312 static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc)
313 {
314         struct ata_port *ap = qc->ap;
315         struct ata_port *alt = ap->host->ports[ap->port_no ^ 1];
316         int rc, flags = (long)ap->host->private_data;
317         int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
318 
319         /* First apply the usual rules */
320         rc = ata_std_qc_defer(qc);
321         if (rc != 0)
322                 return rc;
323 
324         if ((flags & USE_DPLL) != dpll && alt->qc_active)
325                 return ATA_DEFER_PORT;
326         return 0;
327 }
328 
329 static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc)
330 {
331         struct ata_port *ap = qc->ap;
332         int flags = (long)ap->host->private_data;
333         int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE);
334 
335         if ((flags & USE_DPLL) != dpll) {
336                 flags &= ~USE_DPLL;
337                 flags |= dpll;
338                 ap->host->private_data = (void *)(long)flags;
339 
340                 hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23);
341         }
342         return ata_bmdma_qc_issue(qc);
343 }
344 
345 static struct scsi_host_template hpt3x2n_sht = {
346         ATA_BMDMA_SHT(DRV_NAME),
347 };
348 
349 /*
350  *      Configuration for HPT302N/371N.
351  */
352 
353 static struct ata_port_operations hpt3xxn_port_ops = {
354         .inherits       = &ata_bmdma_port_ops,
355 
356         .bmdma_stop     = hpt3x2n_bmdma_stop,
357 
358         .qc_defer       = hpt3x2n_qc_defer,
359         .qc_issue       = hpt3x2n_qc_issue,
360 
361         .cable_detect   = hpt3x2n_cable_detect,
362         .set_piomode    = hpt3x2n_set_piomode,
363         .set_dmamode    = hpt3x2n_set_dmamode,
364         .prereset       = hpt3x2n_pre_reset,
365 };
366 
367 /*
368  *      Configuration for HPT372N. Same as 302N/371N but we have a mode filter.
369  */
370 
371 static struct ata_port_operations hpt372n_port_ops = {
372         .inherits       = &hpt3xxn_port_ops,
373         .mode_filter    = &hpt372n_filter,
374 };
375 
376 /**
377  *      hpt3xn_calibrate_dpll           -       Calibrate the DPLL loop
378  *      @dev: PCI device
379  *
380  *      Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this
381  *      succeeds
382  */
383 
384 static int hpt3xn_calibrate_dpll(struct pci_dev *dev)
385 {
386         u8 reg5b;
387         u32 reg5c;
388         int tries;
389 
390         for (tries = 0; tries < 0x5000; tries++) {
391                 udelay(50);
392                 pci_read_config_byte(dev, 0x5b, &reg5b);
393                 if (reg5b & 0x80) {
394                         /* See if it stays set */
395                         for (tries = 0; tries < 0x1000; tries++) {
396                                 pci_read_config_byte(dev, 0x5b, &reg5b);
397                                 /* Failed ? */
398                                 if ((reg5b & 0x80) == 0)
399                                         return 0;
400                         }
401                         /* Turn off tuning, we have the DPLL set */
402                         pci_read_config_dword(dev, 0x5c, &reg5c);
403                         pci_write_config_dword(dev, 0x5c, reg5c & ~0x100);
404                         return 1;
405                 }
406         }
407         /* Never went stable */
408         return 0;
409 }
410 
411 static int hpt3x2n_pci_clock(struct pci_dev *pdev)
412 {
413         unsigned long freq;
414         u32 fcnt;
415         unsigned long iobase = pci_resource_start(pdev, 4);
416 
417         fcnt = inl(iobase + 0x90);      /* Not PCI readable for some chips */
418         if ((fcnt >> 12) != 0xABCDE) {
419                 int i;
420                 u16 sr;
421                 u32 total = 0;
422 
423                 pr_warn("BIOS clock data not set\n");
424 
425                 /* This is the process the HPT371 BIOS is reported to use */
426                 for (i = 0; i < 128; i++) {
427                         pci_read_config_word(pdev, 0x78, &sr);
428                         total += sr & 0x1FF;
429                         udelay(15);
430                 }
431                 fcnt = total / 128;
432         }
433         fcnt &= 0x1FF;
434 
435         freq = (fcnt * 77) / 192;
436 
437         /* Clamp to bands */
438         if (freq < 40)
439                 return 33;
440         if (freq < 45)
441                 return 40;
442         if (freq < 55)
443                 return 50;
444         return 66;
445 }
446 
447 /**
448  *      hpt3x2n_init_one                -       Initialise an HPT37X/302
449  *      @dev: PCI device
450  *      @id: Entry in match table
451  *
452  *      Initialise an HPT3x2n device. There are some interesting complications
453  *      here. Firstly the chip may report 366 and be one of several variants.
454  *      Secondly all the timings depend on the clock for the chip which we must
455  *      detect and look up
456  *
457  *      This is the known chip mappings. It may be missing a couple of later
458  *      releases.
459  *
460  *      Chip version            PCI             Rev     Notes
461  *      HPT372                  4 (HPT366)      5       Other driver
462  *      HPT372N                 4 (HPT366)      6       UDMA133
463  *      HPT372                  5 (HPT372)      1       Other driver
464  *      HPT372N                 5 (HPT372)      2       UDMA133
465  *      HPT302                  6 (HPT302)      *       Other driver
466  *      HPT302N                 6 (HPT302)      > 1     UDMA133
467  *      HPT371                  7 (HPT371)      *       Other driver
468  *      HPT371N                 7 (HPT371)      > 1     UDMA133
469  *      HPT374                  8 (HPT374)      *       Other driver
470  *      HPT372N                 9 (HPT372N)     *       UDMA133
471  *
472  *      (1) UDMA133 support depends on the bus clock
473  */
474 
475 static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id)
476 {
477         /* HPT372N - UDMA133 */
478         static const struct ata_port_info info_hpt372n = {
479                 .flags = ATA_FLAG_SLAVE_POSS,
480                 .pio_mask = ATA_PIO4,
481                 .mwdma_mask = ATA_MWDMA2,
482                 .udma_mask = ATA_UDMA6,
483                 .port_ops = &hpt372n_port_ops
484         };
485         /* HPT302N and HPT371N - UDMA133 */
486         static const struct ata_port_info info_hpt3xxn = {
487                 .flags = ATA_FLAG_SLAVE_POSS,
488                 .pio_mask = ATA_PIO4,
489                 .mwdma_mask = ATA_MWDMA2,
490                 .udma_mask = ATA_UDMA6,
491                 .port_ops = &hpt3xxn_port_ops
492         };
493         const struct ata_port_info *ppi[] = { &info_hpt3xxn, NULL };
494         u8 rev = dev->revision;
495         u8 irqmask;
496         unsigned int pci_mhz;
497         unsigned int f_low, f_high;
498         int adjust;
499         unsigned long iobase = pci_resource_start(dev, 4);
500         void *hpriv = (void *)USE_DPLL;
501         int rc;
502 
503         rc = pcim_enable_device(dev);
504         if (rc)
505                 return rc;
506 
507         switch (dev->device) {
508         case PCI_DEVICE_ID_TTI_HPT366:
509                 /* 372N if rev >= 6 */
510                 if (rev < 6)
511                         return -ENODEV;
512                 goto hpt372n;
513         case PCI_DEVICE_ID_TTI_HPT371:
514                 /* 371N if rev >= 2 */
515                 if (rev < 2)
516                         return -ENODEV;
517                 break;
518         case PCI_DEVICE_ID_TTI_HPT372:
519                 /* 372N if rev >= 2 */
520                 if (rev < 2)
521                         return -ENODEV;
522                 goto hpt372n;
523         case PCI_DEVICE_ID_TTI_HPT302:
524                 /* 302N if rev >= 2 */
525                 if (rev < 2)
526                         return -ENODEV;
527                 break;
528         case PCI_DEVICE_ID_TTI_HPT372N:
529 hpt372n:
530                 ppi[0] = &info_hpt372n;
531                 break;
532         default:
533                 pr_err("PCI table is bogus, please report (%d)\n", dev->device);
534                 return -ENODEV;
535         }
536 
537         /* Ok so this is a chip we support */
538 
539         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
540         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
541         pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
542         pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
543 
544         pci_read_config_byte(dev, 0x5A, &irqmask);
545         irqmask &= ~0x10;
546         pci_write_config_byte(dev, 0x5a, irqmask);
547 
548         /*
549          * HPT371 chips physically have only one channel, the secondary one,
550          * but the primary channel registers do exist!  Go figure...
551          * So,  we manually disable the non-existing channel here
552          * (if the BIOS hasn't done this already).
553          */
554         if (dev->device == PCI_DEVICE_ID_TTI_HPT371) {
555                 u8 mcr1;
556                 pci_read_config_byte(dev, 0x50, &mcr1);
557                 mcr1 &= ~0x04;
558                 pci_write_config_byte(dev, 0x50, mcr1);
559         }
560 
561         /*
562          * Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or
563          * 50 for UDMA100. Right now we always use 66
564          */
565 
566         pci_mhz = hpt3x2n_pci_clock(dev);
567 
568         f_low = (pci_mhz * 48) / 66;    /* PCI Mhz for 66Mhz DPLL */
569         f_high = f_low + 2;             /* Tolerance */
570 
571         pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100);
572         /* PLL clock */
573         pci_write_config_byte(dev, 0x5B, 0x21);
574 
575         /* Unlike the 37x we don't try jiggling the frequency */
576         for (adjust = 0; adjust < 8; adjust++) {
577                 if (hpt3xn_calibrate_dpll(dev))
578                         break;
579                 pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low);
580         }
581         if (adjust == 8) {
582                 pr_err("DPLL did not stabilize!\n");
583                 return -ENODEV;
584         }
585 
586         pr_info("bus clock %dMHz, using 66MHz DPLL\n", pci_mhz);
587 
588         /*
589          * Set our private data up. We only need a few flags
590          * so we use it directly.
591          */
592         if (pci_mhz > 60)
593                 hpriv = (void *)(PCI66 | USE_DPLL);
594 
595         /*
596          * On  HPT371N, if ATA clock is 66 MHz we must set bit 2 in
597          * the MISC. register to stretch the UltraDMA Tss timing.
598          * NOTE: This register is only writeable via I/O space.
599          */
600         if (dev->device == PCI_DEVICE_ID_TTI_HPT371)
601                 outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c);
602 
603         /* Now kick off ATA set up */
604         return ata_pci_bmdma_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0);
605 }
606 
607 static const struct pci_device_id hpt3x2n[] = {
608         { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
609         { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), },
610         { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), },
611         { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), },
612         { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), },
613 
614         { },
615 };
616 
617 static struct pci_driver hpt3x2n_pci_driver = {
618         .name           = DRV_NAME,
619         .id_table       = hpt3x2n,
620         .probe          = hpt3x2n_init_one,
621         .remove         = ata_pci_remove_one
622 };
623 
624 module_pci_driver(hpt3x2n_pci_driver);
625 
626 MODULE_AUTHOR("Alan Cox");
627 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3xxN");
628 MODULE_LICENSE("GPL");
629 MODULE_DEVICE_TABLE(pci, hpt3x2n);
630 MODULE_VERSION(DRV_VERSION);
631 

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