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Linux/drivers/ata/pata_hpt366.c

  1 /*
  2  * Libata driver for the highpoint 366 and 368 UDMA66 ATA controllers.
  3  *
  4  * This driver is heavily based upon:
  5  *
  6  * linux/drivers/ide/pci/hpt366.c               Version 0.36    April 25, 2003
  7  *
  8  * Copyright (C) 1999-2003              Andre Hedrick <andre@linux-ide.org>
  9  * Portions Copyright (C) 2001          Sun Microsystems, Inc.
 10  * Portions Copyright (C) 2003          Red Hat Inc
 11  *
 12  *
 13  * TODO
 14  *      Look into engine reset on timeout errors. Should not be required.
 15  */
 16 
 17 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
 18 
 19 #include <linux/kernel.h>
 20 #include <linux/module.h>
 21 #include <linux/pci.h>
 22 #include <linux/blkdev.h>
 23 #include <linux/delay.h>
 24 #include <scsi/scsi_host.h>
 25 #include <linux/libata.h>
 26 
 27 #define DRV_NAME        "pata_hpt366"
 28 #define DRV_VERSION     "0.6.11"
 29 
 30 struct hpt_clock {
 31         u8      xfer_mode;
 32         u32     timing;
 33 };
 34 
 35 /* key for bus clock timings
 36  * bit
 37  * 0:3    data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA.
 38  *        cycles = value + 1
 39  * 4:7    data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA.
 40  *        cycles = value + 1
 41  * 8:11   cmd_high_time. Inactive time of DIOW_/DIOR_ during task file
 42  *        register access.
 43  * 12:15  cmd_low_time. Active time of DIOW_/DIOR_ during task file
 44  *        register access.
 45  * 16:18  udma_cycle_time. Clock cycles for UDMA xfer?
 46  * 19:21  pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer.
 47  * 22:24  cmd_pre_high_time. Time to initialize 1st PIO cycle for task file
 48  *        register access.
 49  * 28     UDMA enable.
 50  * 29     DMA  enable.
 51  * 30     PIO_MST enable. If set, the chip is in bus master mode during
 52  *        PIO xfer.
 53  * 31     FIFO enable.
 54  */
 55 
 56 static const struct hpt_clock hpt366_40[] = {
 57         {       XFER_UDMA_4,    0x900fd943      },
 58         {       XFER_UDMA_3,    0x900ad943      },
 59         {       XFER_UDMA_2,    0x900bd943      },
 60         {       XFER_UDMA_1,    0x9008d943      },
 61         {       XFER_UDMA_0,    0x9008d943      },
 62 
 63         {       XFER_MW_DMA_2,  0xa008d943      },
 64         {       XFER_MW_DMA_1,  0xa010d955      },
 65         {       XFER_MW_DMA_0,  0xa010d9fc      },
 66 
 67         {       XFER_PIO_4,     0xc008d963      },
 68         {       XFER_PIO_3,     0xc010d974      },
 69         {       XFER_PIO_2,     0xc010d997      },
 70         {       XFER_PIO_1,     0xc010d9c7      },
 71         {       XFER_PIO_0,     0xc018d9d9      },
 72         {       0,              0x0120d9d9      }
 73 };
 74 
 75 static const struct hpt_clock hpt366_33[] = {
 76         {       XFER_UDMA_4,    0x90c9a731      },
 77         {       XFER_UDMA_3,    0x90cfa731      },
 78         {       XFER_UDMA_2,    0x90caa731      },
 79         {       XFER_UDMA_1,    0x90cba731      },
 80         {       XFER_UDMA_0,    0x90c8a731      },
 81 
 82         {       XFER_MW_DMA_2,  0xa0c8a731      },
 83         {       XFER_MW_DMA_1,  0xa0c8a732      },      /* 0xa0c8a733 */
 84         {       XFER_MW_DMA_0,  0xa0c8a797      },
 85 
 86         {       XFER_PIO_4,     0xc0c8a731      },
 87         {       XFER_PIO_3,     0xc0c8a742      },
 88         {       XFER_PIO_2,     0xc0d0a753      },
 89         {       XFER_PIO_1,     0xc0d0a7a3      },      /* 0xc0d0a793 */
 90         {       XFER_PIO_0,     0xc0d0a7aa      },      /* 0xc0d0a7a7 */
 91         {       0,              0x0120a7a7      }
 92 };
 93 
 94 static const struct hpt_clock hpt366_25[] = {
 95         {       XFER_UDMA_4,    0x90c98521      },
 96         {       XFER_UDMA_3,    0x90cf8521      },
 97         {       XFER_UDMA_2,    0x90cf8521      },
 98         {       XFER_UDMA_1,    0x90cb8521      },
 99         {       XFER_UDMA_0,    0x90cb8521      },
100 
101         {       XFER_MW_DMA_2,  0xa0ca8521      },
102         {       XFER_MW_DMA_1,  0xa0ca8532      },
103         {       XFER_MW_DMA_0,  0xa0ca8575      },
104 
105         {       XFER_PIO_4,     0xc0ca8521      },
106         {       XFER_PIO_3,     0xc0ca8532      },
107         {       XFER_PIO_2,     0xc0ca8542      },
108         {       XFER_PIO_1,     0xc0d08572      },
109         {       XFER_PIO_0,     0xc0d08585      },
110         {       0,              0x01208585      }
111 };
112 
113 /**
114  *      hpt36x_find_mode        -       find the hpt36x timing
115  *      @ap: ATA port
116  *      @speed: transfer mode
117  *
118  *      Return the 32bit register programming information for this channel
119  *      that matches the speed provided.
120  */
121 
122 static u32 hpt36x_find_mode(struct ata_port *ap, int speed)
123 {
124         struct hpt_clock *clocks = ap->host->private_data;
125 
126         while (clocks->xfer_mode) {
127                 if (clocks->xfer_mode == speed)
128                         return clocks->timing;
129                 clocks++;
130         }
131         BUG();
132         return 0xffffffffU;     /* silence compiler warning */
133 }
134 
135 static const char * const bad_ata33[] = {
136         "Maxtor 92720U8", "Maxtor 92040U6", "Maxtor 91360U4", "Maxtor 91020U3",
137         "Maxtor 90845U3", "Maxtor 90650U2",
138         "Maxtor 91360D8", "Maxtor 91190D7", "Maxtor 91020D6", "Maxtor 90845D5",
139         "Maxtor 90680D4", "Maxtor 90510D3", "Maxtor 90340D2",
140         "Maxtor 91152D8", "Maxtor 91008D7", "Maxtor 90845D6", "Maxtor 90840D6",
141         "Maxtor 90720D5", "Maxtor 90648D5", "Maxtor 90576D4",
142         "Maxtor 90510D4",
143         "Maxtor 90432D3", "Maxtor 90288D2", "Maxtor 90256D2",
144         "Maxtor 91000D8", "Maxtor 90910D8", "Maxtor 90875D7", "Maxtor 90840D7",
145         "Maxtor 90750D6", "Maxtor 90625D5", "Maxtor 90500D4",
146         "Maxtor 91728D8", "Maxtor 91512D7", "Maxtor 91303D6", "Maxtor 91080D5",
147         "Maxtor 90845D4", "Maxtor 90680D4", "Maxtor 90648D3", "Maxtor 90432D2",
148         NULL
149 };
150 
151 static const char * const bad_ata66_4[] = {
152         "IBM-DTLA-307075",
153         "IBM-DTLA-307060",
154         "IBM-DTLA-307045",
155         "IBM-DTLA-307030",
156         "IBM-DTLA-307020",
157         "IBM-DTLA-307015",
158         "IBM-DTLA-305040",
159         "IBM-DTLA-305030",
160         "IBM-DTLA-305020",
161         "IC35L010AVER07-0",
162         "IC35L020AVER07-0",
163         "IC35L030AVER07-0",
164         "IC35L040AVER07-0",
165         "IC35L060AVER07-0",
166         "WDC AC310200R",
167         NULL
168 };
169 
170 static const char * const bad_ata66_3[] = {
171         "WDC AC310200R",
172         NULL
173 };
174 
175 static int hpt_dma_blacklisted(const struct ata_device *dev, char *modestr,
176                                const char * const list[])
177 {
178         unsigned char model_num[ATA_ID_PROD_LEN + 1];
179         int i = 0;
180 
181         ata_id_c_string(dev->id, model_num, ATA_ID_PROD, sizeof(model_num));
182 
183         while (list[i] != NULL) {
184                 if (!strcmp(list[i], model_num)) {
185                         pr_warn("%s is not supported for %s\n",
186                                 modestr, list[i]);
187                         return 1;
188                 }
189                 i++;
190         }
191         return 0;
192 }
193 
194 /**
195  *      hpt366_filter   -       mode selection filter
196  *      @adev: ATA device
197  *
198  *      Block UDMA on devices that cause trouble with this controller.
199  */
200 
201 static unsigned long hpt366_filter(struct ata_device *adev, unsigned long mask)
202 {
203         if (adev->class == ATA_DEV_ATA) {
204                 if (hpt_dma_blacklisted(adev, "UDMA",  bad_ata33))
205                         mask &= ~ATA_MASK_UDMA;
206                 if (hpt_dma_blacklisted(adev, "UDMA3", bad_ata66_3))
207                         mask &= ~(0xF8 << ATA_SHIFT_UDMA);
208                 if (hpt_dma_blacklisted(adev, "UDMA4", bad_ata66_4))
209                         mask &= ~(0xF0 << ATA_SHIFT_UDMA);
210         } else if (adev->class == ATA_DEV_ATAPI)
211                 mask &= ~(ATA_MASK_MWDMA | ATA_MASK_UDMA);
212 
213         return mask;
214 }
215 
216 static int hpt36x_cable_detect(struct ata_port *ap)
217 {
218         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
219         u8 ata66;
220 
221         /*
222          * Each channel of pata_hpt366 occupies separate PCI function
223          * as the primary channel and bit1 indicates the cable type.
224          */
225         pci_read_config_byte(pdev, 0x5A, &ata66);
226         if (ata66 & 2)
227                 return ATA_CBL_PATA40;
228         return ATA_CBL_PATA80;
229 }
230 
231 static void hpt366_set_mode(struct ata_port *ap, struct ata_device *adev,
232                             u8 mode)
233 {
234         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
235         u32 addr = 0x40 + 4 * adev->devno;
236         u32 mask, reg, t;
237 
238         /* determine timing mask and find matching clock entry */
239         if (mode < XFER_MW_DMA_0)
240                 mask = 0xc1f8ffff;
241         else if (mode < XFER_UDMA_0)
242                 mask = 0x303800ff;
243         else
244                 mask = 0x30070000;
245 
246         t = hpt36x_find_mode(ap, mode);
247 
248         /*
249          * Combine new mode bits with old config bits and disable
250          * on-chip PIO FIFO/buffer (and PIO MST mode as well) to avoid
251          * problems handling I/O errors later.
252          */
253         pci_read_config_dword(pdev, addr, &reg);
254         reg = ((reg & ~mask) | (t & mask)) & ~0xc0000000;
255         pci_write_config_dword(pdev, addr, reg);
256 }
257 
258 /**
259  *      hpt366_set_piomode              -       PIO setup
260  *      @ap: ATA interface
261  *      @adev: device on the interface
262  *
263  *      Perform PIO mode setup.
264  */
265 
266 static void hpt366_set_piomode(struct ata_port *ap, struct ata_device *adev)
267 {
268         hpt366_set_mode(ap, adev, adev->pio_mode);
269 }
270 
271 /**
272  *      hpt366_set_dmamode              -       DMA timing setup
273  *      @ap: ATA interface
274  *      @adev: Device being configured
275  *
276  *      Set up the channel for MWDMA or UDMA modes. Much the same as with
277  *      PIO, load the mode number and then set MWDMA or UDMA flag.
278  */
279 
280 static void hpt366_set_dmamode(struct ata_port *ap, struct ata_device *adev)
281 {
282         hpt366_set_mode(ap, adev, adev->dma_mode);
283 }
284 
285 static struct scsi_host_template hpt36x_sht = {
286         ATA_BMDMA_SHT(DRV_NAME),
287 };
288 
289 /*
290  *      Configuration for HPT366/68
291  */
292 
293 static struct ata_port_operations hpt366_port_ops = {
294         .inherits       = &ata_bmdma_port_ops,
295         .cable_detect   = hpt36x_cable_detect,
296         .mode_filter    = hpt366_filter,
297         .set_piomode    = hpt366_set_piomode,
298         .set_dmamode    = hpt366_set_dmamode,
299 };
300 
301 /**
302  *      hpt36x_init_chipset     -       common chip setup
303  *      @dev: PCI device
304  *
305  *      Perform the chip setup work that must be done at both init and
306  *      resume time
307  */
308 
309 static void hpt36x_init_chipset(struct pci_dev *dev)
310 {
311         u8 drive_fast;
312 
313         pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4));
314         pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78);
315         pci_write_config_byte(dev, PCI_MIN_GNT, 0x08);
316         pci_write_config_byte(dev, PCI_MAX_LAT, 0x08);
317 
318         pci_read_config_byte(dev, 0x51, &drive_fast);
319         if (drive_fast & 0x80)
320                 pci_write_config_byte(dev, 0x51, drive_fast & ~0x80);
321 }
322 
323 /**
324  *      hpt36x_init_one         -       Initialise an HPT366/368
325  *      @dev: PCI device
326  *      @id: Entry in match table
327  *
328  *      Initialise an HPT36x device. There are some interesting complications
329  *      here. Firstly the chip may report 366 and be one of several variants.
330  *      Secondly all the timings depend on the clock for the chip which we must
331  *      detect and look up
332  *
333  *      This is the known chip mappings. It may be missing a couple of later
334  *      releases.
335  *
336  *      Chip version            PCI             Rev     Notes
337  *      HPT366                  4 (HPT366)      0       UDMA66
338  *      HPT366                  4 (HPT366)      1       UDMA66
339  *      HPT368                  4 (HPT366)      2       UDMA66
340  *      HPT37x/30x              4 (HPT366)      3+      Other driver
341  *
342  */
343 
344 static int hpt36x_init_one(struct pci_dev *dev, const struct pci_device_id *id)
345 {
346         static const struct ata_port_info info_hpt366 = {
347                 .flags = ATA_FLAG_SLAVE_POSS,
348                 .pio_mask = ATA_PIO4,
349                 .mwdma_mask = ATA_MWDMA2,
350                 .udma_mask = ATA_UDMA4,
351                 .port_ops = &hpt366_port_ops
352         };
353         const struct ata_port_info *ppi[] = { &info_hpt366, NULL };
354 
355         void *hpriv = NULL;
356         u32 reg1;
357         int rc;
358 
359         rc = pcim_enable_device(dev);
360         if (rc)
361                 return rc;
362 
363         /* May be a later chip in disguise. Check */
364         /* Newer chips are not in the HPT36x driver. Ignore them */
365         if (dev->revision > 2)
366                 return -ENODEV;
367 
368         hpt36x_init_chipset(dev);
369 
370         pci_read_config_dword(dev, 0x40,  &reg1);
371 
372         /* PCI clocking determines the ATA timing values to use */
373         /* info_hpt366 is safe against re-entry so we can scribble on it */
374         switch ((reg1 & 0x700) >> 8) {
375         case 9:
376                 hpriv = &hpt366_40;
377                 break;
378         case 5:
379                 hpriv = &hpt366_25;
380                 break;
381         default:
382                 hpriv = &hpt366_33;
383                 break;
384         }
385         /* Now kick off ATA set up */
386         return ata_pci_bmdma_init_one(dev, ppi, &hpt36x_sht, hpriv, 0);
387 }
388 
389 #ifdef CONFIG_PM_SLEEP
390 static int hpt36x_reinit_one(struct pci_dev *dev)
391 {
392         struct ata_host *host = pci_get_drvdata(dev);
393         int rc;
394 
395         rc = ata_pci_device_do_resume(dev);
396         if (rc)
397                 return rc;
398         hpt36x_init_chipset(dev);
399         ata_host_resume(host);
400         return 0;
401 }
402 #endif
403 
404 static const struct pci_device_id hpt36x[] = {
405         { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), },
406         { },
407 };
408 
409 static struct pci_driver hpt36x_pci_driver = {
410         .name           = DRV_NAME,
411         .id_table       = hpt36x,
412         .probe          = hpt36x_init_one,
413         .remove         = ata_pci_remove_one,
414 #ifdef CONFIG_PM_SLEEP
415         .suspend        = ata_pci_device_suspend,
416         .resume         = hpt36x_reinit_one,
417 #endif
418 };
419 
420 module_pci_driver(hpt36x_pci_driver);
421 
422 MODULE_AUTHOR("Alan Cox");
423 MODULE_DESCRIPTION("low-level driver for the Highpoint HPT366/368");
424 MODULE_LICENSE("GPL");
425 MODULE_DEVICE_TABLE(pci, hpt36x);
426 MODULE_VERSION(DRV_VERSION);
427 

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