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Linux/drivers/ata/pata_atiixp.c

  1 /*
  2  * pata_atiixp.c        - ATI PATA for new ATA layer
  3  *                        (C) 2005 Red Hat Inc
  4  *                        (C) 2009-2010 Bartlomiej Zolnierkiewicz
  5  *
  6  * Based on
  7  *
  8  *  linux/drivers/ide/pci/atiixp.c      Version 0.01-bart2      Feb. 26, 2004
  9  *
 10  *  Copyright (C) 2003 ATI Inc. <hyu@ati.com>
 11  *  Copyright (C) 2004 Bartlomiej Zolnierkiewicz
 12  *
 13  */
 14 
 15 #include <linux/kernel.h>
 16 #include <linux/module.h>
 17 #include <linux/pci.h>
 18 #include <linux/init.h>
 19 #include <linux/blkdev.h>
 20 #include <linux/delay.h>
 21 #include <scsi/scsi_host.h>
 22 #include <linux/libata.h>
 23 #include <linux/dmi.h>
 24 
 25 #define DRV_NAME "pata_atiixp"
 26 #define DRV_VERSION "0.4.6"
 27 
 28 enum {
 29         ATIIXP_IDE_PIO_TIMING   = 0x40,
 30         ATIIXP_IDE_MWDMA_TIMING = 0x44,
 31         ATIIXP_IDE_PIO_CONTROL  = 0x48,
 32         ATIIXP_IDE_PIO_MODE     = 0x4a,
 33         ATIIXP_IDE_UDMA_CONTROL = 0x54,
 34         ATIIXP_IDE_UDMA_MODE    = 0x56
 35 };
 36 
 37 static const struct dmi_system_id attixp_cable_override_dmi_table[] = {
 38         {
 39                 /* Board has onboard PATA<->SATA converters */
 40                 .ident = "MSI E350DM-E33",
 41                 .matches = {
 42                         DMI_MATCH(DMI_BOARD_VENDOR, "MSI"),
 43                         DMI_MATCH(DMI_BOARD_NAME, "E350DM-E33(MS-7720)"),
 44                 },
 45         },
 46         { }
 47 };
 48 
 49 static int atiixp_cable_detect(struct ata_port *ap)
 50 {
 51         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 52         u8 udma;
 53 
 54         if (dmi_check_system(attixp_cable_override_dmi_table))
 55                 return ATA_CBL_PATA40_SHORT;
 56 
 57         /* Hack from drivers/ide/pci. Really we want to know how to do the
 58            raw detection not play follow the bios mode guess */
 59         pci_read_config_byte(pdev, ATIIXP_IDE_UDMA_MODE + ap->port_no, &udma);
 60         if ((udma & 0x07) >= 0x04 || (udma & 0x70) >= 0x40)
 61                 return  ATA_CBL_PATA80;
 62         return ATA_CBL_PATA40;
 63 }
 64 
 65 static DEFINE_SPINLOCK(atiixp_lock);
 66 
 67 /**
 68  *      atiixp_prereset -       perform reset handling
 69  *      @link: ATA link
 70  *      @deadline: deadline jiffies for the operation
 71  *
 72  *      Reset sequence checking enable bits to see which ports are
 73  *      active.
 74  */
 75 
 76 static int atiixp_prereset(struct ata_link *link, unsigned long deadline)
 77 {
 78         static const struct pci_bits atiixp_enable_bits[] = {
 79                 { 0x48, 1, 0x01, 0x00 },
 80                 { 0x48, 1, 0x08, 0x00 }
 81         };
 82 
 83         struct ata_port *ap = link->ap;
 84         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
 85 
 86         if (!pci_test_config_bits(pdev, &atiixp_enable_bits[ap->port_no]))
 87                 return -ENOENT;
 88 
 89         return ata_sff_prereset(link, deadline);
 90 }
 91 
 92 /**
 93  *      atiixp_set_pio_timing   -       set initial PIO mode data
 94  *      @ap: ATA interface
 95  *      @adev: ATA device
 96  *
 97  *      Called by both the pio and dma setup functions to set the controller
 98  *      timings for PIO transfers. We must load both the mode number and
 99  *      timing values into the controller.
100  */
101 
102 static void atiixp_set_pio_timing(struct ata_port *ap, struct ata_device *adev, int pio)
103 {
104         static u8 pio_timings[5] = { 0x5D, 0x47, 0x34, 0x22, 0x20 };
105 
106         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
107         int dn = 2 * ap->port_no + adev->devno;
108         int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
109         u32 pio_timing_data;
110         u16 pio_mode_data;
111 
112         pci_read_config_word(pdev, ATIIXP_IDE_PIO_MODE, &pio_mode_data);
113         pio_mode_data &= ~(0x7 << (4 * dn));
114         pio_mode_data |= pio << (4 * dn);
115         pci_write_config_word(pdev, ATIIXP_IDE_PIO_MODE, pio_mode_data);
116 
117         pci_read_config_dword(pdev, ATIIXP_IDE_PIO_TIMING, &pio_timing_data);
118         pio_timing_data &= ~(0xFF << timing_shift);
119         pio_timing_data |= (pio_timings[pio] << timing_shift);
120         pci_write_config_dword(pdev, ATIIXP_IDE_PIO_TIMING, pio_timing_data);
121 }
122 
123 /**
124  *      atiixp_set_piomode      -       set initial PIO mode data
125  *      @ap: ATA interface
126  *      @adev: ATA device
127  *
128  *      Called to do the PIO mode setup. We use a shared helper for this
129  *      as the DMA setup must also adjust the PIO timing information.
130  */
131 
132 static void atiixp_set_piomode(struct ata_port *ap, struct ata_device *adev)
133 {
134         unsigned long flags;
135         spin_lock_irqsave(&atiixp_lock, flags);
136         atiixp_set_pio_timing(ap, adev, adev->pio_mode - XFER_PIO_0);
137         spin_unlock_irqrestore(&atiixp_lock, flags);
138 }
139 
140 /**
141  *      atiixp_set_dmamode      -       set initial DMA mode data
142  *      @ap: ATA interface
143  *      @adev: ATA device
144  *
145  *      Called to do the DMA mode setup. We use timing tables for most
146  *      modes but must tune an appropriate PIO mode to match.
147  */
148 
149 static void atiixp_set_dmamode(struct ata_port *ap, struct ata_device *adev)
150 {
151         static u8 mwdma_timings[5] = { 0x77, 0x21, 0x20 };
152 
153         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
154         int dma = adev->dma_mode;
155         int dn = 2 * ap->port_no + adev->devno;
156         int wanted_pio;
157         unsigned long flags;
158 
159         spin_lock_irqsave(&atiixp_lock, flags);
160 
161         if (adev->dma_mode >= XFER_UDMA_0) {
162                 u16 udma_mode_data;
163 
164                 dma -= XFER_UDMA_0;
165 
166                 pci_read_config_word(pdev, ATIIXP_IDE_UDMA_MODE, &udma_mode_data);
167                 udma_mode_data &= ~(0x7 << (4 * dn));
168                 udma_mode_data |= dma << (4 * dn);
169                 pci_write_config_word(pdev, ATIIXP_IDE_UDMA_MODE, udma_mode_data);
170         } else {
171                 int timing_shift = (16 * ap->port_no) + 8 * (adev->devno ^ 1);
172                 u32 mwdma_timing_data;
173 
174                 dma -= XFER_MW_DMA_0;
175 
176                 pci_read_config_dword(pdev, ATIIXP_IDE_MWDMA_TIMING,
177                                       &mwdma_timing_data);
178                 mwdma_timing_data &= ~(0xFF << timing_shift);
179                 mwdma_timing_data |= (mwdma_timings[dma] << timing_shift);
180                 pci_write_config_dword(pdev, ATIIXP_IDE_MWDMA_TIMING,
181                                        mwdma_timing_data);
182         }
183         /*
184          *      We must now look at the PIO mode situation. We may need to
185          *      adjust the PIO mode to keep the timings acceptable
186          */
187          if (adev->dma_mode >= XFER_MW_DMA_2)
188                 wanted_pio = 4;
189         else if (adev->dma_mode == XFER_MW_DMA_1)
190                 wanted_pio = 3;
191         else if (adev->dma_mode == XFER_MW_DMA_0)
192                 wanted_pio = 0;
193         else BUG();
194 
195         if (adev->pio_mode != wanted_pio)
196                 atiixp_set_pio_timing(ap, adev, wanted_pio);
197         spin_unlock_irqrestore(&atiixp_lock, flags);
198 }
199 
200 /**
201  *      atiixp_bmdma_start      -       DMA start callback
202  *      @qc: Command in progress
203  *
204  *      When DMA begins we need to ensure that the UDMA control
205  *      register for the channel is correctly set.
206  *
207  *      Note: The host lock held by the libata layer protects
208  *      us from two channels both trying to set DMA bits at once
209  */
210 
211 static void atiixp_bmdma_start(struct ata_queued_cmd *qc)
212 {
213         struct ata_port *ap = qc->ap;
214         struct ata_device *adev = qc->dev;
215 
216         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
217         int dn = (2 * ap->port_no) + adev->devno;
218         u16 tmp16;
219 
220         pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
221         if (ata_using_udma(adev))
222                 tmp16 |= (1 << dn);
223         else
224                 tmp16 &= ~(1 << dn);
225         pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
226         ata_bmdma_start(qc);
227 }
228 
229 /**
230  *      atiixp_dma_stop -       DMA stop callback
231  *      @qc: Command in progress
232  *
233  *      DMA has completed. Clear the UDMA flag as the next operations will
234  *      be PIO ones not UDMA data transfer.
235  *
236  *      Note: The host lock held by the libata layer protects
237  *      us from two channels both trying to set DMA bits at once
238  */
239 
240 static void atiixp_bmdma_stop(struct ata_queued_cmd *qc)
241 {
242         struct ata_port *ap = qc->ap;
243         struct pci_dev *pdev = to_pci_dev(ap->host->dev);
244         int dn = (2 * ap->port_no) + qc->dev->devno;
245         u16 tmp16;
246 
247         pci_read_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, &tmp16);
248         tmp16 &= ~(1 << dn);
249         pci_write_config_word(pdev, ATIIXP_IDE_UDMA_CONTROL, tmp16);
250         ata_bmdma_stop(qc);
251 }
252 
253 static struct scsi_host_template atiixp_sht = {
254         ATA_BMDMA_SHT(DRV_NAME),
255         .sg_tablesize           = LIBATA_DUMB_MAX_PRD,
256 };
257 
258 static struct ata_port_operations atiixp_port_ops = {
259         .inherits       = &ata_bmdma_port_ops,
260 
261         .qc_prep        = ata_bmdma_dumb_qc_prep,
262         .bmdma_start    = atiixp_bmdma_start,
263         .bmdma_stop     = atiixp_bmdma_stop,
264 
265         .prereset       = atiixp_prereset,
266         .cable_detect   = atiixp_cable_detect,
267         .set_piomode    = atiixp_set_piomode,
268         .set_dmamode    = atiixp_set_dmamode,
269 };
270 
271 static int atiixp_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
272 {
273         static const struct ata_port_info info = {
274                 .flags = ATA_FLAG_SLAVE_POSS,
275                 .pio_mask = ATA_PIO4,
276                 .mwdma_mask = ATA_MWDMA12_ONLY,
277                 .udma_mask = ATA_UDMA5,
278                 .port_ops = &atiixp_port_ops
279         };
280         const struct ata_port_info *ppi[] = { &info, &info };
281 
282         return ata_pci_bmdma_init_one(pdev, ppi, &atiixp_sht, NULL,
283                                       ATA_HOST_PARALLEL_SCAN);
284 }
285 
286 static const struct pci_device_id atiixp[] = {
287         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP200_IDE), },
288         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP300_IDE), },
289         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP400_IDE), },
290         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP600_IDE), },
291         { PCI_VDEVICE(ATI, PCI_DEVICE_ID_ATI_IXP700_IDE), },
292         { PCI_VDEVICE(AMD, PCI_DEVICE_ID_AMD_HUDSON2_IDE), },
293 
294         { },
295 };
296 
297 static struct pci_driver atiixp_pci_driver = {
298         .name           = DRV_NAME,
299         .id_table       = atiixp,
300         .probe          = atiixp_init_one,
301         .remove         = ata_pci_remove_one,
302 #ifdef CONFIG_PM
303         .resume         = ata_pci_device_resume,
304         .suspend        = ata_pci_device_suspend,
305 #endif
306 };
307 
308 module_pci_driver(atiixp_pci_driver);
309 
310 MODULE_AUTHOR("Alan Cox");
311 MODULE_DESCRIPTION("low-level driver for ATI IXP200/300/400");
312 MODULE_LICENSE("GPL");
313 MODULE_DEVICE_TABLE(pci, atiixp);
314 MODULE_VERSION(DRV_VERSION);
315 

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