Version:  2.0.40 2.2.26 2.4.37 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19

Linux/drivers/ata/ahci.c

  1 /*
  2  *  ahci.c - AHCI SATA support
  3  *
  4  *  Maintained by:  Tejun Heo <tj@kernel.org>
  5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  6  *                  on emails.
  7  *
  8  *  Copyright 2004-2005 Red Hat, Inc.
  9  *
 10  *
 11  *  This program is free software; you can redistribute it and/or modify
 12  *  it under the terms of the GNU General Public License as published by
 13  *  the Free Software Foundation; either version 2, or (at your option)
 14  *  any later version.
 15  *
 16  *  This program is distributed in the hope that it will be useful,
 17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 19  *  GNU General Public License for more details.
 20  *
 21  *  You should have received a copy of the GNU General Public License
 22  *  along with this program; see the file COPYING.  If not, write to
 23  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 24  *
 25  *
 26  * libata documentation is available via 'make {ps|pdf}docs',
 27  * as Documentation/DocBook/libata.*
 28  *
 29  * AHCI hardware documentation:
 30  * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
 31  * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
 32  *
 33  */
 34 
 35 #include <linux/kernel.h>
 36 #include <linux/module.h>
 37 #include <linux/pci.h>
 38 #include <linux/blkdev.h>
 39 #include <linux/delay.h>
 40 #include <linux/interrupt.h>
 41 #include <linux/dma-mapping.h>
 42 #include <linux/device.h>
 43 #include <linux/dmi.h>
 44 #include <linux/gfp.h>
 45 #include <scsi/scsi_host.h>
 46 #include <scsi/scsi_cmnd.h>
 47 #include <linux/libata.h>
 48 #include "ahci.h"
 49 
 50 #define DRV_NAME        "ahci"
 51 #define DRV_VERSION     "3.0"
 52 
 53 enum {
 54         AHCI_PCI_BAR_STA2X11    = 0,
 55         AHCI_PCI_BAR_ENMOTUS    = 2,
 56         AHCI_PCI_BAR_STANDARD   = 5,
 57 };
 58 
 59 enum board_ids {
 60         /* board IDs by feature in alphabetical order */
 61         board_ahci,
 62         board_ahci_ign_iferr,
 63         board_ahci_nomsi,
 64         board_ahci_noncq,
 65         board_ahci_nosntf,
 66         board_ahci_yes_fbs,
 67 
 68         /* board IDs for specific chipsets in alphabetical order */
 69         board_ahci_mcp65,
 70         board_ahci_mcp77,
 71         board_ahci_mcp89,
 72         board_ahci_mv,
 73         board_ahci_sb600,
 74         board_ahci_sb700,       /* for SB700 and SB800 */
 75         board_ahci_vt8251,
 76 
 77         /* aliases */
 78         board_ahci_mcp_linux    = board_ahci_mcp65,
 79         board_ahci_mcp67        = board_ahci_mcp65,
 80         board_ahci_mcp73        = board_ahci_mcp65,
 81         board_ahci_mcp79        = board_ahci_mcp77,
 82 };
 83 
 84 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
 85 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 86                                  unsigned long deadline);
 87 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
 88 static bool is_mcp89_apple(struct pci_dev *pdev);
 89 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 90                                 unsigned long deadline);
 91 #ifdef CONFIG_PM
 92 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg);
 93 static int ahci_pci_device_resume(struct pci_dev *pdev);
 94 #endif
 95 
 96 static struct scsi_host_template ahci_sht = {
 97         AHCI_SHT("ahci"),
 98 };
 99 
100 static struct ata_port_operations ahci_vt8251_ops = {
101         .inherits               = &ahci_ops,
102         .hardreset              = ahci_vt8251_hardreset,
103 };
104 
105 static struct ata_port_operations ahci_p5wdh_ops = {
106         .inherits               = &ahci_ops,
107         .hardreset              = ahci_p5wdh_hardreset,
108 };
109 
110 static const struct ata_port_info ahci_port_info[] = {
111         /* by features */
112         [board_ahci] = {
113                 .flags          = AHCI_FLAG_COMMON,
114                 .pio_mask       = ATA_PIO4,
115                 .udma_mask      = ATA_UDMA6,
116                 .port_ops       = &ahci_ops,
117         },
118         [board_ahci_ign_iferr] = {
119                 AHCI_HFLAGS     (AHCI_HFLAG_IGN_IRQ_IF_ERR),
120                 .flags          = AHCI_FLAG_COMMON,
121                 .pio_mask       = ATA_PIO4,
122                 .udma_mask      = ATA_UDMA6,
123                 .port_ops       = &ahci_ops,
124         },
125         [board_ahci_nomsi] = {
126                 AHCI_HFLAGS     (AHCI_HFLAG_NO_MSI),
127                 .flags          = AHCI_FLAG_COMMON,
128                 .pio_mask       = ATA_PIO4,
129                 .udma_mask      = ATA_UDMA6,
130                 .port_ops       = &ahci_ops,
131         },
132         [board_ahci_noncq] = {
133                 AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ),
134                 .flags          = AHCI_FLAG_COMMON,
135                 .pio_mask       = ATA_PIO4,
136                 .udma_mask      = ATA_UDMA6,
137                 .port_ops       = &ahci_ops,
138         },
139         [board_ahci_nosntf] = {
140                 AHCI_HFLAGS     (AHCI_HFLAG_NO_SNTF),
141                 .flags          = AHCI_FLAG_COMMON,
142                 .pio_mask       = ATA_PIO4,
143                 .udma_mask      = ATA_UDMA6,
144                 .port_ops       = &ahci_ops,
145         },
146         [board_ahci_yes_fbs] = {
147                 AHCI_HFLAGS     (AHCI_HFLAG_YES_FBS),
148                 .flags          = AHCI_FLAG_COMMON,
149                 .pio_mask       = ATA_PIO4,
150                 .udma_mask      = ATA_UDMA6,
151                 .port_ops       = &ahci_ops,
152         },
153         /* by chipsets */
154         [board_ahci_mcp65] = {
155                 AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
156                                  AHCI_HFLAG_YES_NCQ),
157                 .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
158                 .pio_mask       = ATA_PIO4,
159                 .udma_mask      = ATA_UDMA6,
160                 .port_ops       = &ahci_ops,
161         },
162         [board_ahci_mcp77] = {
163                 AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
164                 .flags          = AHCI_FLAG_COMMON,
165                 .pio_mask       = ATA_PIO4,
166                 .udma_mask      = ATA_UDMA6,
167                 .port_ops       = &ahci_ops,
168         },
169         [board_ahci_mcp89] = {
170                 AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA),
171                 .flags          = AHCI_FLAG_COMMON,
172                 .pio_mask       = ATA_PIO4,
173                 .udma_mask      = ATA_UDMA6,
174                 .port_ops       = &ahci_ops,
175         },
176         [board_ahci_mv] = {
177                 AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
178                                  AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
179                 .flags          = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
180                 .pio_mask       = ATA_PIO4,
181                 .udma_mask      = ATA_UDMA6,
182                 .port_ops       = &ahci_ops,
183         },
184         [board_ahci_sb600] = {
185                 AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL |
186                                  AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
187                                  AHCI_HFLAG_32BIT_ONLY),
188                 .flags          = AHCI_FLAG_COMMON,
189                 .pio_mask       = ATA_PIO4,
190                 .udma_mask      = ATA_UDMA6,
191                 .port_ops       = &ahci_pmp_retry_srst_ops,
192         },
193         [board_ahci_sb700] = {  /* for SB700 and SB800 */
194                 AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL),
195                 .flags          = AHCI_FLAG_COMMON,
196                 .pio_mask       = ATA_PIO4,
197                 .udma_mask      = ATA_UDMA6,
198                 .port_ops       = &ahci_pmp_retry_srst_ops,
199         },
200         [board_ahci_vt8251] = {
201                 AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
202                 .flags          = AHCI_FLAG_COMMON,
203                 .pio_mask       = ATA_PIO4,
204                 .udma_mask      = ATA_UDMA6,
205                 .port_ops       = &ahci_vt8251_ops,
206         },
207 };
208 
209 static const struct pci_device_id ahci_pci_tbl[] = {
210         /* Intel */
211         { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
212         { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
213         { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
214         { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
215         { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
216         { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
217         { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
218         { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
219         { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
220         { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
221         { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
222         { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
223         { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
224         { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
225         { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
226         { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
227         { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
228         { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
229         { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
230         { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
231         { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
232         { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
233         { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
234         { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
235         { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
236         { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
237         { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
238         { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
239         { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
240         { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
241         { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
242         { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
243         { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
244         { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
245         { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
246         { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
247         { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
248         { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
249         { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
250         { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
251         { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
252         { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
253         { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
254         { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
255         { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
256         { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
257         { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
258         { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
259         { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
260         { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
261         { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
262         { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
263         { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
264         { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
265         { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
266         { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
267         { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
268         { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
269         { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
270         { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
271         { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
272         { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
273         { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
274         { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
275         { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
276         { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
277         { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
278         { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
279         { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
280         { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
281         { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
282         { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
283         { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
284         { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
285         { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
286         { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
287         { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
288         { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
289         { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
290         { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
291         { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
292         { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
293         { PCI_VDEVICE(INTEL, 0x1f32), board_ahci }, /* Avoton AHCI */
294         { PCI_VDEVICE(INTEL, 0x1f33), board_ahci }, /* Avoton AHCI */
295         { PCI_VDEVICE(INTEL, 0x1f34), board_ahci }, /* Avoton RAID */
296         { PCI_VDEVICE(INTEL, 0x1f35), board_ahci }, /* Avoton RAID */
297         { PCI_VDEVICE(INTEL, 0x1f36), board_ahci }, /* Avoton RAID */
298         { PCI_VDEVICE(INTEL, 0x1f37), board_ahci }, /* Avoton RAID */
299         { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci }, /* Avoton RAID */
300         { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci }, /* Avoton RAID */
301         { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
302         { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
303         { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
304         { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
305         { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
306         { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
307         { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
308         { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
309         { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
310         { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
311         { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
312         { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
313         { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
314         { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
315         { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
316         { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
317         { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
318         { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
319         { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
320         { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
321         { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
322         { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
323         { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
324         { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
325         { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
326         { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
327         { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
328         { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
329         { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
330         { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
331 
332         /* JMicron 360/1/3/5/6, match class to avoid IDE function */
333         { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
334           PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
335         /* JMicron 362B and 362C have an AHCI function with IDE class code */
336         { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
337         { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
338 
339         /* ATI */
340         { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
341         { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
342         { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
343         { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
344         { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
345         { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
346         { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
347 
348         /* AMD */
349         { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
350         { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
351         /* AMD is using RAID class only for ahci controllers */
352         { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
353           PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
354 
355         /* VIA */
356         { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
357         { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
358 
359         /* NVIDIA */
360         { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },      /* MCP65 */
361         { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },      /* MCP65 */
362         { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },      /* MCP65 */
363         { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },      /* MCP65 */
364         { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },      /* MCP65 */
365         { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },      /* MCP65 */
366         { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },      /* MCP65 */
367         { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },      /* MCP65 */
368         { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },      /* MCP67 */
369         { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },      /* MCP67 */
370         { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },      /* MCP67 */
371         { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },      /* MCP67 */
372         { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },      /* MCP67 */
373         { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },      /* MCP67 */
374         { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },      /* MCP67 */
375         { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },      /* MCP67 */
376         { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },      /* MCP67 */
377         { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },      /* MCP67 */
378         { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },      /* MCP67 */
379         { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },      /* MCP67 */
380         { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },  /* Linux ID */
381         { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },  /* Linux ID */
382         { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },  /* Linux ID */
383         { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },  /* Linux ID */
384         { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },  /* Linux ID */
385         { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },  /* Linux ID */
386         { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },  /* Linux ID */
387         { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },  /* Linux ID */
388         { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },  /* Linux ID */
389         { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },  /* Linux ID */
390         { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },  /* Linux ID */
391         { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },  /* Linux ID */
392         { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },  /* Linux ID */
393         { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },  /* Linux ID */
394         { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },  /* Linux ID */
395         { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },  /* Linux ID */
396         { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },      /* MCP73 */
397         { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },      /* MCP73 */
398         { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },      /* MCP73 */
399         { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },      /* MCP73 */
400         { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },      /* MCP73 */
401         { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },      /* MCP73 */
402         { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },      /* MCP73 */
403         { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },      /* MCP73 */
404         { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },      /* MCP73 */
405         { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },      /* MCP73 */
406         { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },      /* MCP73 */
407         { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },      /* MCP73 */
408         { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },      /* MCP77 */
409         { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },      /* MCP77 */
410         { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },      /* MCP77 */
411         { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },      /* MCP77 */
412         { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },      /* MCP77 */
413         { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },      /* MCP77 */
414         { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },      /* MCP77 */
415         { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },      /* MCP77 */
416         { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },      /* MCP77 */
417         { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },      /* MCP77 */
418         { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },      /* MCP77 */
419         { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },      /* MCP77 */
420         { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },      /* MCP79 */
421         { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },      /* MCP79 */
422         { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },      /* MCP79 */
423         { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },      /* MCP79 */
424         { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },      /* MCP79 */
425         { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },      /* MCP79 */
426         { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },      /* MCP79 */
427         { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },      /* MCP79 */
428         { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },      /* MCP79 */
429         { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },      /* MCP79 */
430         { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },      /* MCP79 */
431         { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },      /* MCP79 */
432         { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },      /* MCP89 */
433         { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },      /* MCP89 */
434         { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },      /* MCP89 */
435         { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },      /* MCP89 */
436         { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },      /* MCP89 */
437         { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },      /* MCP89 */
438         { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },      /* MCP89 */
439         { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },      /* MCP89 */
440         { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },      /* MCP89 */
441         { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },      /* MCP89 */
442         { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },      /* MCP89 */
443         { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },      /* MCP89 */
444 
445         /* SiS */
446         { PCI_VDEVICE(SI, 0x1184), board_ahci },                /* SiS 966 */
447         { PCI_VDEVICE(SI, 0x1185), board_ahci },                /* SiS 968 */
448         { PCI_VDEVICE(SI, 0x0186), board_ahci },                /* SiS 968 */
449 
450         /* ST Microelectronics */
451         { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci },           /* ST ConneXt */
452 
453         /* Marvell */
454         { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },        /* 6145 */
455         { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },        /* 6121 */
456         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
457           .class = PCI_CLASS_STORAGE_SATA_AHCI,
458           .class_mask = 0xffffff,
459           .driver_data = board_ahci_yes_fbs },                  /* 88se9128 */
460         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
461           .driver_data = board_ahci_yes_fbs },                  /* 88se9125 */
462         { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
463                          PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
464           .driver_data = board_ahci_yes_fbs },                  /* 88se9170 */
465         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
466           .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
467         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
468           .driver_data = board_ahci_yes_fbs },                  /* 88se9182 */
469         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
470           .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
471         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
472           .driver_data = board_ahci_yes_fbs },                  /* 88se9172 on some Gigabyte */
473         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
474           .driver_data = board_ahci_yes_fbs },
475         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
476           .driver_data = board_ahci_yes_fbs },
477         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
478           .driver_data = board_ahci_yes_fbs },
479         { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
480           .driver_data = board_ahci_yes_fbs },
481 
482         /* Promise */
483         { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },   /* PDC42819 */
484         { PCI_VDEVICE(PROMISE, 0x3781), board_ahci },   /* FastTrak TX8660 ahci-mode */
485 
486         /* Asmedia */
487         { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci },   /* ASM1060 */
488         { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci },   /* ASM1060 */
489         { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci },   /* ASM1061 */
490         { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci },   /* ASM1062 */
491 
492         /*
493          * Samsung SSDs found on some macbooks.  NCQ times out if MSI is
494          * enabled.  https://bugzilla.kernel.org/show_bug.cgi?id=60731
495          */
496         { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
497         { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
498 
499         /* Enmotus */
500         { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
501 
502         /* Generic, PCI class code for AHCI */
503         { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
504           PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
505 
506         { }     /* terminate list */
507 };
508 
509 
510 static struct pci_driver ahci_pci_driver = {
511         .name                   = DRV_NAME,
512         .id_table               = ahci_pci_tbl,
513         .probe                  = ahci_init_one,
514         .remove                 = ata_pci_remove_one,
515 #ifdef CONFIG_PM
516         .suspend                = ahci_pci_device_suspend,
517         .resume                 = ahci_pci_device_resume,
518 #endif
519 };
520 
521 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
522 static int marvell_enable;
523 #else
524 static int marvell_enable = 1;
525 #endif
526 module_param(marvell_enable, int, 0644);
527 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
528 
529 
530 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
531                                          struct ahci_host_priv *hpriv)
532 {
533         if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
534                 dev_info(&pdev->dev, "JMB361 has only one port\n");
535                 hpriv->force_port_map = 1;
536         }
537 
538         /*
539          * Temporary Marvell 6145 hack: PATA port presence
540          * is asserted through the standard AHCI port
541          * presence register, as bit 4 (counting from 0)
542          */
543         if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
544                 if (pdev->device == 0x6121)
545                         hpriv->mask_port_map = 0x3;
546                 else
547                         hpriv->mask_port_map = 0xf;
548                 dev_info(&pdev->dev,
549                           "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
550         }
551 
552         ahci_save_initial_config(&pdev->dev, hpriv);
553 }
554 
555 static int ahci_pci_reset_controller(struct ata_host *host)
556 {
557         struct pci_dev *pdev = to_pci_dev(host->dev);
558 
559         ahci_reset_controller(host);
560 
561         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
562                 struct ahci_host_priv *hpriv = host->private_data;
563                 u16 tmp16;
564 
565                 /* configure PCS */
566                 pci_read_config_word(pdev, 0x92, &tmp16);
567                 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
568                         tmp16 |= hpriv->port_map;
569                         pci_write_config_word(pdev, 0x92, tmp16);
570                 }
571         }
572 
573         return 0;
574 }
575 
576 static void ahci_pci_init_controller(struct ata_host *host)
577 {
578         struct ahci_host_priv *hpriv = host->private_data;
579         struct pci_dev *pdev = to_pci_dev(host->dev);
580         void __iomem *port_mmio;
581         u32 tmp;
582         int mv;
583 
584         if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
585                 if (pdev->device == 0x6121)
586                         mv = 2;
587                 else
588                         mv = 4;
589                 port_mmio = __ahci_port_base(host, mv);
590 
591                 writel(0, port_mmio + PORT_IRQ_MASK);
592 
593                 /* clear port IRQ */
594                 tmp = readl(port_mmio + PORT_IRQ_STAT);
595                 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
596                 if (tmp)
597                         writel(tmp, port_mmio + PORT_IRQ_STAT);
598         }
599 
600         ahci_init_controller(host);
601 }
602 
603 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
604                                  unsigned long deadline)
605 {
606         struct ata_port *ap = link->ap;
607         struct ahci_host_priv *hpriv = ap->host->private_data;
608         bool online;
609         int rc;
610 
611         DPRINTK("ENTER\n");
612 
613         ahci_stop_engine(ap);
614 
615         rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
616                                  deadline, &online, NULL);
617 
618         hpriv->start_engine(ap);
619 
620         DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
621 
622         /* vt8251 doesn't clear BSY on signature FIS reception,
623          * request follow-up softreset.
624          */
625         return online ? -EAGAIN : rc;
626 }
627 
628 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
629                                 unsigned long deadline)
630 {
631         struct ata_port *ap = link->ap;
632         struct ahci_port_priv *pp = ap->private_data;
633         struct ahci_host_priv *hpriv = ap->host->private_data;
634         u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
635         struct ata_taskfile tf;
636         bool online;
637         int rc;
638 
639         ahci_stop_engine(ap);
640 
641         /* clear D2H reception area to properly wait for D2H FIS */
642         ata_tf_init(link->device, &tf);
643         tf.command = ATA_BUSY;
644         ata_tf_to_fis(&tf, 0, 0, d2h_fis);
645 
646         rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
647                                  deadline, &online, NULL);
648 
649         hpriv->start_engine(ap);
650 
651         /* The pseudo configuration device on SIMG4726 attached to
652          * ASUS P5W-DH Deluxe doesn't send signature FIS after
653          * hardreset if no device is attached to the first downstream
654          * port && the pseudo device locks up on SRST w/ PMP==0.  To
655          * work around this, wait for !BSY only briefly.  If BSY isn't
656          * cleared, perform CLO and proceed to IDENTIFY (achieved by
657          * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
658          *
659          * Wait for two seconds.  Devices attached to downstream port
660          * which can't process the following IDENTIFY after this will
661          * have to be reset again.  For most cases, this should
662          * suffice while making probing snappish enough.
663          */
664         if (online) {
665                 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
666                                           ahci_check_ready);
667                 if (rc)
668                         ahci_kick_engine(ap);
669         }
670         return rc;
671 }
672 
673 #ifdef CONFIG_PM
674 static int ahci_pci_device_suspend(struct pci_dev *pdev, pm_message_t mesg)
675 {
676         struct ata_host *host = pci_get_drvdata(pdev);
677         struct ahci_host_priv *hpriv = host->private_data;
678         void __iomem *mmio = hpriv->mmio;
679         u32 ctl;
680 
681         if (mesg.event & PM_EVENT_SUSPEND &&
682             hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
683                 dev_err(&pdev->dev,
684                         "BIOS update required for suspend/resume\n");
685                 return -EIO;
686         }
687 
688         if (mesg.event & PM_EVENT_SLEEP) {
689                 /* AHCI spec rev1.1 section 8.3.3:
690                  * Software must disable interrupts prior to requesting a
691                  * transition of the HBA to D3 state.
692                  */
693                 ctl = readl(mmio + HOST_CTL);
694                 ctl &= ~HOST_IRQ_EN;
695                 writel(ctl, mmio + HOST_CTL);
696                 readl(mmio + HOST_CTL); /* flush */
697         }
698 
699         return ata_pci_device_suspend(pdev, mesg);
700 }
701 
702 static int ahci_pci_device_resume(struct pci_dev *pdev)
703 {
704         struct ata_host *host = pci_get_drvdata(pdev);
705         int rc;
706 
707         rc = ata_pci_device_do_resume(pdev);
708         if (rc)
709                 return rc;
710 
711         /* Apple BIOS helpfully mangles the registers on resume */
712         if (is_mcp89_apple(pdev))
713                 ahci_mcp89_apple_enable(pdev);
714 
715         if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
716                 rc = ahci_pci_reset_controller(host);
717                 if (rc)
718                         return rc;
719 
720                 ahci_pci_init_controller(host);
721         }
722 
723         ata_host_resume(host);
724 
725         return 0;
726 }
727 #endif
728 
729 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
730 {
731         int rc;
732 
733         /*
734          * If the device fixup already set the dma_mask to some non-standard
735          * value, don't extend it here. This happens on STA2X11, for example.
736          */
737         if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
738                 return 0;
739 
740         if (using_dac &&
741             !pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
742                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
743                 if (rc) {
744                         rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
745                         if (rc) {
746                                 dev_err(&pdev->dev,
747                                         "64-bit DMA enable failed\n");
748                                 return rc;
749                         }
750                 }
751         } else {
752                 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
753                 if (rc) {
754                         dev_err(&pdev->dev, "32-bit DMA enable failed\n");
755                         return rc;
756                 }
757                 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
758                 if (rc) {
759                         dev_err(&pdev->dev,
760                                 "32-bit consistent DMA enable failed\n");
761                         return rc;
762                 }
763         }
764         return 0;
765 }
766 
767 static void ahci_pci_print_info(struct ata_host *host)
768 {
769         struct pci_dev *pdev = to_pci_dev(host->dev);
770         u16 cc;
771         const char *scc_s;
772 
773         pci_read_config_word(pdev, 0x0a, &cc);
774         if (cc == PCI_CLASS_STORAGE_IDE)
775                 scc_s = "IDE";
776         else if (cc == PCI_CLASS_STORAGE_SATA)
777                 scc_s = "SATA";
778         else if (cc == PCI_CLASS_STORAGE_RAID)
779                 scc_s = "RAID";
780         else
781                 scc_s = "unknown";
782 
783         ahci_print_info(host, scc_s);
784 }
785 
786 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
787  * hardwired to on-board SIMG 4726.  The chipset is ICH8 and doesn't
788  * support PMP and the 4726 either directly exports the device
789  * attached to the first downstream port or acts as a hardware storage
790  * controller and emulate a single ATA device (can be RAID 0/1 or some
791  * other configuration).
792  *
793  * When there's no device attached to the first downstream port of the
794  * 4726, "Config Disk" appears, which is a pseudo ATA device to
795  * configure the 4726.  However, ATA emulation of the device is very
796  * lame.  It doesn't send signature D2H Reg FIS after the initial
797  * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
798  *
799  * The following function works around the problem by always using
800  * hardreset on the port and not depending on receiving signature FIS
801  * afterward.  If signature FIS isn't received soon, ATA class is
802  * assumed without follow-up softreset.
803  */
804 static void ahci_p5wdh_workaround(struct ata_host *host)
805 {
806         static const struct dmi_system_id sysids[] = {
807                 {
808                         .ident = "P5W DH Deluxe",
809                         .matches = {
810                                 DMI_MATCH(DMI_SYS_VENDOR,
811                                           "ASUSTEK COMPUTER INC"),
812                                 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
813                         },
814                 },
815                 { }
816         };
817         struct pci_dev *pdev = to_pci_dev(host->dev);
818 
819         if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
820             dmi_check_system(sysids)) {
821                 struct ata_port *ap = host->ports[1];
822 
823                 dev_info(&pdev->dev,
824                          "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
825 
826                 ap->ops = &ahci_p5wdh_ops;
827                 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
828         }
829 }
830 
831 /*
832  * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
833  * booting in BIOS compatibility mode.  We restore the registers but not ID.
834  */
835 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
836 {
837         u32 val;
838 
839         printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
840 
841         pci_read_config_dword(pdev, 0xf8, &val);
842         val |= 1 << 0x1b;
843         /* the following changes the device ID, but appears not to affect function */
844         /* val = (val & ~0xf0000000) | 0x80000000; */
845         pci_write_config_dword(pdev, 0xf8, val);
846 
847         pci_read_config_dword(pdev, 0x54c, &val);
848         val |= 1 << 0xc;
849         pci_write_config_dword(pdev, 0x54c, val);
850 
851         pci_read_config_dword(pdev, 0x4a4, &val);
852         val &= 0xff;
853         val |= 0x01060100;
854         pci_write_config_dword(pdev, 0x4a4, val);
855 
856         pci_read_config_dword(pdev, 0x54c, &val);
857         val &= ~(1 << 0xc);
858         pci_write_config_dword(pdev, 0x54c, val);
859 
860         pci_read_config_dword(pdev, 0xf8, &val);
861         val &= ~(1 << 0x1b);
862         pci_write_config_dword(pdev, 0xf8, val);
863 }
864 
865 static bool is_mcp89_apple(struct pci_dev *pdev)
866 {
867         return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
868                 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
869                 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
870                 pdev->subsystem_device == 0xcb89;
871 }
872 
873 /* only some SB600 ahci controllers can do 64bit DMA */
874 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
875 {
876         static const struct dmi_system_id sysids[] = {
877                 /*
878                  * The oldest version known to be broken is 0901 and
879                  * working is 1501 which was released on 2007-10-26.
880                  * Enable 64bit DMA on 1501 and anything newer.
881                  *
882                  * Please read bko#9412 for more info.
883                  */
884                 {
885                         .ident = "ASUS M2A-VM",
886                         .matches = {
887                                 DMI_MATCH(DMI_BOARD_VENDOR,
888                                           "ASUSTeK Computer INC."),
889                                 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
890                         },
891                         .driver_data = "20071026",      /* yyyymmdd */
892                 },
893                 /*
894                  * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
895                  * support 64bit DMA.
896                  *
897                  * BIOS versions earlier than 1.5 had the Manufacturer DMI
898                  * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
899                  * This spelling mistake was fixed in BIOS version 1.5, so
900                  * 1.5 and later have the Manufacturer as
901                  * "MICRO-STAR INTERNATIONAL CO.,LTD".
902                  * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
903                  *
904                  * BIOS versions earlier than 1.9 had a Board Product Name
905                  * DMI field of "MS-7376". This was changed to be
906                  * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
907                  * match on DMI_BOARD_NAME of "MS-7376".
908                  */
909                 {
910                         .ident = "MSI K9A2 Platinum",
911                         .matches = {
912                                 DMI_MATCH(DMI_BOARD_VENDOR,
913                                           "MICRO-STAR INTER"),
914                                 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
915                         },
916                 },
917                 /*
918                  * All BIOS versions for the MSI K9AGM2 (MS-7327) support
919                  * 64bit DMA.
920                  *
921                  * This board also had the typo mentioned above in the
922                  * Manufacturer DMI field (fixed in BIOS version 1.5), so
923                  * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
924                  */
925                 {
926                         .ident = "MSI K9AGM2",
927                         .matches = {
928                                 DMI_MATCH(DMI_BOARD_VENDOR,
929                                           "MICRO-STAR INTER"),
930                                 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
931                         },
932                 },
933                 /*
934                  * All BIOS versions for the Asus M3A support 64bit DMA.
935                  * (all release versions from 0301 to 1206 were tested)
936                  */
937                 {
938                         .ident = "ASUS M3A",
939                         .matches = {
940                                 DMI_MATCH(DMI_BOARD_VENDOR,
941                                           "ASUSTeK Computer INC."),
942                                 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
943                         },
944                 },
945                 { }
946         };
947         const struct dmi_system_id *match;
948         int year, month, date;
949         char buf[9];
950 
951         match = dmi_first_match(sysids);
952         if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
953             !match)
954                 return false;
955 
956         if (!match->driver_data)
957                 goto enable_64bit;
958 
959         dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
960         snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
961 
962         if (strcmp(buf, match->driver_data) >= 0)
963                 goto enable_64bit;
964         else {
965                 dev_warn(&pdev->dev,
966                          "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
967                          match->ident);
968                 return false;
969         }
970 
971 enable_64bit:
972         dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
973         return true;
974 }
975 
976 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
977 {
978         static const struct dmi_system_id broken_systems[] = {
979                 {
980                         .ident = "HP Compaq nx6310",
981                         .matches = {
982                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
983                                 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
984                         },
985                         /* PCI slot number of the controller */
986                         .driver_data = (void *)0x1FUL,
987                 },
988                 {
989                         .ident = "HP Compaq 6720s",
990                         .matches = {
991                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
992                                 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
993                         },
994                         /* PCI slot number of the controller */
995                         .driver_data = (void *)0x1FUL,
996                 },
997 
998                 { }     /* terminate list */
999         };
1000         const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1001 
1002         if (dmi) {
1003                 unsigned long slot = (unsigned long)dmi->driver_data;
1004                 /* apply the quirk only to on-board controllers */
1005                 return slot == PCI_SLOT(pdev->devfn);
1006         }
1007 
1008         return false;
1009 }
1010 
1011 static bool ahci_broken_suspend(struct pci_dev *pdev)
1012 {
1013         static const struct dmi_system_id sysids[] = {
1014                 /*
1015                  * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1016                  * to the harddisk doesn't become online after
1017                  * resuming from STR.  Warn and fail suspend.
1018                  *
1019                  * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1020                  *
1021                  * Use dates instead of versions to match as HP is
1022                  * apparently recycling both product and version
1023                  * strings.
1024                  *
1025                  * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1026                  */
1027                 {
1028                         .ident = "dv4",
1029                         .matches = {
1030                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1031                                 DMI_MATCH(DMI_PRODUCT_NAME,
1032                                           "HP Pavilion dv4 Notebook PC"),
1033                         },
1034                         .driver_data = "20090105",      /* F.30 */
1035                 },
1036                 {
1037                         .ident = "dv5",
1038                         .matches = {
1039                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1040                                 DMI_MATCH(DMI_PRODUCT_NAME,
1041                                           "HP Pavilion dv5 Notebook PC"),
1042                         },
1043                         .driver_data = "20090506",      /* F.16 */
1044                 },
1045                 {
1046                         .ident = "dv6",
1047                         .matches = {
1048                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1049                                 DMI_MATCH(DMI_PRODUCT_NAME,
1050                                           "HP Pavilion dv6 Notebook PC"),
1051                         },
1052                         .driver_data = "20090423",      /* F.21 */
1053                 },
1054                 {
1055                         .ident = "HDX18",
1056                         .matches = {
1057                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1058                                 DMI_MATCH(DMI_PRODUCT_NAME,
1059                                           "HP HDX18 Notebook PC"),
1060                         },
1061                         .driver_data = "20090430",      /* F.23 */
1062                 },
1063                 /*
1064                  * Acer eMachines G725 has the same problem.  BIOS
1065                  * V1.03 is known to be broken.  V3.04 is known to
1066                  * work.  Between, there are V1.06, V2.06 and V3.03
1067                  * that we don't have much idea about.  For now,
1068                  * blacklist anything older than V3.04.
1069                  *
1070                  * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1071                  */
1072                 {
1073                         .ident = "G725",
1074                         .matches = {
1075                                 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1076                                 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1077                         },
1078                         .driver_data = "20091216",      /* V3.04 */
1079                 },
1080                 { }     /* terminate list */
1081         };
1082         const struct dmi_system_id *dmi = dmi_first_match(sysids);
1083         int year, month, date;
1084         char buf[9];
1085 
1086         if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1087                 return false;
1088 
1089         dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1090         snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1091 
1092         return strcmp(buf, dmi->driver_data) < 0;
1093 }
1094 
1095 static bool ahci_broken_online(struct pci_dev *pdev)
1096 {
1097 #define ENCODE_BUSDEVFN(bus, slot, func)                        \
1098         (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1099         static const struct dmi_system_id sysids[] = {
1100                 /*
1101                  * There are several gigabyte boards which use
1102                  * SIMG5723s configured as hardware RAID.  Certain
1103                  * 5723 firmware revisions shipped there keep the link
1104                  * online but fail to answer properly to SRST or
1105                  * IDENTIFY when no device is attached downstream
1106                  * causing libata to retry quite a few times leading
1107                  * to excessive detection delay.
1108                  *
1109                  * As these firmwares respond to the second reset try
1110                  * with invalid device signature, considering unknown
1111                  * sig as offline works around the problem acceptably.
1112                  */
1113                 {
1114                         .ident = "EP45-DQ6",
1115                         .matches = {
1116                                 DMI_MATCH(DMI_BOARD_VENDOR,
1117                                           "Gigabyte Technology Co., Ltd."),
1118                                 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1119                         },
1120                         .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1121                 },
1122                 {
1123                         .ident = "EP45-DS5",
1124                         .matches = {
1125                                 DMI_MATCH(DMI_BOARD_VENDOR,
1126                                           "Gigabyte Technology Co., Ltd."),
1127                                 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1128                         },
1129                         .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1130                 },
1131                 { }     /* terminate list */
1132         };
1133 #undef ENCODE_BUSDEVFN
1134         const struct dmi_system_id *dmi = dmi_first_match(sysids);
1135         unsigned int val;
1136 
1137         if (!dmi)
1138                 return false;
1139 
1140         val = (unsigned long)dmi->driver_data;
1141 
1142         return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1143 }
1144 
1145 static bool ahci_broken_devslp(struct pci_dev *pdev)
1146 {
1147         /* device with broken DEVSLP but still showing SDS capability */
1148         static const struct pci_device_id ids[] = {
1149                 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1150                 {}
1151         };
1152 
1153         return pci_match_id(ids, pdev);
1154 }
1155 
1156 #ifdef CONFIG_ATA_ACPI
1157 static void ahci_gtf_filter_workaround(struct ata_host *host)
1158 {
1159         static const struct dmi_system_id sysids[] = {
1160                 /*
1161                  * Aspire 3810T issues a bunch of SATA enable commands
1162                  * via _GTF including an invalid one and one which is
1163                  * rejected by the device.  Among the successful ones
1164                  * is FPDMA non-zero offset enable which when enabled
1165                  * only on the drive side leads to NCQ command
1166                  * failures.  Filter it out.
1167                  */
1168                 {
1169                         .ident = "Aspire 3810T",
1170                         .matches = {
1171                                 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1172                                 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1173                         },
1174                         .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1175                 },
1176                 { }
1177         };
1178         const struct dmi_system_id *dmi = dmi_first_match(sysids);
1179         unsigned int filter;
1180         int i;
1181 
1182         if (!dmi)
1183                 return;
1184 
1185         filter = (unsigned long)dmi->driver_data;
1186         dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1187                  filter, dmi->ident);
1188 
1189         for (i = 0; i < host->n_ports; i++) {
1190                 struct ata_port *ap = host->ports[i];
1191                 struct ata_link *link;
1192                 struct ata_device *dev;
1193 
1194                 ata_for_each_link(link, ap, EDGE)
1195                         ata_for_each_dev(dev, link, ALL)
1196                                 dev->gtf_filter |= filter;
1197         }
1198 }
1199 #else
1200 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1201 {}
1202 #endif
1203 
1204 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1205                                 struct ahci_host_priv *hpriv)
1206 {
1207         int rc, nvec;
1208 
1209         if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1210                 goto intx;
1211 
1212         nvec = pci_msi_vec_count(pdev);
1213         if (nvec < 0)
1214                 goto intx;
1215 
1216         /*
1217          * If number of MSIs is less than number of ports then Sharing Last
1218          * Message mode could be enforced. In this case assume that advantage
1219          * of multipe MSIs is negated and use single MSI mode instead.
1220          */
1221         if (nvec < n_ports)
1222                 goto single_msi;
1223 
1224         rc = pci_enable_msi_exact(pdev, nvec);
1225         if (rc == -ENOSPC)
1226                 goto single_msi;
1227         else if (rc < 0)
1228                 goto intx;
1229 
1230         /* fallback to single MSI mode if the controller enforced MRSM mode */
1231         if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1232                 pci_disable_msi(pdev);
1233                 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1234                 goto single_msi;
1235         }
1236 
1237         if (nvec > 1)
1238                 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1239 
1240         return nvec;
1241 
1242 single_msi:
1243         if (pci_enable_msi(pdev))
1244                 goto intx;
1245         return 1;
1246 
1247 intx:
1248         pci_intx(pdev, 1);
1249         return 0;
1250 }
1251 
1252 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1253 {
1254         unsigned int board_id = ent->driver_data;
1255         struct ata_port_info pi = ahci_port_info[board_id];
1256         const struct ata_port_info *ppi[] = { &pi, NULL };
1257         struct device *dev = &pdev->dev;
1258         struct ahci_host_priv *hpriv;
1259         struct ata_host *host;
1260         int n_ports, i, rc;
1261         int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1262 
1263         VPRINTK("ENTER\n");
1264 
1265         WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1266 
1267         ata_print_version_once(&pdev->dev, DRV_VERSION);
1268 
1269         /* The AHCI driver can only drive the SATA ports, the PATA driver
1270            can drive them all so if both drivers are selected make sure
1271            AHCI stays out of the way */
1272         if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1273                 return -ENODEV;
1274 
1275         /* Apple BIOS on MCP89 prevents us using AHCI */
1276         if (is_mcp89_apple(pdev))
1277                 ahci_mcp89_apple_enable(pdev);
1278 
1279         /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1280          * At the moment, we can only use the AHCI mode. Let the users know
1281          * that for SAS drives they're out of luck.
1282          */
1283         if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1284                 dev_info(&pdev->dev,
1285                          "PDC42819 can only drive SATA devices with this driver\n");
1286 
1287         /* Both Connext and Enmotus devices use non-standard BARs */
1288         if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1289                 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1290         else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1291                 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1292 
1293         /*
1294          * The JMicron chip 361/363 contains one SATA controller and one
1295          * PATA controller,for powering on these both controllers, we must
1296          * follow the sequence one by one, otherwise one of them can not be
1297          * powered on successfully, so here we disable the async suspend
1298          * method for these chips.
1299          */
1300         if (pdev->vendor == PCI_VENDOR_ID_JMICRON &&
1301                 (pdev->device == PCI_DEVICE_ID_JMICRON_JMB363 ||
1302                 pdev->device == PCI_DEVICE_ID_JMICRON_JMB361))
1303                 device_disable_async_suspend(&pdev->dev);
1304 
1305         /* acquire resources */
1306         rc = pcim_enable_device(pdev);
1307         if (rc)
1308                 return rc;
1309 
1310         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1311             (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1312                 u8 map;
1313 
1314                 /* ICH6s share the same PCI ID for both piix and ahci
1315                  * modes.  Enabling ahci mode while MAP indicates
1316                  * combined mode is a bad idea.  Yield to ata_piix.
1317                  */
1318                 pci_read_config_byte(pdev, ICH_MAP, &map);
1319                 if (map & 0x3) {
1320                         dev_info(&pdev->dev,
1321                                  "controller is in combined mode, can't enable AHCI mode\n");
1322                         return -ENODEV;
1323                 }
1324         }
1325 
1326         /* AHCI controllers often implement SFF compatible interface.
1327          * Grab all PCI BARs just in case.
1328          */
1329         rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1330         if (rc == -EBUSY)
1331                 pcim_pin_device(pdev);
1332         if (rc)
1333                 return rc;
1334 
1335         hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1336         if (!hpriv)
1337                 return -ENOMEM;
1338         hpriv->flags |= (unsigned long)pi.private_data;
1339 
1340         /* MCP65 revision A1 and A2 can't do MSI */
1341         if (board_id == board_ahci_mcp65 &&
1342             (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1343                 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1344 
1345         /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1346         if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1347                 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1348 
1349         /* only some SB600s can do 64bit DMA */
1350         if (ahci_sb600_enable_64bit(pdev))
1351                 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1352 
1353         hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1354 
1355         /* must set flag prior to save config in order to take effect */
1356         if (ahci_broken_devslp(pdev))
1357                 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1358 
1359         /* save initial config */
1360         ahci_pci_save_initial_config(pdev, hpriv);
1361 
1362         /* prepare host */
1363         if (hpriv->cap & HOST_CAP_NCQ) {
1364                 pi.flags |= ATA_FLAG_NCQ;
1365                 /*
1366                  * Auto-activate optimization is supposed to be
1367                  * supported on all AHCI controllers indicating NCQ
1368                  * capability, but it seems to be broken on some
1369                  * chipsets including NVIDIAs.
1370                  */
1371                 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1372                         pi.flags |= ATA_FLAG_FPDMA_AA;
1373 
1374                 /*
1375                  * All AHCI controllers should be forward-compatible
1376                  * with the new auxiliary field. This code should be
1377                  * conditionalized if any buggy AHCI controllers are
1378                  * encountered.
1379                  */
1380                 pi.flags |= ATA_FLAG_FPDMA_AUX;
1381         }
1382 
1383         if (hpriv->cap & HOST_CAP_PMP)
1384                 pi.flags |= ATA_FLAG_PMP;
1385 
1386         ahci_set_em_messages(hpriv, &pi);
1387 
1388         if (ahci_broken_system_poweroff(pdev)) {
1389                 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1390                 dev_info(&pdev->dev,
1391                         "quirky BIOS, skipping spindown on poweroff\n");
1392         }
1393 
1394         if (ahci_broken_suspend(pdev)) {
1395                 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1396                 dev_warn(&pdev->dev,
1397                          "BIOS update required for suspend/resume\n");
1398         }
1399 
1400         if (ahci_broken_online(pdev)) {
1401                 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1402                 dev_info(&pdev->dev,
1403                          "online status unreliable, applying workaround\n");
1404         }
1405 
1406         /* CAP.NP sometimes indicate the index of the last enabled
1407          * port, at other times, that of the last possible port, so
1408          * determining the maximum port number requires looking at
1409          * both CAP.NP and port_map.
1410          */
1411         n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1412 
1413         ahci_init_interrupts(pdev, n_ports, hpriv);
1414 
1415         host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1416         if (!host)
1417                 return -ENOMEM;
1418         host->private_data = hpriv;
1419 
1420         if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1421                 host->flags |= ATA_HOST_PARALLEL_SCAN;
1422         else
1423                 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1424 
1425         if (pi.flags & ATA_FLAG_EM)
1426                 ahci_reset_em(host);
1427 
1428         for (i = 0; i < host->n_ports; i++) {
1429                 struct ata_port *ap = host->ports[i];
1430 
1431                 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1432                 ata_port_pbar_desc(ap, ahci_pci_bar,
1433                                    0x100 + ap->port_no * 0x80, "port");
1434 
1435                 /* set enclosure management message type */
1436                 if (ap->flags & ATA_FLAG_EM)
1437                         ap->em_message_type = hpriv->em_msg_type;
1438 
1439 
1440                 /* disabled/not-implemented port */
1441                 if (!(hpriv->port_map & (1 << i)))
1442                         ap->ops = &ata_dummy_port_ops;
1443         }
1444 
1445         /* apply workaround for ASUS P5W DH Deluxe mainboard */
1446         ahci_p5wdh_workaround(host);
1447 
1448         /* apply gtf filter quirk */
1449         ahci_gtf_filter_workaround(host);
1450 
1451         /* initialize adapter */
1452         rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1453         if (rc)
1454                 return rc;
1455 
1456         rc = ahci_pci_reset_controller(host);
1457         if (rc)
1458                 return rc;
1459 
1460         ahci_pci_init_controller(host);
1461         ahci_pci_print_info(host);
1462 
1463         pci_set_master(pdev);
1464 
1465         return ahci_host_activate(host, pdev->irq, &ahci_sht);
1466 }
1467 
1468 module_pci_driver(ahci_pci_driver);
1469 
1470 MODULE_AUTHOR("Jeff Garzik");
1471 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1472 MODULE_LICENSE("GPL");
1473 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1474 MODULE_VERSION(DRV_VERSION);
1475 

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