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Linux/drivers/ata/ahci.c

  1 /*
  2  *  ahci.c - AHCI SATA support
  3  *
  4  *  Maintained by:  Tejun Heo <tj@kernel.org>
  5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  6  *                  on emails.
  7  *
  8  *  Copyright 2004-2005 Red Hat, Inc.
  9  *
 10  *
 11  *  This program is free software; you can redistribute it and/or modify
 12  *  it under the terms of the GNU General Public License as published by
 13  *  the Free Software Foundation; either version 2, or (at your option)
 14  *  any later version.
 15  *
 16  *  This program is distributed in the hope that it will be useful,
 17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 19  *  GNU General Public License for more details.
 20  *
 21  *  You should have received a copy of the GNU General Public License
 22  *  along with this program; see the file COPYING.  If not, write to
 23  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 24  *
 25  *
 26  * libata documentation is available via 'make {ps|pdf}docs',
 27  * as Documentation/DocBook/libata.*
 28  *
 29  * AHCI hardware documentation:
 30  * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
 31  * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
 32  *
 33  */
 34 
 35 #include <linux/kernel.h>
 36 #include <linux/module.h>
 37 #include <linux/pci.h>
 38 #include <linux/blkdev.h>
 39 #include <linux/delay.h>
 40 #include <linux/interrupt.h>
 41 #include <linux/dma-mapping.h>
 42 #include <linux/device.h>
 43 #include <linux/dmi.h>
 44 #include <linux/gfp.h>
 45 #include <linux/msi.h>
 46 #include <scsi/scsi_host.h>
 47 #include <scsi/scsi_cmnd.h>
 48 #include <linux/libata.h>
 49 #include <linux/ahci-remap.h>
 50 #include <linux/io-64-nonatomic-lo-hi.h>
 51 #include "ahci.h"
 52 
 53 #define DRV_NAME        "ahci"
 54 #define DRV_VERSION     "3.0"
 55 
 56 enum {
 57         AHCI_PCI_BAR_STA2X11    = 0,
 58         AHCI_PCI_BAR_CAVIUM     = 0,
 59         AHCI_PCI_BAR_ENMOTUS    = 2,
 60         AHCI_PCI_BAR_STANDARD   = 5,
 61 };
 62 
 63 enum board_ids {
 64         /* board IDs by feature in alphabetical order */
 65         board_ahci,
 66         board_ahci_ign_iferr,
 67         board_ahci_nomsi,
 68         board_ahci_noncq,
 69         board_ahci_nosntf,
 70         board_ahci_yes_fbs,
 71 
 72         /* board IDs for specific chipsets in alphabetical order */
 73         board_ahci_avn,
 74         board_ahci_mcp65,
 75         board_ahci_mcp77,
 76         board_ahci_mcp89,
 77         board_ahci_mv,
 78         board_ahci_sb600,
 79         board_ahci_sb700,       /* for SB700 and SB800 */
 80         board_ahci_vt8251,
 81 
 82         /* aliases */
 83         board_ahci_mcp_linux    = board_ahci_mcp65,
 84         board_ahci_mcp67        = board_ahci_mcp65,
 85         board_ahci_mcp73        = board_ahci_mcp65,
 86         board_ahci_mcp79        = board_ahci_mcp77,
 87 };
 88 
 89 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
 90 static void ahci_remove_one(struct pci_dev *dev);
 91 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 92                                  unsigned long deadline);
 93 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
 94                               unsigned long deadline);
 95 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
 96 static bool is_mcp89_apple(struct pci_dev *pdev);
 97 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 98                                 unsigned long deadline);
 99 #ifdef CONFIG_PM
100 static int ahci_pci_device_runtime_suspend(struct device *dev);
101 static int ahci_pci_device_runtime_resume(struct device *dev);
102 #ifdef CONFIG_PM_SLEEP
103 static int ahci_pci_device_suspend(struct device *dev);
104 static int ahci_pci_device_resume(struct device *dev);
105 #endif
106 #endif /* CONFIG_PM */
107 
108 static struct scsi_host_template ahci_sht = {
109         AHCI_SHT("ahci"),
110 };
111 
112 static struct ata_port_operations ahci_vt8251_ops = {
113         .inherits               = &ahci_ops,
114         .hardreset              = ahci_vt8251_hardreset,
115 };
116 
117 static struct ata_port_operations ahci_p5wdh_ops = {
118         .inherits               = &ahci_ops,
119         .hardreset              = ahci_p5wdh_hardreset,
120 };
121 
122 static struct ata_port_operations ahci_avn_ops = {
123         .inherits               = &ahci_ops,
124         .hardreset              = ahci_avn_hardreset,
125 };
126 
127 static const struct ata_port_info ahci_port_info[] = {
128         /* by features */
129         [board_ahci] = {
130                 .flags          = AHCI_FLAG_COMMON,
131                 .pio_mask       = ATA_PIO4,
132                 .udma_mask      = ATA_UDMA6,
133                 .port_ops       = &ahci_ops,
134         },
135         [board_ahci_ign_iferr] = {
136                 AHCI_HFLAGS     (AHCI_HFLAG_IGN_IRQ_IF_ERR),
137                 .flags          = AHCI_FLAG_COMMON,
138                 .pio_mask       = ATA_PIO4,
139                 .udma_mask      = ATA_UDMA6,
140                 .port_ops       = &ahci_ops,
141         },
142         [board_ahci_nomsi] = {
143                 AHCI_HFLAGS     (AHCI_HFLAG_NO_MSI),
144                 .flags          = AHCI_FLAG_COMMON,
145                 .pio_mask       = ATA_PIO4,
146                 .udma_mask      = ATA_UDMA6,
147                 .port_ops       = &ahci_ops,
148         },
149         [board_ahci_noncq] = {
150                 AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ),
151                 .flags          = AHCI_FLAG_COMMON,
152                 .pio_mask       = ATA_PIO4,
153                 .udma_mask      = ATA_UDMA6,
154                 .port_ops       = &ahci_ops,
155         },
156         [board_ahci_nosntf] = {
157                 AHCI_HFLAGS     (AHCI_HFLAG_NO_SNTF),
158                 .flags          = AHCI_FLAG_COMMON,
159                 .pio_mask       = ATA_PIO4,
160                 .udma_mask      = ATA_UDMA6,
161                 .port_ops       = &ahci_ops,
162         },
163         [board_ahci_yes_fbs] = {
164                 AHCI_HFLAGS     (AHCI_HFLAG_YES_FBS),
165                 .flags          = AHCI_FLAG_COMMON,
166                 .pio_mask       = ATA_PIO4,
167                 .udma_mask      = ATA_UDMA6,
168                 .port_ops       = &ahci_ops,
169         },
170         /* by chipsets */
171         [board_ahci_avn] = {
172                 .flags          = AHCI_FLAG_COMMON,
173                 .pio_mask       = ATA_PIO4,
174                 .udma_mask      = ATA_UDMA6,
175                 .port_ops       = &ahci_avn_ops,
176         },
177         [board_ahci_mcp65] = {
178                 AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
179                                  AHCI_HFLAG_YES_NCQ),
180                 .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
181                 .pio_mask       = ATA_PIO4,
182                 .udma_mask      = ATA_UDMA6,
183                 .port_ops       = &ahci_ops,
184         },
185         [board_ahci_mcp77] = {
186                 AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
187                 .flags          = AHCI_FLAG_COMMON,
188                 .pio_mask       = ATA_PIO4,
189                 .udma_mask      = ATA_UDMA6,
190                 .port_ops       = &ahci_ops,
191         },
192         [board_ahci_mcp89] = {
193                 AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA),
194                 .flags          = AHCI_FLAG_COMMON,
195                 .pio_mask       = ATA_PIO4,
196                 .udma_mask      = ATA_UDMA6,
197                 .port_ops       = &ahci_ops,
198         },
199         [board_ahci_mv] = {
200                 AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
201                                  AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
202                 .flags          = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
203                 .pio_mask       = ATA_PIO4,
204                 .udma_mask      = ATA_UDMA6,
205                 .port_ops       = &ahci_ops,
206         },
207         [board_ahci_sb600] = {
208                 AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL |
209                                  AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
210                                  AHCI_HFLAG_32BIT_ONLY),
211                 .flags          = AHCI_FLAG_COMMON,
212                 .pio_mask       = ATA_PIO4,
213                 .udma_mask      = ATA_UDMA6,
214                 .port_ops       = &ahci_pmp_retry_srst_ops,
215         },
216         [board_ahci_sb700] = {  /* for SB700 and SB800 */
217                 AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL),
218                 .flags          = AHCI_FLAG_COMMON,
219                 .pio_mask       = ATA_PIO4,
220                 .udma_mask      = ATA_UDMA6,
221                 .port_ops       = &ahci_pmp_retry_srst_ops,
222         },
223         [board_ahci_vt8251] = {
224                 AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
225                 .flags          = AHCI_FLAG_COMMON,
226                 .pio_mask       = ATA_PIO4,
227                 .udma_mask      = ATA_UDMA6,
228                 .port_ops       = &ahci_vt8251_ops,
229         },
230 };
231 
232 static const struct pci_device_id ahci_pci_tbl[] = {
233         /* Intel */
234         { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
235         { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
236         { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
237         { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
238         { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
239         { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
240         { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
241         { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
242         { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
243         { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
244         { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
245         { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
246         { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
247         { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
248         { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
249         { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
250         { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
251         { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
252         { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
253         { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
254         { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
255         { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
256         { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
257         { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
258         { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
259         { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
260         { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
261         { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
262         { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
263         { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
264         { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
265         { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
266         { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
267         { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
268         { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
269         { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
270         { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
271         { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
272         { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
273         { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
274         { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
275         { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
276         { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
277         { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
278         { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
279         { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
280         { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
281         { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
282         { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
283         { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
284         { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
285         { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
286         { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
287         { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
288         { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
289         { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
290         { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
291         { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
292         { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
293         { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
294         { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
295         { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
296         { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
297         { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
298         { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
299         { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
300         { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
301         { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
302         { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
303         { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
304         { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
305         { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
306         { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
307         { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
308         { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
309         { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
310         { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
311         { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
312         { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
313         { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
314         { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
315         { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
316         { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
317         { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
318         { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
319         { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
320         { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
321         { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
322         { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
323         { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
324         { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
325         { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
326         { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
327         { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
328         { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
329         { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
330         { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
331         { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
332         { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
333         { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
334         { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
335         { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
336         { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
337         { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
338         { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
339         { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
340         { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
341         { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
342         { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
343         { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
344         { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
345         { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
346         { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
347         { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
348         { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
349         { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
350         { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
351         { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
352         { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
353         { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
354         { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
355         { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
356         { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
357         { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
358         { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
359         { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
360         { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
361         { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
362         { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
363         { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
364         { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
365         { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
366         { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
367         { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
368         { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
369         { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
370         { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
371         { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
372         { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
373         { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
374         { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
375         { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
376         { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
377         { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
378         { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
379         { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
380         { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
381         { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
382         { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
383         { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
384         { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
385         { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
386         { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
387         { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
388 
389         /* JMicron 360/1/3/5/6, match class to avoid IDE function */
390         { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
391           PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
392         /* JMicron 362B and 362C have an AHCI function with IDE class code */
393         { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
394         { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
395         /* May need to update quirk_jmicron_async_suspend() for additions */
396 
397         /* ATI */
398         { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
399         { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
400         { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
401         { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
402         { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
403         { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
404         { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
405 
406         /* AMD */
407         { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
408         { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
409         /* AMD is using RAID class only for ahci controllers */
410         { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
411           PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
412 
413         /* VIA */
414         { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
415         { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
416 
417         /* NVIDIA */
418         { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },      /* MCP65 */
419         { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },      /* MCP65 */
420         { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },      /* MCP65 */
421         { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },      /* MCP65 */
422         { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },      /* MCP65 */
423         { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },      /* MCP65 */
424         { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },      /* MCP65 */
425         { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },      /* MCP65 */
426         { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },      /* MCP67 */
427         { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },      /* MCP67 */
428         { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },      /* MCP67 */
429         { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },      /* MCP67 */
430         { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },      /* MCP67 */
431         { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },      /* MCP67 */
432         { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },      /* MCP67 */
433         { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },      /* MCP67 */
434         { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },      /* MCP67 */
435         { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },      /* MCP67 */
436         { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },      /* MCP67 */
437         { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },      /* MCP67 */
438         { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },  /* Linux ID */
439         { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },  /* Linux ID */
440         { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },  /* Linux ID */
441         { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },  /* Linux ID */
442         { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },  /* Linux ID */
443         { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },  /* Linux ID */
444         { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },  /* Linux ID */
445         { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },  /* Linux ID */
446         { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },  /* Linux ID */
447         { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },  /* Linux ID */
448         { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },  /* Linux ID */
449         { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },  /* Linux ID */
450         { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },  /* Linux ID */
451         { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },  /* Linux ID */
452         { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },  /* Linux ID */
453         { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },  /* Linux ID */
454         { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },      /* MCP73 */
455         { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },      /* MCP73 */
456         { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },      /* MCP73 */
457         { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },      /* MCP73 */
458         { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },      /* MCP73 */
459         { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },      /* MCP73 */
460         { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },      /* MCP73 */
461         { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },      /* MCP73 */
462         { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },      /* MCP73 */
463         { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },      /* MCP73 */
464         { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },      /* MCP73 */
465         { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },      /* MCP73 */
466         { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },      /* MCP77 */
467         { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },      /* MCP77 */
468         { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },      /* MCP77 */
469         { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },      /* MCP77 */
470         { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },      /* MCP77 */
471         { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },      /* MCP77 */
472         { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },      /* MCP77 */
473         { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },      /* MCP77 */
474         { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },      /* MCP77 */
475         { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },      /* MCP77 */
476         { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },      /* MCP77 */
477         { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },      /* MCP77 */
478         { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },      /* MCP79 */
479         { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },      /* MCP79 */
480         { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },      /* MCP79 */
481         { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },      /* MCP79 */
482         { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },      /* MCP79 */
483         { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },      /* MCP79 */
484         { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },      /* MCP79 */
485         { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },      /* MCP79 */
486         { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },      /* MCP79 */
487         { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },      /* MCP79 */
488         { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },      /* MCP79 */
489         { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },      /* MCP79 */
490         { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },      /* MCP89 */
491         { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },      /* MCP89 */
492         { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },      /* MCP89 */
493         { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },      /* MCP89 */
494         { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },      /* MCP89 */
495         { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },      /* MCP89 */
496         { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },      /* MCP89 */
497         { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },      /* MCP89 */
498         { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },      /* MCP89 */
499         { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },      /* MCP89 */
500         { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },      /* MCP89 */
501         { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },      /* MCP89 */
502 
503         /* SiS */
504         { PCI_VDEVICE(SI, 0x1184), board_ahci },                /* SiS 966 */
505         { PCI_VDEVICE(SI, 0x1185), board_ahci },                /* SiS 968 */
506         { PCI_VDEVICE(SI, 0x0186), board_ahci },                /* SiS 968 */
507 
508         /* ST Microelectronics */
509         { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci },           /* ST ConneXt */
510 
511         /* Marvell */
512         { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },        /* 6145 */
513         { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },        /* 6121 */
514         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
515           .class = PCI_CLASS_STORAGE_SATA_AHCI,
516           .class_mask = 0xffffff,
517           .driver_data = board_ahci_yes_fbs },                  /* 88se9128 */
518         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
519           .driver_data = board_ahci_yes_fbs },                  /* 88se9125 */
520         { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
521                          PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
522           .driver_data = board_ahci_yes_fbs },                  /* 88se9170 */
523         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
524           .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
525         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
526           .driver_data = board_ahci_yes_fbs },                  /* 88se9182 */
527         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
528           .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
529         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
530           .driver_data = board_ahci_yes_fbs },                  /* 88se9172 on some Gigabyte */
531         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
532           .driver_data = board_ahci_yes_fbs },
533         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2),        /* 88se91a2 */
534           .driver_data = board_ahci_yes_fbs },
535         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
536           .driver_data = board_ahci_yes_fbs },
537         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
538           .driver_data = board_ahci_yes_fbs },
539         { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
540           .driver_data = board_ahci_yes_fbs },
541 
542         /* Promise */
543         { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },   /* PDC42819 */
544         { PCI_VDEVICE(PROMISE, 0x3781), board_ahci },   /* FastTrak TX8660 ahci-mode */
545 
546         /* Asmedia */
547         { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci },   /* ASM1060 */
548         { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci },   /* ASM1060 */
549         { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci },   /* ASM1061 */
550         { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci },   /* ASM1062 */
551 
552         /*
553          * Samsung SSDs found on some macbooks.  NCQ times out if MSI is
554          * enabled.  https://bugzilla.kernel.org/show_bug.cgi?id=60731
555          */
556         { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
557         { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
558 
559         /* Enmotus */
560         { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
561 
562         /* Generic, PCI class code for AHCI */
563         { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
564           PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
565 
566         { }     /* terminate list */
567 };
568 
569 static const struct dev_pm_ops ahci_pci_pm_ops = {
570         SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
571         SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
572                            ahci_pci_device_runtime_resume, NULL)
573 };
574 
575 static struct pci_driver ahci_pci_driver = {
576         .name                   = DRV_NAME,
577         .id_table               = ahci_pci_tbl,
578         .probe                  = ahci_init_one,
579         .remove                 = ahci_remove_one,
580         .driver = {
581                 .pm             = &ahci_pci_pm_ops,
582         },
583 };
584 
585 #if IS_ENABLED(CONFIG_PATA_MARVELL)
586 static int marvell_enable;
587 #else
588 static int marvell_enable = 1;
589 #endif
590 module_param(marvell_enable, int, 0644);
591 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
592 
593 
594 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
595                                          struct ahci_host_priv *hpriv)
596 {
597         if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
598                 dev_info(&pdev->dev, "JMB361 has only one port\n");
599                 hpriv->force_port_map = 1;
600         }
601 
602         /*
603          * Temporary Marvell 6145 hack: PATA port presence
604          * is asserted through the standard AHCI port
605          * presence register, as bit 4 (counting from 0)
606          */
607         if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
608                 if (pdev->device == 0x6121)
609                         hpriv->mask_port_map = 0x3;
610                 else
611                         hpriv->mask_port_map = 0xf;
612                 dev_info(&pdev->dev,
613                           "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
614         }
615 
616         ahci_save_initial_config(&pdev->dev, hpriv);
617 }
618 
619 static int ahci_pci_reset_controller(struct ata_host *host)
620 {
621         struct pci_dev *pdev = to_pci_dev(host->dev);
622 
623         ahci_reset_controller(host);
624 
625         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
626                 struct ahci_host_priv *hpriv = host->private_data;
627                 u16 tmp16;
628 
629                 /* configure PCS */
630                 pci_read_config_word(pdev, 0x92, &tmp16);
631                 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
632                         tmp16 |= hpriv->port_map;
633                         pci_write_config_word(pdev, 0x92, tmp16);
634                 }
635         }
636 
637         return 0;
638 }
639 
640 static void ahci_pci_init_controller(struct ata_host *host)
641 {
642         struct ahci_host_priv *hpriv = host->private_data;
643         struct pci_dev *pdev = to_pci_dev(host->dev);
644         void __iomem *port_mmio;
645         u32 tmp;
646         int mv;
647 
648         if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
649                 if (pdev->device == 0x6121)
650                         mv = 2;
651                 else
652                         mv = 4;
653                 port_mmio = __ahci_port_base(host, mv);
654 
655                 writel(0, port_mmio + PORT_IRQ_MASK);
656 
657                 /* clear port IRQ */
658                 tmp = readl(port_mmio + PORT_IRQ_STAT);
659                 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
660                 if (tmp)
661                         writel(tmp, port_mmio + PORT_IRQ_STAT);
662         }
663 
664         ahci_init_controller(host);
665 }
666 
667 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
668                                  unsigned long deadline)
669 {
670         struct ata_port *ap = link->ap;
671         struct ahci_host_priv *hpriv = ap->host->private_data;
672         bool online;
673         int rc;
674 
675         DPRINTK("ENTER\n");
676 
677         ahci_stop_engine(ap);
678 
679         rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
680                                  deadline, &online, NULL);
681 
682         hpriv->start_engine(ap);
683 
684         DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
685 
686         /* vt8251 doesn't clear BSY on signature FIS reception,
687          * request follow-up softreset.
688          */
689         return online ? -EAGAIN : rc;
690 }
691 
692 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
693                                 unsigned long deadline)
694 {
695         struct ata_port *ap = link->ap;
696         struct ahci_port_priv *pp = ap->private_data;
697         struct ahci_host_priv *hpriv = ap->host->private_data;
698         u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
699         struct ata_taskfile tf;
700         bool online;
701         int rc;
702 
703         ahci_stop_engine(ap);
704 
705         /* clear D2H reception area to properly wait for D2H FIS */
706         ata_tf_init(link->device, &tf);
707         tf.command = ATA_BUSY;
708         ata_tf_to_fis(&tf, 0, 0, d2h_fis);
709 
710         rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
711                                  deadline, &online, NULL);
712 
713         hpriv->start_engine(ap);
714 
715         /* The pseudo configuration device on SIMG4726 attached to
716          * ASUS P5W-DH Deluxe doesn't send signature FIS after
717          * hardreset if no device is attached to the first downstream
718          * port && the pseudo device locks up on SRST w/ PMP==0.  To
719          * work around this, wait for !BSY only briefly.  If BSY isn't
720          * cleared, perform CLO and proceed to IDENTIFY (achieved by
721          * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
722          *
723          * Wait for two seconds.  Devices attached to downstream port
724          * which can't process the following IDENTIFY after this will
725          * have to be reset again.  For most cases, this should
726          * suffice while making probing snappish enough.
727          */
728         if (online) {
729                 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
730                                           ahci_check_ready);
731                 if (rc)
732                         ahci_kick_engine(ap);
733         }
734         return rc;
735 }
736 
737 /*
738  * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
739  *
740  * It has been observed with some SSDs that the timing of events in the
741  * link synchronization phase can leave the port in a state that can not
742  * be recovered by a SATA-hard-reset alone.  The failing signature is
743  * SStatus.DET stuck at 1 ("Device presence detected but Phy
744  * communication not established").  It was found that unloading and
745  * reloading the driver when this problem occurs allows the drive
746  * connection to be recovered (DET advanced to 0x3).  The critical
747  * component of reloading the driver is that the port state machines are
748  * reset by bouncing "port enable" in the AHCI PCS configuration
749  * register.  So, reproduce that effect by bouncing a port whenever we
750  * see DET==1 after a reset.
751  */
752 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
753                               unsigned long deadline)
754 {
755         const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
756         struct ata_port *ap = link->ap;
757         struct ahci_port_priv *pp = ap->private_data;
758         struct ahci_host_priv *hpriv = ap->host->private_data;
759         u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
760         unsigned long tmo = deadline - jiffies;
761         struct ata_taskfile tf;
762         bool online;
763         int rc, i;
764 
765         DPRINTK("ENTER\n");
766 
767         ahci_stop_engine(ap);
768 
769         for (i = 0; i < 2; i++) {
770                 u16 val;
771                 u32 sstatus;
772                 int port = ap->port_no;
773                 struct ata_host *host = ap->host;
774                 struct pci_dev *pdev = to_pci_dev(host->dev);
775 
776                 /* clear D2H reception area to properly wait for D2H FIS */
777                 ata_tf_init(link->device, &tf);
778                 tf.command = ATA_BUSY;
779                 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
780 
781                 rc = sata_link_hardreset(link, timing, deadline, &online,
782                                 ahci_check_ready);
783 
784                 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
785                                 (sstatus & 0xf) != 1)
786                         break;
787 
788                 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
789                                 port);
790 
791                 pci_read_config_word(pdev, 0x92, &val);
792                 val &= ~(1 << port);
793                 pci_write_config_word(pdev, 0x92, val);
794                 ata_msleep(ap, 1000);
795                 val |= 1 << port;
796                 pci_write_config_word(pdev, 0x92, val);
797                 deadline += tmo;
798         }
799 
800         hpriv->start_engine(ap);
801 
802         if (online)
803                 *class = ahci_dev_classify(ap);
804 
805         DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
806         return rc;
807 }
808 
809 
810 #ifdef CONFIG_PM
811 static void ahci_pci_disable_interrupts(struct ata_host *host)
812 {
813         struct ahci_host_priv *hpriv = host->private_data;
814         void __iomem *mmio = hpriv->mmio;
815         u32 ctl;
816 
817         /* AHCI spec rev1.1 section 8.3.3:
818          * Software must disable interrupts prior to requesting a
819          * transition of the HBA to D3 state.
820          */
821         ctl = readl(mmio + HOST_CTL);
822         ctl &= ~HOST_IRQ_EN;
823         writel(ctl, mmio + HOST_CTL);
824         readl(mmio + HOST_CTL); /* flush */
825 }
826 
827 static int ahci_pci_device_runtime_suspend(struct device *dev)
828 {
829         struct pci_dev *pdev = to_pci_dev(dev);
830         struct ata_host *host = pci_get_drvdata(pdev);
831 
832         ahci_pci_disable_interrupts(host);
833         return 0;
834 }
835 
836 static int ahci_pci_device_runtime_resume(struct device *dev)
837 {
838         struct pci_dev *pdev = to_pci_dev(dev);
839         struct ata_host *host = pci_get_drvdata(pdev);
840         int rc;
841 
842         rc = ahci_pci_reset_controller(host);
843         if (rc)
844                 return rc;
845         ahci_pci_init_controller(host);
846         return 0;
847 }
848 
849 #ifdef CONFIG_PM_SLEEP
850 static int ahci_pci_device_suspend(struct device *dev)
851 {
852         struct pci_dev *pdev = to_pci_dev(dev);
853         struct ata_host *host = pci_get_drvdata(pdev);
854         struct ahci_host_priv *hpriv = host->private_data;
855 
856         if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
857                 dev_err(&pdev->dev,
858                         "BIOS update required for suspend/resume\n");
859                 return -EIO;
860         }
861 
862         ahci_pci_disable_interrupts(host);
863         return ata_host_suspend(host, PMSG_SUSPEND);
864 }
865 
866 static int ahci_pci_device_resume(struct device *dev)
867 {
868         struct pci_dev *pdev = to_pci_dev(dev);
869         struct ata_host *host = pci_get_drvdata(pdev);
870         int rc;
871 
872         /* Apple BIOS helpfully mangles the registers on resume */
873         if (is_mcp89_apple(pdev))
874                 ahci_mcp89_apple_enable(pdev);
875 
876         if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
877                 rc = ahci_pci_reset_controller(host);
878                 if (rc)
879                         return rc;
880 
881                 ahci_pci_init_controller(host);
882         }
883 
884         ata_host_resume(host);
885 
886         return 0;
887 }
888 #endif
889 
890 #endif /* CONFIG_PM */
891 
892 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
893 {
894         int rc;
895 
896         /*
897          * If the device fixup already set the dma_mask to some non-standard
898          * value, don't extend it here. This happens on STA2X11, for example.
899          */
900         if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
901                 return 0;
902 
903         if (using_dac &&
904             !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
905                 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
906                 if (rc) {
907                         rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
908                         if (rc) {
909                                 dev_err(&pdev->dev,
910                                         "64-bit DMA enable failed\n");
911                                 return rc;
912                         }
913                 }
914         } else {
915                 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
916                 if (rc) {
917                         dev_err(&pdev->dev, "32-bit DMA enable failed\n");
918                         return rc;
919                 }
920                 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
921                 if (rc) {
922                         dev_err(&pdev->dev,
923                                 "32-bit consistent DMA enable failed\n");
924                         return rc;
925                 }
926         }
927         return 0;
928 }
929 
930 static void ahci_pci_print_info(struct ata_host *host)
931 {
932         struct pci_dev *pdev = to_pci_dev(host->dev);
933         u16 cc;
934         const char *scc_s;
935 
936         pci_read_config_word(pdev, 0x0a, &cc);
937         if (cc == PCI_CLASS_STORAGE_IDE)
938                 scc_s = "IDE";
939         else if (cc == PCI_CLASS_STORAGE_SATA)
940                 scc_s = "SATA";
941         else if (cc == PCI_CLASS_STORAGE_RAID)
942                 scc_s = "RAID";
943         else
944                 scc_s = "unknown";
945 
946         ahci_print_info(host, scc_s);
947 }
948 
949 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
950  * hardwired to on-board SIMG 4726.  The chipset is ICH8 and doesn't
951  * support PMP and the 4726 either directly exports the device
952  * attached to the first downstream port or acts as a hardware storage
953  * controller and emulate a single ATA device (can be RAID 0/1 or some
954  * other configuration).
955  *
956  * When there's no device attached to the first downstream port of the
957  * 4726, "Config Disk" appears, which is a pseudo ATA device to
958  * configure the 4726.  However, ATA emulation of the device is very
959  * lame.  It doesn't send signature D2H Reg FIS after the initial
960  * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
961  *
962  * The following function works around the problem by always using
963  * hardreset on the port and not depending on receiving signature FIS
964  * afterward.  If signature FIS isn't received soon, ATA class is
965  * assumed without follow-up softreset.
966  */
967 static void ahci_p5wdh_workaround(struct ata_host *host)
968 {
969         static const struct dmi_system_id sysids[] = {
970                 {
971                         .ident = "P5W DH Deluxe",
972                         .matches = {
973                                 DMI_MATCH(DMI_SYS_VENDOR,
974                                           "ASUSTEK COMPUTER INC"),
975                                 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
976                         },
977                 },
978                 { }
979         };
980         struct pci_dev *pdev = to_pci_dev(host->dev);
981 
982         if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
983             dmi_check_system(sysids)) {
984                 struct ata_port *ap = host->ports[1];
985 
986                 dev_info(&pdev->dev,
987                          "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
988 
989                 ap->ops = &ahci_p5wdh_ops;
990                 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
991         }
992 }
993 
994 /*
995  * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
996  * booting in BIOS compatibility mode.  We restore the registers but not ID.
997  */
998 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
999 {
1000         u32 val;
1001 
1002         printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1003 
1004         pci_read_config_dword(pdev, 0xf8, &val);
1005         val |= 1 << 0x1b;
1006         /* the following changes the device ID, but appears not to affect function */
1007         /* val = (val & ~0xf0000000) | 0x80000000; */
1008         pci_write_config_dword(pdev, 0xf8, val);
1009 
1010         pci_read_config_dword(pdev, 0x54c, &val);
1011         val |= 1 << 0xc;
1012         pci_write_config_dword(pdev, 0x54c, val);
1013 
1014         pci_read_config_dword(pdev, 0x4a4, &val);
1015         val &= 0xff;
1016         val |= 0x01060100;
1017         pci_write_config_dword(pdev, 0x4a4, val);
1018 
1019         pci_read_config_dword(pdev, 0x54c, &val);
1020         val &= ~(1 << 0xc);
1021         pci_write_config_dword(pdev, 0x54c, val);
1022 
1023         pci_read_config_dword(pdev, 0xf8, &val);
1024         val &= ~(1 << 0x1b);
1025         pci_write_config_dword(pdev, 0xf8, val);
1026 }
1027 
1028 static bool is_mcp89_apple(struct pci_dev *pdev)
1029 {
1030         return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1031                 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1032                 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1033                 pdev->subsystem_device == 0xcb89;
1034 }
1035 
1036 /* only some SB600 ahci controllers can do 64bit DMA */
1037 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1038 {
1039         static const struct dmi_system_id sysids[] = {
1040                 /*
1041                  * The oldest version known to be broken is 0901 and
1042                  * working is 1501 which was released on 2007-10-26.
1043                  * Enable 64bit DMA on 1501 and anything newer.
1044                  *
1045                  * Please read bko#9412 for more info.
1046                  */
1047                 {
1048                         .ident = "ASUS M2A-VM",
1049                         .matches = {
1050                                 DMI_MATCH(DMI_BOARD_VENDOR,
1051                                           "ASUSTeK Computer INC."),
1052                                 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1053                         },
1054                         .driver_data = "20071026",      /* yyyymmdd */
1055                 },
1056                 /*
1057                  * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1058                  * support 64bit DMA.
1059                  *
1060                  * BIOS versions earlier than 1.5 had the Manufacturer DMI
1061                  * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1062                  * This spelling mistake was fixed in BIOS version 1.5, so
1063                  * 1.5 and later have the Manufacturer as
1064                  * "MICRO-STAR INTERNATIONAL CO.,LTD".
1065                  * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1066                  *
1067                  * BIOS versions earlier than 1.9 had a Board Product Name
1068                  * DMI field of "MS-7376". This was changed to be
1069                  * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1070                  * match on DMI_BOARD_NAME of "MS-7376".
1071                  */
1072                 {
1073                         .ident = "MSI K9A2 Platinum",
1074                         .matches = {
1075                                 DMI_MATCH(DMI_BOARD_VENDOR,
1076                                           "MICRO-STAR INTER"),
1077                                 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1078                         },
1079                 },
1080                 /*
1081                  * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1082                  * 64bit DMA.
1083                  *
1084                  * This board also had the typo mentioned above in the
1085                  * Manufacturer DMI field (fixed in BIOS version 1.5), so
1086                  * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1087                  */
1088                 {
1089                         .ident = "MSI K9AGM2",
1090                         .matches = {
1091                                 DMI_MATCH(DMI_BOARD_VENDOR,
1092                                           "MICRO-STAR INTER"),
1093                                 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1094                         },
1095                 },
1096                 /*
1097                  * All BIOS versions for the Asus M3A support 64bit DMA.
1098                  * (all release versions from 0301 to 1206 were tested)
1099                  */
1100                 {
1101                         .ident = "ASUS M3A",
1102                         .matches = {
1103                                 DMI_MATCH(DMI_BOARD_VENDOR,
1104                                           "ASUSTeK Computer INC."),
1105                                 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1106                         },
1107                 },
1108                 { }
1109         };
1110         const struct dmi_system_id *match;
1111         int year, month, date;
1112         char buf[9];
1113 
1114         match = dmi_first_match(sysids);
1115         if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1116             !match)
1117                 return false;
1118 
1119         if (!match->driver_data)
1120                 goto enable_64bit;
1121 
1122         dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1123         snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1124 
1125         if (strcmp(buf, match->driver_data) >= 0)
1126                 goto enable_64bit;
1127         else {
1128                 dev_warn(&pdev->dev,
1129                          "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1130                          match->ident);
1131                 return false;
1132         }
1133 
1134 enable_64bit:
1135         dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1136         return true;
1137 }
1138 
1139 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1140 {
1141         static const struct dmi_system_id broken_systems[] = {
1142                 {
1143                         .ident = "HP Compaq nx6310",
1144                         .matches = {
1145                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1146                                 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1147                         },
1148                         /* PCI slot number of the controller */
1149                         .driver_data = (void *)0x1FUL,
1150                 },
1151                 {
1152                         .ident = "HP Compaq 6720s",
1153                         .matches = {
1154                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1155                                 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1156                         },
1157                         /* PCI slot number of the controller */
1158                         .driver_data = (void *)0x1FUL,
1159                 },
1160 
1161                 { }     /* terminate list */
1162         };
1163         const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1164 
1165         if (dmi) {
1166                 unsigned long slot = (unsigned long)dmi->driver_data;
1167                 /* apply the quirk only to on-board controllers */
1168                 return slot == PCI_SLOT(pdev->devfn);
1169         }
1170 
1171         return false;
1172 }
1173 
1174 static bool ahci_broken_suspend(struct pci_dev *pdev)
1175 {
1176         static const struct dmi_system_id sysids[] = {
1177                 /*
1178                  * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1179                  * to the harddisk doesn't become online after
1180                  * resuming from STR.  Warn and fail suspend.
1181                  *
1182                  * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1183                  *
1184                  * Use dates instead of versions to match as HP is
1185                  * apparently recycling both product and version
1186                  * strings.
1187                  *
1188                  * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1189                  */
1190                 {
1191                         .ident = "dv4",
1192                         .matches = {
1193                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1194                                 DMI_MATCH(DMI_PRODUCT_NAME,
1195                                           "HP Pavilion dv4 Notebook PC"),
1196                         },
1197                         .driver_data = "20090105",      /* F.30 */
1198                 },
1199                 {
1200                         .ident = "dv5",
1201                         .matches = {
1202                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1203                                 DMI_MATCH(DMI_PRODUCT_NAME,
1204                                           "HP Pavilion dv5 Notebook PC"),
1205                         },
1206                         .driver_data = "20090506",      /* F.16 */
1207                 },
1208                 {
1209                         .ident = "dv6",
1210                         .matches = {
1211                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1212                                 DMI_MATCH(DMI_PRODUCT_NAME,
1213                                           "HP Pavilion dv6 Notebook PC"),
1214                         },
1215                         .driver_data = "20090423",      /* F.21 */
1216                 },
1217                 {
1218                         .ident = "HDX18",
1219                         .matches = {
1220                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1221                                 DMI_MATCH(DMI_PRODUCT_NAME,
1222                                           "HP HDX18 Notebook PC"),
1223                         },
1224                         .driver_data = "20090430",      /* F.23 */
1225                 },
1226                 /*
1227                  * Acer eMachines G725 has the same problem.  BIOS
1228                  * V1.03 is known to be broken.  V3.04 is known to
1229                  * work.  Between, there are V1.06, V2.06 and V3.03
1230                  * that we don't have much idea about.  For now,
1231                  * blacklist anything older than V3.04.
1232                  *
1233                  * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1234                  */
1235                 {
1236                         .ident = "G725",
1237                         .matches = {
1238                                 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1239                                 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1240                         },
1241                         .driver_data = "20091216",      /* V3.04 */
1242                 },
1243                 { }     /* terminate list */
1244         };
1245         const struct dmi_system_id *dmi = dmi_first_match(sysids);
1246         int year, month, date;
1247         char buf[9];
1248 
1249         if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1250                 return false;
1251 
1252         dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1253         snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1254 
1255         return strcmp(buf, dmi->driver_data) < 0;
1256 }
1257 
1258 static bool ahci_broken_online(struct pci_dev *pdev)
1259 {
1260 #define ENCODE_BUSDEVFN(bus, slot, func)                        \
1261         (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1262         static const struct dmi_system_id sysids[] = {
1263                 /*
1264                  * There are several gigabyte boards which use
1265                  * SIMG5723s configured as hardware RAID.  Certain
1266                  * 5723 firmware revisions shipped there keep the link
1267                  * online but fail to answer properly to SRST or
1268                  * IDENTIFY when no device is attached downstream
1269                  * causing libata to retry quite a few times leading
1270                  * to excessive detection delay.
1271                  *
1272                  * As these firmwares respond to the second reset try
1273                  * with invalid device signature, considering unknown
1274                  * sig as offline works around the problem acceptably.
1275                  */
1276                 {
1277                         .ident = "EP45-DQ6",
1278                         .matches = {
1279                                 DMI_MATCH(DMI_BOARD_VENDOR,
1280                                           "Gigabyte Technology Co., Ltd."),
1281                                 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1282                         },
1283                         .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1284                 },
1285                 {
1286                         .ident = "EP45-DS5",
1287                         .matches = {
1288                                 DMI_MATCH(DMI_BOARD_VENDOR,
1289                                           "Gigabyte Technology Co., Ltd."),
1290                                 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1291                         },
1292                         .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1293                 },
1294                 { }     /* terminate list */
1295         };
1296 #undef ENCODE_BUSDEVFN
1297         const struct dmi_system_id *dmi = dmi_first_match(sysids);
1298         unsigned int val;
1299 
1300         if (!dmi)
1301                 return false;
1302 
1303         val = (unsigned long)dmi->driver_data;
1304 
1305         return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1306 }
1307 
1308 static bool ahci_broken_devslp(struct pci_dev *pdev)
1309 {
1310         /* device with broken DEVSLP but still showing SDS capability */
1311         static const struct pci_device_id ids[] = {
1312                 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1313                 {}
1314         };
1315 
1316         return pci_match_id(ids, pdev);
1317 }
1318 
1319 #ifdef CONFIG_ATA_ACPI
1320 static void ahci_gtf_filter_workaround(struct ata_host *host)
1321 {
1322         static const struct dmi_system_id sysids[] = {
1323                 /*
1324                  * Aspire 3810T issues a bunch of SATA enable commands
1325                  * via _GTF including an invalid one and one which is
1326                  * rejected by the device.  Among the successful ones
1327                  * is FPDMA non-zero offset enable which when enabled
1328                  * only on the drive side leads to NCQ command
1329                  * failures.  Filter it out.
1330                  */
1331                 {
1332                         .ident = "Aspire 3810T",
1333                         .matches = {
1334                                 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1335                                 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1336                         },
1337                         .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1338                 },
1339                 { }
1340         };
1341         const struct dmi_system_id *dmi = dmi_first_match(sysids);
1342         unsigned int filter;
1343         int i;
1344 
1345         if (!dmi)
1346                 return;
1347 
1348         filter = (unsigned long)dmi->driver_data;
1349         dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1350                  filter, dmi->ident);
1351 
1352         for (i = 0; i < host->n_ports; i++) {
1353                 struct ata_port *ap = host->ports[i];
1354                 struct ata_link *link;
1355                 struct ata_device *dev;
1356 
1357                 ata_for_each_link(link, ap, EDGE)
1358                         ata_for_each_dev(dev, link, ALL)
1359                                 dev->gtf_filter |= filter;
1360         }
1361 }
1362 #else
1363 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1364 {}
1365 #endif
1366 
1367 #ifdef CONFIG_ARM64
1368 /*
1369  * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1370  * Workaround is to make sure all pending IRQs are served before leaving
1371  * handler.
1372  */
1373 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1374 {
1375         struct ata_host *host = dev_instance;
1376         struct ahci_host_priv *hpriv;
1377         unsigned int rc = 0;
1378         void __iomem *mmio;
1379         u32 irq_stat, irq_masked;
1380         unsigned int handled = 1;
1381 
1382         VPRINTK("ENTER\n");
1383         hpriv = host->private_data;
1384         mmio = hpriv->mmio;
1385         irq_stat = readl(mmio + HOST_IRQ_STAT);
1386         if (!irq_stat)
1387                 return IRQ_NONE;
1388 
1389         do {
1390                 irq_masked = irq_stat & hpriv->port_map;
1391                 spin_lock(&host->lock);
1392                 rc = ahci_handle_port_intr(host, irq_masked);
1393                 if (!rc)
1394                         handled = 0;
1395                 writel(irq_stat, mmio + HOST_IRQ_STAT);
1396                 irq_stat = readl(mmio + HOST_IRQ_STAT);
1397                 spin_unlock(&host->lock);
1398         } while (irq_stat);
1399         VPRINTK("EXIT\n");
1400 
1401         return IRQ_RETVAL(handled);
1402 }
1403 #endif
1404 
1405 static void ahci_remap_check(struct pci_dev *pdev, int bar,
1406                 struct ahci_host_priv *hpriv)
1407 {
1408         int i, count = 0;
1409         u32 cap;
1410 
1411         /*
1412          * Check if this device might have remapped nvme devices.
1413          */
1414         if (pdev->vendor != PCI_VENDOR_ID_INTEL ||
1415             pci_resource_len(pdev, bar) < SZ_512K ||
1416             bar != AHCI_PCI_BAR_STANDARD ||
1417             !(readl(hpriv->mmio + AHCI_VSCAP) & 1))
1418                 return;
1419 
1420         cap = readq(hpriv->mmio + AHCI_REMAP_CAP);
1421         for (i = 0; i < AHCI_MAX_REMAP; i++) {
1422                 if ((cap & (1 << i)) == 0)
1423                         continue;
1424                 if (readl(hpriv->mmio + ahci_remap_dcc(i))
1425                                 != PCI_CLASS_STORAGE_EXPRESS)
1426                         continue;
1427 
1428                 /* We've found a remapped device */
1429                 count++;
1430         }
1431 
1432         if (!count)
1433                 return;
1434 
1435         dev_warn(&pdev->dev, "Found %d remapped NVMe devices.\n", count);
1436         dev_warn(&pdev->dev, "Switch your BIOS from RAID to AHCI mode to use them.\n");
1437 }
1438 
1439 static int ahci_get_irq_vector(struct ata_host *host, int port)
1440 {
1441         return pci_irq_vector(to_pci_dev(host->dev), port);
1442 }
1443 
1444 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1445                         struct ahci_host_priv *hpriv)
1446 {
1447         int nvec;
1448 
1449         if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1450                 return -ENODEV;
1451 
1452         /*
1453          * If number of MSIs is less than number of ports then Sharing Last
1454          * Message mode could be enforced. In this case assume that advantage
1455          * of multipe MSIs is negated and use single MSI mode instead.
1456          */
1457         if (n_ports > 1) {
1458                 nvec = pci_alloc_irq_vectors(pdev, n_ports, INT_MAX,
1459                                 PCI_IRQ_MSIX | PCI_IRQ_MSI);
1460                 if (nvec > 0) {
1461                         if (!(readl(hpriv->mmio + HOST_CTL) & HOST_MRSM)) {
1462                                 hpriv->get_irq_vector = ahci_get_irq_vector;
1463                                 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1464                                 return nvec;
1465                         }
1466 
1467                         /*
1468                          * Fallback to single MSI mode if the controller
1469                          * enforced MRSM mode.
1470                          */
1471                         printk(KERN_INFO
1472                                 "ahci: MRSM is on, fallback to single MSI\n");
1473                         pci_free_irq_vectors(pdev);
1474                 }
1475         }
1476 
1477         /*
1478          * If the host is not capable of supporting per-port vectors, fall
1479          * back to single MSI before finally attempting single MSI-X.
1480          */
1481         nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI);
1482         if (nvec == 1)
1483                 return nvec;
1484         return pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSIX);
1485 }
1486 
1487 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1488 {
1489         unsigned int board_id = ent->driver_data;
1490         struct ata_port_info pi = ahci_port_info[board_id];
1491         const struct ata_port_info *ppi[] = { &pi, NULL };
1492         struct device *dev = &pdev->dev;
1493         struct ahci_host_priv *hpriv;
1494         struct ata_host *host;
1495         int n_ports, i, rc;
1496         int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1497 
1498         VPRINTK("ENTER\n");
1499 
1500         WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1501 
1502         ata_print_version_once(&pdev->dev, DRV_VERSION);
1503 
1504         /* The AHCI driver can only drive the SATA ports, the PATA driver
1505            can drive them all so if both drivers are selected make sure
1506            AHCI stays out of the way */
1507         if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1508                 return -ENODEV;
1509 
1510         /* Apple BIOS on MCP89 prevents us using AHCI */
1511         if (is_mcp89_apple(pdev))
1512                 ahci_mcp89_apple_enable(pdev);
1513 
1514         /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1515          * At the moment, we can only use the AHCI mode. Let the users know
1516          * that for SAS drives they're out of luck.
1517          */
1518         if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1519                 dev_info(&pdev->dev,
1520                          "PDC42819 can only drive SATA devices with this driver\n");
1521 
1522         /* Some devices use non-standard BARs */
1523         if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1524                 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1525         else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1526                 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1527         else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1528                 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1529 
1530         /* acquire resources */
1531         rc = pcim_enable_device(pdev);
1532         if (rc)
1533                 return rc;
1534 
1535         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1536             (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1537                 u8 map;
1538 
1539                 /* ICH6s share the same PCI ID for both piix and ahci
1540                  * modes.  Enabling ahci mode while MAP indicates
1541                  * combined mode is a bad idea.  Yield to ata_piix.
1542                  */
1543                 pci_read_config_byte(pdev, ICH_MAP, &map);
1544                 if (map & 0x3) {
1545                         dev_info(&pdev->dev,
1546                                  "controller is in combined mode, can't enable AHCI mode\n");
1547                         return -ENODEV;
1548                 }
1549         }
1550 
1551         /* AHCI controllers often implement SFF compatible interface.
1552          * Grab all PCI BARs just in case.
1553          */
1554         rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1555         if (rc == -EBUSY)
1556                 pcim_pin_device(pdev);
1557         if (rc)
1558                 return rc;
1559 
1560         hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1561         if (!hpriv)
1562                 return -ENOMEM;
1563         hpriv->flags |= (unsigned long)pi.private_data;
1564 
1565         /* MCP65 revision A1 and A2 can't do MSI */
1566         if (board_id == board_ahci_mcp65 &&
1567             (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1568                 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1569 
1570         /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1571         if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1572                 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1573 
1574         /* only some SB600s can do 64bit DMA */
1575         if (ahci_sb600_enable_64bit(pdev))
1576                 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1577 
1578         hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1579 
1580         /* detect remapped nvme devices */
1581         ahci_remap_check(pdev, ahci_pci_bar, hpriv);
1582 
1583         /* must set flag prior to save config in order to take effect */
1584         if (ahci_broken_devslp(pdev))
1585                 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1586 
1587 #ifdef CONFIG_ARM64
1588         if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1589                 hpriv->irq_handler = ahci_thunderx_irq_handler;
1590 #endif
1591 
1592         /* save initial config */
1593         ahci_pci_save_initial_config(pdev, hpriv);
1594 
1595         /* prepare host */
1596         if (hpriv->cap & HOST_CAP_NCQ) {
1597                 pi.flags |= ATA_FLAG_NCQ;
1598                 /*
1599                  * Auto-activate optimization is supposed to be
1600                  * supported on all AHCI controllers indicating NCQ
1601                  * capability, but it seems to be broken on some
1602                  * chipsets including NVIDIAs.
1603                  */
1604                 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1605                         pi.flags |= ATA_FLAG_FPDMA_AA;
1606 
1607                 /*
1608                  * All AHCI controllers should be forward-compatible
1609                  * with the new auxiliary field. This code should be
1610                  * conditionalized if any buggy AHCI controllers are
1611                  * encountered.
1612                  */
1613                 pi.flags |= ATA_FLAG_FPDMA_AUX;
1614         }
1615 
1616         if (hpriv->cap & HOST_CAP_PMP)
1617                 pi.flags |= ATA_FLAG_PMP;
1618 
1619         ahci_set_em_messages(hpriv, &pi);
1620 
1621         if (ahci_broken_system_poweroff(pdev)) {
1622                 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1623                 dev_info(&pdev->dev,
1624                         "quirky BIOS, skipping spindown on poweroff\n");
1625         }
1626 
1627         if (ahci_broken_suspend(pdev)) {
1628                 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1629                 dev_warn(&pdev->dev,
1630                          "BIOS update required for suspend/resume\n");
1631         }
1632 
1633         if (ahci_broken_online(pdev)) {
1634                 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1635                 dev_info(&pdev->dev,
1636                          "online status unreliable, applying workaround\n");
1637         }
1638 
1639         /* CAP.NP sometimes indicate the index of the last enabled
1640          * port, at other times, that of the last possible port, so
1641          * determining the maximum port number requires looking at
1642          * both CAP.NP and port_map.
1643          */
1644         n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1645 
1646         host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1647         if (!host)
1648                 return -ENOMEM;
1649         host->private_data = hpriv;
1650 
1651         if (ahci_init_msi(pdev, n_ports, hpriv) < 0) {
1652                 /* legacy intx interrupts */
1653                 pci_intx(pdev, 1);
1654         }
1655         hpriv->irq = pci_irq_vector(pdev, 0);
1656 
1657         if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1658                 host->flags |= ATA_HOST_PARALLEL_SCAN;
1659         else
1660                 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1661 
1662         if (pi.flags & ATA_FLAG_EM)
1663                 ahci_reset_em(host);
1664 
1665         for (i = 0; i < host->n_ports; i++) {
1666                 struct ata_port *ap = host->ports[i];
1667 
1668                 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1669                 ata_port_pbar_desc(ap, ahci_pci_bar,
1670                                    0x100 + ap->port_no * 0x80, "port");
1671 
1672                 /* set enclosure management message type */
1673                 if (ap->flags & ATA_FLAG_EM)
1674                         ap->em_message_type = hpriv->em_msg_type;
1675 
1676 
1677                 /* disabled/not-implemented port */
1678                 if (!(hpriv->port_map & (1 << i)))
1679                         ap->ops = &ata_dummy_port_ops;
1680         }
1681 
1682         /* apply workaround for ASUS P5W DH Deluxe mainboard */
1683         ahci_p5wdh_workaround(host);
1684 
1685         /* apply gtf filter quirk */
1686         ahci_gtf_filter_workaround(host);
1687 
1688         /* initialize adapter */
1689         rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1690         if (rc)
1691                 return rc;
1692 
1693         rc = ahci_pci_reset_controller(host);
1694         if (rc)
1695                 return rc;
1696 
1697         ahci_pci_init_controller(host);
1698         ahci_pci_print_info(host);
1699 
1700         pci_set_master(pdev);
1701 
1702         rc = ahci_host_activate(host, &ahci_sht);
1703         if (rc)
1704                 return rc;
1705 
1706         pm_runtime_put_noidle(&pdev->dev);
1707         return 0;
1708 }
1709 
1710 static void ahci_remove_one(struct pci_dev *pdev)
1711 {
1712         pm_runtime_get_noresume(&pdev->dev);
1713         ata_pci_remove_one(pdev);
1714 }
1715 
1716 module_pci_driver(ahci_pci_driver);
1717 
1718 MODULE_AUTHOR("Jeff Garzik");
1719 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1720 MODULE_LICENSE("GPL");
1721 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1722 MODULE_VERSION(DRV_VERSION);
1723 

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