Version:  2.0.40 2.2.26 2.4.37 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6

Linux/drivers/ata/ahci.c

  1 /*
  2  *  ahci.c - AHCI SATA support
  3  *
  4  *  Maintained by:  Tejun Heo <tj@kernel.org>
  5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  6  *                  on emails.
  7  *
  8  *  Copyright 2004-2005 Red Hat, Inc.
  9  *
 10  *
 11  *  This program is free software; you can redistribute it and/or modify
 12  *  it under the terms of the GNU General Public License as published by
 13  *  the Free Software Foundation; either version 2, or (at your option)
 14  *  any later version.
 15  *
 16  *  This program is distributed in the hope that it will be useful,
 17  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 18  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 19  *  GNU General Public License for more details.
 20  *
 21  *  You should have received a copy of the GNU General Public License
 22  *  along with this program; see the file COPYING.  If not, write to
 23  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 24  *
 25  *
 26  * libata documentation is available via 'make {ps|pdf}docs',
 27  * as Documentation/DocBook/libata.*
 28  *
 29  * AHCI hardware documentation:
 30  * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
 31  * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
 32  *
 33  */
 34 
 35 #include <linux/kernel.h>
 36 #include <linux/module.h>
 37 #include <linux/pci.h>
 38 #include <linux/blkdev.h>
 39 #include <linux/delay.h>
 40 #include <linux/interrupt.h>
 41 #include <linux/dma-mapping.h>
 42 #include <linux/device.h>
 43 #include <linux/dmi.h>
 44 #include <linux/gfp.h>
 45 #include <linux/msi.h>
 46 #include <scsi/scsi_host.h>
 47 #include <scsi/scsi_cmnd.h>
 48 #include <linux/libata.h>
 49 #include "ahci.h"
 50 
 51 #define DRV_NAME        "ahci"
 52 #define DRV_VERSION     "3.0"
 53 
 54 enum {
 55         AHCI_PCI_BAR_STA2X11    = 0,
 56         AHCI_PCI_BAR_CAVIUM     = 0,
 57         AHCI_PCI_BAR_ENMOTUS    = 2,
 58         AHCI_PCI_BAR_STANDARD   = 5,
 59 };
 60 
 61 enum board_ids {
 62         /* board IDs by feature in alphabetical order */
 63         board_ahci,
 64         board_ahci_ign_iferr,
 65         board_ahci_nomsi,
 66         board_ahci_noncq,
 67         board_ahci_nosntf,
 68         board_ahci_yes_fbs,
 69 
 70         /* board IDs for specific chipsets in alphabetical order */
 71         board_ahci_avn,
 72         board_ahci_mcp65,
 73         board_ahci_mcp77,
 74         board_ahci_mcp89,
 75         board_ahci_mv,
 76         board_ahci_sb600,
 77         board_ahci_sb700,       /* for SB700 and SB800 */
 78         board_ahci_vt8251,
 79 
 80         /* aliases */
 81         board_ahci_mcp_linux    = board_ahci_mcp65,
 82         board_ahci_mcp67        = board_ahci_mcp65,
 83         board_ahci_mcp73        = board_ahci_mcp65,
 84         board_ahci_mcp79        = board_ahci_mcp77,
 85 };
 86 
 87 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
 88 static void ahci_remove_one(struct pci_dev *dev);
 89 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
 90                                  unsigned long deadline);
 91 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
 92                               unsigned long deadline);
 93 static void ahci_mcp89_apple_enable(struct pci_dev *pdev);
 94 static bool is_mcp89_apple(struct pci_dev *pdev);
 95 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
 96                                 unsigned long deadline);
 97 #ifdef CONFIG_PM
 98 static int ahci_pci_device_runtime_suspend(struct device *dev);
 99 static int ahci_pci_device_runtime_resume(struct device *dev);
100 #ifdef CONFIG_PM_SLEEP
101 static int ahci_pci_device_suspend(struct device *dev);
102 static int ahci_pci_device_resume(struct device *dev);
103 #endif
104 #endif /* CONFIG_PM */
105 
106 static struct scsi_host_template ahci_sht = {
107         AHCI_SHT("ahci"),
108 };
109 
110 static struct ata_port_operations ahci_vt8251_ops = {
111         .inherits               = &ahci_ops,
112         .hardreset              = ahci_vt8251_hardreset,
113 };
114 
115 static struct ata_port_operations ahci_p5wdh_ops = {
116         .inherits               = &ahci_ops,
117         .hardreset              = ahci_p5wdh_hardreset,
118 };
119 
120 static struct ata_port_operations ahci_avn_ops = {
121         .inherits               = &ahci_ops,
122         .hardreset              = ahci_avn_hardreset,
123 };
124 
125 static const struct ata_port_info ahci_port_info[] = {
126         /* by features */
127         [board_ahci] = {
128                 .flags          = AHCI_FLAG_COMMON,
129                 .pio_mask       = ATA_PIO4,
130                 .udma_mask      = ATA_UDMA6,
131                 .port_ops       = &ahci_ops,
132         },
133         [board_ahci_ign_iferr] = {
134                 AHCI_HFLAGS     (AHCI_HFLAG_IGN_IRQ_IF_ERR),
135                 .flags          = AHCI_FLAG_COMMON,
136                 .pio_mask       = ATA_PIO4,
137                 .udma_mask      = ATA_UDMA6,
138                 .port_ops       = &ahci_ops,
139         },
140         [board_ahci_nomsi] = {
141                 AHCI_HFLAGS     (AHCI_HFLAG_NO_MSI),
142                 .flags          = AHCI_FLAG_COMMON,
143                 .pio_mask       = ATA_PIO4,
144                 .udma_mask      = ATA_UDMA6,
145                 .port_ops       = &ahci_ops,
146         },
147         [board_ahci_noncq] = {
148                 AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ),
149                 .flags          = AHCI_FLAG_COMMON,
150                 .pio_mask       = ATA_PIO4,
151                 .udma_mask      = ATA_UDMA6,
152                 .port_ops       = &ahci_ops,
153         },
154         [board_ahci_nosntf] = {
155                 AHCI_HFLAGS     (AHCI_HFLAG_NO_SNTF),
156                 .flags          = AHCI_FLAG_COMMON,
157                 .pio_mask       = ATA_PIO4,
158                 .udma_mask      = ATA_UDMA6,
159                 .port_ops       = &ahci_ops,
160         },
161         [board_ahci_yes_fbs] = {
162                 AHCI_HFLAGS     (AHCI_HFLAG_YES_FBS),
163                 .flags          = AHCI_FLAG_COMMON,
164                 .pio_mask       = ATA_PIO4,
165                 .udma_mask      = ATA_UDMA6,
166                 .port_ops       = &ahci_ops,
167         },
168         /* by chipsets */
169         [board_ahci_avn] = {
170                 .flags          = AHCI_FLAG_COMMON,
171                 .pio_mask       = ATA_PIO4,
172                 .udma_mask      = ATA_UDMA6,
173                 .port_ops       = &ahci_avn_ops,
174         },
175         [board_ahci_mcp65] = {
176                 AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP |
177                                  AHCI_HFLAG_YES_NCQ),
178                 .flags          = AHCI_FLAG_COMMON | ATA_FLAG_NO_DIPM,
179                 .pio_mask       = ATA_PIO4,
180                 .udma_mask      = ATA_UDMA6,
181                 .port_ops       = &ahci_ops,
182         },
183         [board_ahci_mcp77] = {
184                 AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA | AHCI_HFLAG_NO_PMP),
185                 .flags          = AHCI_FLAG_COMMON,
186                 .pio_mask       = ATA_PIO4,
187                 .udma_mask      = ATA_UDMA6,
188                 .port_ops       = &ahci_ops,
189         },
190         [board_ahci_mcp89] = {
191                 AHCI_HFLAGS     (AHCI_HFLAG_NO_FPDMA_AA),
192                 .flags          = AHCI_FLAG_COMMON,
193                 .pio_mask       = ATA_PIO4,
194                 .udma_mask      = ATA_UDMA6,
195                 .port_ops       = &ahci_ops,
196         },
197         [board_ahci_mv] = {
198                 AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_MSI |
199                                  AHCI_HFLAG_MV_PATA | AHCI_HFLAG_NO_PMP),
200                 .flags          = ATA_FLAG_SATA | ATA_FLAG_PIO_DMA,
201                 .pio_mask       = ATA_PIO4,
202                 .udma_mask      = ATA_UDMA6,
203                 .port_ops       = &ahci_ops,
204         },
205         [board_ahci_sb600] = {
206                 AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL |
207                                  AHCI_HFLAG_NO_MSI | AHCI_HFLAG_SECT255 |
208                                  AHCI_HFLAG_32BIT_ONLY),
209                 .flags          = AHCI_FLAG_COMMON,
210                 .pio_mask       = ATA_PIO4,
211                 .udma_mask      = ATA_UDMA6,
212                 .port_ops       = &ahci_pmp_retry_srst_ops,
213         },
214         [board_ahci_sb700] = {  /* for SB700 and SB800 */
215                 AHCI_HFLAGS     (AHCI_HFLAG_IGN_SERR_INTERNAL),
216                 .flags          = AHCI_FLAG_COMMON,
217                 .pio_mask       = ATA_PIO4,
218                 .udma_mask      = ATA_UDMA6,
219                 .port_ops       = &ahci_pmp_retry_srst_ops,
220         },
221         [board_ahci_vt8251] = {
222                 AHCI_HFLAGS     (AHCI_HFLAG_NO_NCQ | AHCI_HFLAG_NO_PMP),
223                 .flags          = AHCI_FLAG_COMMON,
224                 .pio_mask       = ATA_PIO4,
225                 .udma_mask      = ATA_UDMA6,
226                 .port_ops       = &ahci_vt8251_ops,
227         },
228 };
229 
230 static const struct pci_device_id ahci_pci_tbl[] = {
231         /* Intel */
232         { PCI_VDEVICE(INTEL, 0x2652), board_ahci }, /* ICH6 */
233         { PCI_VDEVICE(INTEL, 0x2653), board_ahci }, /* ICH6M */
234         { PCI_VDEVICE(INTEL, 0x27c1), board_ahci }, /* ICH7 */
235         { PCI_VDEVICE(INTEL, 0x27c5), board_ahci }, /* ICH7M */
236         { PCI_VDEVICE(INTEL, 0x27c3), board_ahci }, /* ICH7R */
237         { PCI_VDEVICE(AL, 0x5288), board_ahci_ign_iferr }, /* ULi M5288 */
238         { PCI_VDEVICE(INTEL, 0x2681), board_ahci }, /* ESB2 */
239         { PCI_VDEVICE(INTEL, 0x2682), board_ahci }, /* ESB2 */
240         { PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
241         { PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
242         { PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
243         { PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
244         { PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
245         { PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
246         { PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
247         { PCI_VDEVICE(INTEL, 0x2922), board_ahci }, /* ICH9 */
248         { PCI_VDEVICE(INTEL, 0x2923), board_ahci }, /* ICH9 */
249         { PCI_VDEVICE(INTEL, 0x2924), board_ahci }, /* ICH9 */
250         { PCI_VDEVICE(INTEL, 0x2925), board_ahci }, /* ICH9 */
251         { PCI_VDEVICE(INTEL, 0x2927), board_ahci }, /* ICH9 */
252         { PCI_VDEVICE(INTEL, 0x2929), board_ahci }, /* ICH9M */
253         { PCI_VDEVICE(INTEL, 0x292a), board_ahci }, /* ICH9M */
254         { PCI_VDEVICE(INTEL, 0x292b), board_ahci }, /* ICH9M */
255         { PCI_VDEVICE(INTEL, 0x292c), board_ahci }, /* ICH9M */
256         { PCI_VDEVICE(INTEL, 0x292f), board_ahci }, /* ICH9M */
257         { PCI_VDEVICE(INTEL, 0x294d), board_ahci }, /* ICH9 */
258         { PCI_VDEVICE(INTEL, 0x294e), board_ahci }, /* ICH9M */
259         { PCI_VDEVICE(INTEL, 0x502a), board_ahci }, /* Tolapai */
260         { PCI_VDEVICE(INTEL, 0x502b), board_ahci }, /* Tolapai */
261         { PCI_VDEVICE(INTEL, 0x3a05), board_ahci }, /* ICH10 */
262         { PCI_VDEVICE(INTEL, 0x3a22), board_ahci }, /* ICH10 */
263         { PCI_VDEVICE(INTEL, 0x3a25), board_ahci }, /* ICH10 */
264         { PCI_VDEVICE(INTEL, 0x3b22), board_ahci }, /* PCH AHCI */
265         { PCI_VDEVICE(INTEL, 0x3b23), board_ahci }, /* PCH AHCI */
266         { PCI_VDEVICE(INTEL, 0x3b24), board_ahci }, /* PCH RAID */
267         { PCI_VDEVICE(INTEL, 0x3b25), board_ahci }, /* PCH RAID */
268         { PCI_VDEVICE(INTEL, 0x3b29), board_ahci }, /* PCH AHCI */
269         { PCI_VDEVICE(INTEL, 0x3b2b), board_ahci }, /* PCH RAID */
270         { PCI_VDEVICE(INTEL, 0x3b2c), board_ahci }, /* PCH RAID */
271         { PCI_VDEVICE(INTEL, 0x3b2f), board_ahci }, /* PCH AHCI */
272         { PCI_VDEVICE(INTEL, 0x19b0), board_ahci }, /* DNV AHCI */
273         { PCI_VDEVICE(INTEL, 0x19b1), board_ahci }, /* DNV AHCI */
274         { PCI_VDEVICE(INTEL, 0x19b2), board_ahci }, /* DNV AHCI */
275         { PCI_VDEVICE(INTEL, 0x19b3), board_ahci }, /* DNV AHCI */
276         { PCI_VDEVICE(INTEL, 0x19b4), board_ahci }, /* DNV AHCI */
277         { PCI_VDEVICE(INTEL, 0x19b5), board_ahci }, /* DNV AHCI */
278         { PCI_VDEVICE(INTEL, 0x19b6), board_ahci }, /* DNV AHCI */
279         { PCI_VDEVICE(INTEL, 0x19b7), board_ahci }, /* DNV AHCI */
280         { PCI_VDEVICE(INTEL, 0x19bE), board_ahci }, /* DNV AHCI */
281         { PCI_VDEVICE(INTEL, 0x19bF), board_ahci }, /* DNV AHCI */
282         { PCI_VDEVICE(INTEL, 0x19c0), board_ahci }, /* DNV AHCI */
283         { PCI_VDEVICE(INTEL, 0x19c1), board_ahci }, /* DNV AHCI */
284         { PCI_VDEVICE(INTEL, 0x19c2), board_ahci }, /* DNV AHCI */
285         { PCI_VDEVICE(INTEL, 0x19c3), board_ahci }, /* DNV AHCI */
286         { PCI_VDEVICE(INTEL, 0x19c4), board_ahci }, /* DNV AHCI */
287         { PCI_VDEVICE(INTEL, 0x19c5), board_ahci }, /* DNV AHCI */
288         { PCI_VDEVICE(INTEL, 0x19c6), board_ahci }, /* DNV AHCI */
289         { PCI_VDEVICE(INTEL, 0x19c7), board_ahci }, /* DNV AHCI */
290         { PCI_VDEVICE(INTEL, 0x19cE), board_ahci }, /* DNV AHCI */
291         { PCI_VDEVICE(INTEL, 0x19cF), board_ahci }, /* DNV AHCI */
292         { PCI_VDEVICE(INTEL, 0x1c02), board_ahci }, /* CPT AHCI */
293         { PCI_VDEVICE(INTEL, 0x1c03), board_ahci }, /* CPT AHCI */
294         { PCI_VDEVICE(INTEL, 0x1c04), board_ahci }, /* CPT RAID */
295         { PCI_VDEVICE(INTEL, 0x1c05), board_ahci }, /* CPT RAID */
296         { PCI_VDEVICE(INTEL, 0x1c06), board_ahci }, /* CPT RAID */
297         { PCI_VDEVICE(INTEL, 0x1c07), board_ahci }, /* CPT RAID */
298         { PCI_VDEVICE(INTEL, 0x1d02), board_ahci }, /* PBG AHCI */
299         { PCI_VDEVICE(INTEL, 0x1d04), board_ahci }, /* PBG RAID */
300         { PCI_VDEVICE(INTEL, 0x1d06), board_ahci }, /* PBG RAID */
301         { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* PBG RAID */
302         { PCI_VDEVICE(INTEL, 0x2323), board_ahci }, /* DH89xxCC AHCI */
303         { PCI_VDEVICE(INTEL, 0x1e02), board_ahci }, /* Panther Point AHCI */
304         { PCI_VDEVICE(INTEL, 0x1e03), board_ahci }, /* Panther Point AHCI */
305         { PCI_VDEVICE(INTEL, 0x1e04), board_ahci }, /* Panther Point RAID */
306         { PCI_VDEVICE(INTEL, 0x1e05), board_ahci }, /* Panther Point RAID */
307         { PCI_VDEVICE(INTEL, 0x1e06), board_ahci }, /* Panther Point RAID */
308         { PCI_VDEVICE(INTEL, 0x1e07), board_ahci }, /* Panther Point RAID */
309         { PCI_VDEVICE(INTEL, 0x1e0e), board_ahci }, /* Panther Point RAID */
310         { PCI_VDEVICE(INTEL, 0x8c02), board_ahci }, /* Lynx Point AHCI */
311         { PCI_VDEVICE(INTEL, 0x8c03), board_ahci }, /* Lynx Point AHCI */
312         { PCI_VDEVICE(INTEL, 0x8c04), board_ahci }, /* Lynx Point RAID */
313         { PCI_VDEVICE(INTEL, 0x8c05), board_ahci }, /* Lynx Point RAID */
314         { PCI_VDEVICE(INTEL, 0x8c06), board_ahci }, /* Lynx Point RAID */
315         { PCI_VDEVICE(INTEL, 0x8c07), board_ahci }, /* Lynx Point RAID */
316         { PCI_VDEVICE(INTEL, 0x8c0e), board_ahci }, /* Lynx Point RAID */
317         { PCI_VDEVICE(INTEL, 0x8c0f), board_ahci }, /* Lynx Point RAID */
318         { PCI_VDEVICE(INTEL, 0x9c02), board_ahci }, /* Lynx Point-LP AHCI */
319         { PCI_VDEVICE(INTEL, 0x9c03), board_ahci }, /* Lynx Point-LP AHCI */
320         { PCI_VDEVICE(INTEL, 0x9c04), board_ahci }, /* Lynx Point-LP RAID */
321         { PCI_VDEVICE(INTEL, 0x9c05), board_ahci }, /* Lynx Point-LP RAID */
322         { PCI_VDEVICE(INTEL, 0x9c06), board_ahci }, /* Lynx Point-LP RAID */
323         { PCI_VDEVICE(INTEL, 0x9c07), board_ahci }, /* Lynx Point-LP RAID */
324         { PCI_VDEVICE(INTEL, 0x9c0e), board_ahci }, /* Lynx Point-LP RAID */
325         { PCI_VDEVICE(INTEL, 0x9c0f), board_ahci }, /* Lynx Point-LP RAID */
326         { PCI_VDEVICE(INTEL, 0x1f22), board_ahci }, /* Avoton AHCI */
327         { PCI_VDEVICE(INTEL, 0x1f23), board_ahci }, /* Avoton AHCI */
328         { PCI_VDEVICE(INTEL, 0x1f24), board_ahci }, /* Avoton RAID */
329         { PCI_VDEVICE(INTEL, 0x1f25), board_ahci }, /* Avoton RAID */
330         { PCI_VDEVICE(INTEL, 0x1f26), board_ahci }, /* Avoton RAID */
331         { PCI_VDEVICE(INTEL, 0x1f27), board_ahci }, /* Avoton RAID */
332         { PCI_VDEVICE(INTEL, 0x1f2e), board_ahci }, /* Avoton RAID */
333         { PCI_VDEVICE(INTEL, 0x1f2f), board_ahci }, /* Avoton RAID */
334         { PCI_VDEVICE(INTEL, 0x1f32), board_ahci_avn }, /* Avoton AHCI */
335         { PCI_VDEVICE(INTEL, 0x1f33), board_ahci_avn }, /* Avoton AHCI */
336         { PCI_VDEVICE(INTEL, 0x1f34), board_ahci_avn }, /* Avoton RAID */
337         { PCI_VDEVICE(INTEL, 0x1f35), board_ahci_avn }, /* Avoton RAID */
338         { PCI_VDEVICE(INTEL, 0x1f36), board_ahci_avn }, /* Avoton RAID */
339         { PCI_VDEVICE(INTEL, 0x1f37), board_ahci_avn }, /* Avoton RAID */
340         { PCI_VDEVICE(INTEL, 0x1f3e), board_ahci_avn }, /* Avoton RAID */
341         { PCI_VDEVICE(INTEL, 0x1f3f), board_ahci_avn }, /* Avoton RAID */
342         { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Wellsburg RAID */
343         { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Wellsburg RAID */
344         { PCI_VDEVICE(INTEL, 0x8d02), board_ahci }, /* Wellsburg AHCI */
345         { PCI_VDEVICE(INTEL, 0x8d04), board_ahci }, /* Wellsburg RAID */
346         { PCI_VDEVICE(INTEL, 0x8d06), board_ahci }, /* Wellsburg RAID */
347         { PCI_VDEVICE(INTEL, 0x8d0e), board_ahci }, /* Wellsburg RAID */
348         { PCI_VDEVICE(INTEL, 0x8d62), board_ahci }, /* Wellsburg AHCI */
349         { PCI_VDEVICE(INTEL, 0x8d64), board_ahci }, /* Wellsburg RAID */
350         { PCI_VDEVICE(INTEL, 0x8d66), board_ahci }, /* Wellsburg RAID */
351         { PCI_VDEVICE(INTEL, 0x8d6e), board_ahci }, /* Wellsburg RAID */
352         { PCI_VDEVICE(INTEL, 0x23a3), board_ahci }, /* Coleto Creek AHCI */
353         { PCI_VDEVICE(INTEL, 0x9c83), board_ahci }, /* Wildcat Point-LP AHCI */
354         { PCI_VDEVICE(INTEL, 0x9c85), board_ahci }, /* Wildcat Point-LP RAID */
355         { PCI_VDEVICE(INTEL, 0x9c87), board_ahci }, /* Wildcat Point-LP RAID */
356         { PCI_VDEVICE(INTEL, 0x9c8f), board_ahci }, /* Wildcat Point-LP RAID */
357         { PCI_VDEVICE(INTEL, 0x8c82), board_ahci }, /* 9 Series AHCI */
358         { PCI_VDEVICE(INTEL, 0x8c83), board_ahci }, /* 9 Series AHCI */
359         { PCI_VDEVICE(INTEL, 0x8c84), board_ahci }, /* 9 Series RAID */
360         { PCI_VDEVICE(INTEL, 0x8c85), board_ahci }, /* 9 Series RAID */
361         { PCI_VDEVICE(INTEL, 0x8c86), board_ahci }, /* 9 Series RAID */
362         { PCI_VDEVICE(INTEL, 0x8c87), board_ahci }, /* 9 Series RAID */
363         { PCI_VDEVICE(INTEL, 0x8c8e), board_ahci }, /* 9 Series RAID */
364         { PCI_VDEVICE(INTEL, 0x8c8f), board_ahci }, /* 9 Series RAID */
365         { PCI_VDEVICE(INTEL, 0x9d03), board_ahci }, /* Sunrise Point-LP AHCI */
366         { PCI_VDEVICE(INTEL, 0x9d05), board_ahci }, /* Sunrise Point-LP RAID */
367         { PCI_VDEVICE(INTEL, 0x9d07), board_ahci }, /* Sunrise Point-LP RAID */
368         { PCI_VDEVICE(INTEL, 0xa102), board_ahci }, /* Sunrise Point-H AHCI */
369         { PCI_VDEVICE(INTEL, 0xa103), board_ahci }, /* Sunrise Point-H AHCI */
370         { PCI_VDEVICE(INTEL, 0xa105), board_ahci }, /* Sunrise Point-H RAID */
371         { PCI_VDEVICE(INTEL, 0xa106), board_ahci }, /* Sunrise Point-H RAID */
372         { PCI_VDEVICE(INTEL, 0xa107), board_ahci }, /* Sunrise Point-H RAID */
373         { PCI_VDEVICE(INTEL, 0xa10f), board_ahci }, /* Sunrise Point-H RAID */
374         { PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* Lewisburg RAID*/
375         { PCI_VDEVICE(INTEL, 0x2823), board_ahci }, /* Lewisburg AHCI*/
376         { PCI_VDEVICE(INTEL, 0x2826), board_ahci }, /* Lewisburg RAID*/
377         { PCI_VDEVICE(INTEL, 0x2827), board_ahci }, /* Lewisburg RAID*/
378         { PCI_VDEVICE(INTEL, 0xa182), board_ahci }, /* Lewisburg AHCI*/
379         { PCI_VDEVICE(INTEL, 0xa186), board_ahci }, /* Lewisburg RAID*/
380         { PCI_VDEVICE(INTEL, 0xa1d2), board_ahci }, /* Lewisburg RAID*/
381         { PCI_VDEVICE(INTEL, 0xa1d6), board_ahci }, /* Lewisburg RAID*/
382         { PCI_VDEVICE(INTEL, 0xa202), board_ahci }, /* Lewisburg AHCI*/
383         { PCI_VDEVICE(INTEL, 0xa206), board_ahci }, /* Lewisburg RAID*/
384         { PCI_VDEVICE(INTEL, 0xa252), board_ahci }, /* Lewisburg RAID*/
385         { PCI_VDEVICE(INTEL, 0xa256), board_ahci }, /* Lewisburg RAID*/
386 
387         /* JMicron 360/1/3/5/6, match class to avoid IDE function */
388         { PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
389           PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci_ign_iferr },
390         /* JMicron 362B and 362C have an AHCI function with IDE class code */
391         { PCI_VDEVICE(JMICRON, 0x2362), board_ahci_ign_iferr },
392         { PCI_VDEVICE(JMICRON, 0x236f), board_ahci_ign_iferr },
393         /* May need to update quirk_jmicron_async_suspend() for additions */
394 
395         /* ATI */
396         { PCI_VDEVICE(ATI, 0x4380), board_ahci_sb600 }, /* ATI SB600 */
397         { PCI_VDEVICE(ATI, 0x4390), board_ahci_sb700 }, /* ATI SB700/800 */
398         { PCI_VDEVICE(ATI, 0x4391), board_ahci_sb700 }, /* ATI SB700/800 */
399         { PCI_VDEVICE(ATI, 0x4392), board_ahci_sb700 }, /* ATI SB700/800 */
400         { PCI_VDEVICE(ATI, 0x4393), board_ahci_sb700 }, /* ATI SB700/800 */
401         { PCI_VDEVICE(ATI, 0x4394), board_ahci_sb700 }, /* ATI SB700/800 */
402         { PCI_VDEVICE(ATI, 0x4395), board_ahci_sb700 }, /* ATI SB700/800 */
403 
404         /* AMD */
405         { PCI_VDEVICE(AMD, 0x7800), board_ahci }, /* AMD Hudson-2 */
406         { PCI_VDEVICE(AMD, 0x7900), board_ahci }, /* AMD CZ */
407         /* AMD is using RAID class only for ahci controllers */
408         { PCI_VENDOR_ID_AMD, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
409           PCI_CLASS_STORAGE_RAID << 8, 0xffffff, board_ahci },
410 
411         /* VIA */
412         { PCI_VDEVICE(VIA, 0x3349), board_ahci_vt8251 }, /* VIA VT8251 */
413         { PCI_VDEVICE(VIA, 0x6287), board_ahci_vt8251 }, /* VIA VT8251 */
414 
415         /* NVIDIA */
416         { PCI_VDEVICE(NVIDIA, 0x044c), board_ahci_mcp65 },      /* MCP65 */
417         { PCI_VDEVICE(NVIDIA, 0x044d), board_ahci_mcp65 },      /* MCP65 */
418         { PCI_VDEVICE(NVIDIA, 0x044e), board_ahci_mcp65 },      /* MCP65 */
419         { PCI_VDEVICE(NVIDIA, 0x044f), board_ahci_mcp65 },      /* MCP65 */
420         { PCI_VDEVICE(NVIDIA, 0x045c), board_ahci_mcp65 },      /* MCP65 */
421         { PCI_VDEVICE(NVIDIA, 0x045d), board_ahci_mcp65 },      /* MCP65 */
422         { PCI_VDEVICE(NVIDIA, 0x045e), board_ahci_mcp65 },      /* MCP65 */
423         { PCI_VDEVICE(NVIDIA, 0x045f), board_ahci_mcp65 },      /* MCP65 */
424         { PCI_VDEVICE(NVIDIA, 0x0550), board_ahci_mcp67 },      /* MCP67 */
425         { PCI_VDEVICE(NVIDIA, 0x0551), board_ahci_mcp67 },      /* MCP67 */
426         { PCI_VDEVICE(NVIDIA, 0x0552), board_ahci_mcp67 },      /* MCP67 */
427         { PCI_VDEVICE(NVIDIA, 0x0553), board_ahci_mcp67 },      /* MCP67 */
428         { PCI_VDEVICE(NVIDIA, 0x0554), board_ahci_mcp67 },      /* MCP67 */
429         { PCI_VDEVICE(NVIDIA, 0x0555), board_ahci_mcp67 },      /* MCP67 */
430         { PCI_VDEVICE(NVIDIA, 0x0556), board_ahci_mcp67 },      /* MCP67 */
431         { PCI_VDEVICE(NVIDIA, 0x0557), board_ahci_mcp67 },      /* MCP67 */
432         { PCI_VDEVICE(NVIDIA, 0x0558), board_ahci_mcp67 },      /* MCP67 */
433         { PCI_VDEVICE(NVIDIA, 0x0559), board_ahci_mcp67 },      /* MCP67 */
434         { PCI_VDEVICE(NVIDIA, 0x055a), board_ahci_mcp67 },      /* MCP67 */
435         { PCI_VDEVICE(NVIDIA, 0x055b), board_ahci_mcp67 },      /* MCP67 */
436         { PCI_VDEVICE(NVIDIA, 0x0580), board_ahci_mcp_linux },  /* Linux ID */
437         { PCI_VDEVICE(NVIDIA, 0x0581), board_ahci_mcp_linux },  /* Linux ID */
438         { PCI_VDEVICE(NVIDIA, 0x0582), board_ahci_mcp_linux },  /* Linux ID */
439         { PCI_VDEVICE(NVIDIA, 0x0583), board_ahci_mcp_linux },  /* Linux ID */
440         { PCI_VDEVICE(NVIDIA, 0x0584), board_ahci_mcp_linux },  /* Linux ID */
441         { PCI_VDEVICE(NVIDIA, 0x0585), board_ahci_mcp_linux },  /* Linux ID */
442         { PCI_VDEVICE(NVIDIA, 0x0586), board_ahci_mcp_linux },  /* Linux ID */
443         { PCI_VDEVICE(NVIDIA, 0x0587), board_ahci_mcp_linux },  /* Linux ID */
444         { PCI_VDEVICE(NVIDIA, 0x0588), board_ahci_mcp_linux },  /* Linux ID */
445         { PCI_VDEVICE(NVIDIA, 0x0589), board_ahci_mcp_linux },  /* Linux ID */
446         { PCI_VDEVICE(NVIDIA, 0x058a), board_ahci_mcp_linux },  /* Linux ID */
447         { PCI_VDEVICE(NVIDIA, 0x058b), board_ahci_mcp_linux },  /* Linux ID */
448         { PCI_VDEVICE(NVIDIA, 0x058c), board_ahci_mcp_linux },  /* Linux ID */
449         { PCI_VDEVICE(NVIDIA, 0x058d), board_ahci_mcp_linux },  /* Linux ID */
450         { PCI_VDEVICE(NVIDIA, 0x058e), board_ahci_mcp_linux },  /* Linux ID */
451         { PCI_VDEVICE(NVIDIA, 0x058f), board_ahci_mcp_linux },  /* Linux ID */
452         { PCI_VDEVICE(NVIDIA, 0x07f0), board_ahci_mcp73 },      /* MCP73 */
453         { PCI_VDEVICE(NVIDIA, 0x07f1), board_ahci_mcp73 },      /* MCP73 */
454         { PCI_VDEVICE(NVIDIA, 0x07f2), board_ahci_mcp73 },      /* MCP73 */
455         { PCI_VDEVICE(NVIDIA, 0x07f3), board_ahci_mcp73 },      /* MCP73 */
456         { PCI_VDEVICE(NVIDIA, 0x07f4), board_ahci_mcp73 },      /* MCP73 */
457         { PCI_VDEVICE(NVIDIA, 0x07f5), board_ahci_mcp73 },      /* MCP73 */
458         { PCI_VDEVICE(NVIDIA, 0x07f6), board_ahci_mcp73 },      /* MCP73 */
459         { PCI_VDEVICE(NVIDIA, 0x07f7), board_ahci_mcp73 },      /* MCP73 */
460         { PCI_VDEVICE(NVIDIA, 0x07f8), board_ahci_mcp73 },      /* MCP73 */
461         { PCI_VDEVICE(NVIDIA, 0x07f9), board_ahci_mcp73 },      /* MCP73 */
462         { PCI_VDEVICE(NVIDIA, 0x07fa), board_ahci_mcp73 },      /* MCP73 */
463         { PCI_VDEVICE(NVIDIA, 0x07fb), board_ahci_mcp73 },      /* MCP73 */
464         { PCI_VDEVICE(NVIDIA, 0x0ad0), board_ahci_mcp77 },      /* MCP77 */
465         { PCI_VDEVICE(NVIDIA, 0x0ad1), board_ahci_mcp77 },      /* MCP77 */
466         { PCI_VDEVICE(NVIDIA, 0x0ad2), board_ahci_mcp77 },      /* MCP77 */
467         { PCI_VDEVICE(NVIDIA, 0x0ad3), board_ahci_mcp77 },      /* MCP77 */
468         { PCI_VDEVICE(NVIDIA, 0x0ad4), board_ahci_mcp77 },      /* MCP77 */
469         { PCI_VDEVICE(NVIDIA, 0x0ad5), board_ahci_mcp77 },      /* MCP77 */
470         { PCI_VDEVICE(NVIDIA, 0x0ad6), board_ahci_mcp77 },      /* MCP77 */
471         { PCI_VDEVICE(NVIDIA, 0x0ad7), board_ahci_mcp77 },      /* MCP77 */
472         { PCI_VDEVICE(NVIDIA, 0x0ad8), board_ahci_mcp77 },      /* MCP77 */
473         { PCI_VDEVICE(NVIDIA, 0x0ad9), board_ahci_mcp77 },      /* MCP77 */
474         { PCI_VDEVICE(NVIDIA, 0x0ada), board_ahci_mcp77 },      /* MCP77 */
475         { PCI_VDEVICE(NVIDIA, 0x0adb), board_ahci_mcp77 },      /* MCP77 */
476         { PCI_VDEVICE(NVIDIA, 0x0ab4), board_ahci_mcp79 },      /* MCP79 */
477         { PCI_VDEVICE(NVIDIA, 0x0ab5), board_ahci_mcp79 },      /* MCP79 */
478         { PCI_VDEVICE(NVIDIA, 0x0ab6), board_ahci_mcp79 },      /* MCP79 */
479         { PCI_VDEVICE(NVIDIA, 0x0ab7), board_ahci_mcp79 },      /* MCP79 */
480         { PCI_VDEVICE(NVIDIA, 0x0ab8), board_ahci_mcp79 },      /* MCP79 */
481         { PCI_VDEVICE(NVIDIA, 0x0ab9), board_ahci_mcp79 },      /* MCP79 */
482         { PCI_VDEVICE(NVIDIA, 0x0aba), board_ahci_mcp79 },      /* MCP79 */
483         { PCI_VDEVICE(NVIDIA, 0x0abb), board_ahci_mcp79 },      /* MCP79 */
484         { PCI_VDEVICE(NVIDIA, 0x0abc), board_ahci_mcp79 },      /* MCP79 */
485         { PCI_VDEVICE(NVIDIA, 0x0abd), board_ahci_mcp79 },      /* MCP79 */
486         { PCI_VDEVICE(NVIDIA, 0x0abe), board_ahci_mcp79 },      /* MCP79 */
487         { PCI_VDEVICE(NVIDIA, 0x0abf), board_ahci_mcp79 },      /* MCP79 */
488         { PCI_VDEVICE(NVIDIA, 0x0d84), board_ahci_mcp89 },      /* MCP89 */
489         { PCI_VDEVICE(NVIDIA, 0x0d85), board_ahci_mcp89 },      /* MCP89 */
490         { PCI_VDEVICE(NVIDIA, 0x0d86), board_ahci_mcp89 },      /* MCP89 */
491         { PCI_VDEVICE(NVIDIA, 0x0d87), board_ahci_mcp89 },      /* MCP89 */
492         { PCI_VDEVICE(NVIDIA, 0x0d88), board_ahci_mcp89 },      /* MCP89 */
493         { PCI_VDEVICE(NVIDIA, 0x0d89), board_ahci_mcp89 },      /* MCP89 */
494         { PCI_VDEVICE(NVIDIA, 0x0d8a), board_ahci_mcp89 },      /* MCP89 */
495         { PCI_VDEVICE(NVIDIA, 0x0d8b), board_ahci_mcp89 },      /* MCP89 */
496         { PCI_VDEVICE(NVIDIA, 0x0d8c), board_ahci_mcp89 },      /* MCP89 */
497         { PCI_VDEVICE(NVIDIA, 0x0d8d), board_ahci_mcp89 },      /* MCP89 */
498         { PCI_VDEVICE(NVIDIA, 0x0d8e), board_ahci_mcp89 },      /* MCP89 */
499         { PCI_VDEVICE(NVIDIA, 0x0d8f), board_ahci_mcp89 },      /* MCP89 */
500 
501         /* SiS */
502         { PCI_VDEVICE(SI, 0x1184), board_ahci },                /* SiS 966 */
503         { PCI_VDEVICE(SI, 0x1185), board_ahci },                /* SiS 968 */
504         { PCI_VDEVICE(SI, 0x0186), board_ahci },                /* SiS 968 */
505 
506         /* ST Microelectronics */
507         { PCI_VDEVICE(STMICRO, 0xCC06), board_ahci },           /* ST ConneXt */
508 
509         /* Marvell */
510         { PCI_VDEVICE(MARVELL, 0x6145), board_ahci_mv },        /* 6145 */
511         { PCI_VDEVICE(MARVELL, 0x6121), board_ahci_mv },        /* 6121 */
512         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9123),
513           .class = PCI_CLASS_STORAGE_SATA_AHCI,
514           .class_mask = 0xffffff,
515           .driver_data = board_ahci_yes_fbs },                  /* 88se9128 */
516         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9125),
517           .driver_data = board_ahci_yes_fbs },                  /* 88se9125 */
518         { PCI_DEVICE_SUB(PCI_VENDOR_ID_MARVELL_EXT, 0x9178,
519                          PCI_VENDOR_ID_MARVELL_EXT, 0x9170),
520           .driver_data = board_ahci_yes_fbs },                  /* 88se9170 */
521         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
522           .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
523         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
524           .driver_data = board_ahci_yes_fbs },                  /* 88se9182 */
525         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9182),
526           .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
527         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
528           .driver_data = board_ahci_yes_fbs },                  /* 88se9172 on some Gigabyte */
529         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0),
530           .driver_data = board_ahci_yes_fbs },
531         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a2),        /* 88se91a2 */
532           .driver_data = board_ahci_yes_fbs },
533         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
534           .driver_data = board_ahci_yes_fbs },
535         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9230),
536           .driver_data = board_ahci_yes_fbs },
537         { PCI_DEVICE(PCI_VENDOR_ID_TTI, 0x0642),
538           .driver_data = board_ahci_yes_fbs },
539 
540         /* Promise */
541         { PCI_VDEVICE(PROMISE, 0x3f20), board_ahci },   /* PDC42819 */
542         { PCI_VDEVICE(PROMISE, 0x3781), board_ahci },   /* FastTrak TX8660 ahci-mode */
543 
544         /* Asmedia */
545         { PCI_VDEVICE(ASMEDIA, 0x0601), board_ahci },   /* ASM1060 */
546         { PCI_VDEVICE(ASMEDIA, 0x0602), board_ahci },   /* ASM1060 */
547         { PCI_VDEVICE(ASMEDIA, 0x0611), board_ahci },   /* ASM1061 */
548         { PCI_VDEVICE(ASMEDIA, 0x0612), board_ahci },   /* ASM1062 */
549 
550         /*
551          * Samsung SSDs found on some macbooks.  NCQ times out if MSI is
552          * enabled.  https://bugzilla.kernel.org/show_bug.cgi?id=60731
553          */
554         { PCI_VDEVICE(SAMSUNG, 0x1600), board_ahci_nomsi },
555         { PCI_VDEVICE(SAMSUNG, 0xa800), board_ahci_nomsi },
556 
557         /* Enmotus */
558         { PCI_DEVICE(0x1c44, 0x8000), board_ahci },
559 
560         /* Generic, PCI class code for AHCI */
561         { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
562           PCI_CLASS_STORAGE_SATA_AHCI, 0xffffff, board_ahci },
563 
564         { }     /* terminate list */
565 };
566 
567 static const struct dev_pm_ops ahci_pci_pm_ops = {
568         SET_SYSTEM_SLEEP_PM_OPS(ahci_pci_device_suspend, ahci_pci_device_resume)
569         SET_RUNTIME_PM_OPS(ahci_pci_device_runtime_suspend,
570                            ahci_pci_device_runtime_resume, NULL)
571 };
572 
573 static struct pci_driver ahci_pci_driver = {
574         .name                   = DRV_NAME,
575         .id_table               = ahci_pci_tbl,
576         .probe                  = ahci_init_one,
577         .remove                 = ahci_remove_one,
578         .driver = {
579                 .pm             = &ahci_pci_pm_ops,
580         },
581 };
582 
583 #if defined(CONFIG_PATA_MARVELL) || defined(CONFIG_PATA_MARVELL_MODULE)
584 static int marvell_enable;
585 #else
586 static int marvell_enable = 1;
587 #endif
588 module_param(marvell_enable, int, 0644);
589 MODULE_PARM_DESC(marvell_enable, "Marvell SATA via AHCI (1 = enabled)");
590 
591 
592 static void ahci_pci_save_initial_config(struct pci_dev *pdev,
593                                          struct ahci_host_priv *hpriv)
594 {
595         if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361) {
596                 dev_info(&pdev->dev, "JMB361 has only one port\n");
597                 hpriv->force_port_map = 1;
598         }
599 
600         /*
601          * Temporary Marvell 6145 hack: PATA port presence
602          * is asserted through the standard AHCI port
603          * presence register, as bit 4 (counting from 0)
604          */
605         if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
606                 if (pdev->device == 0x6121)
607                         hpriv->mask_port_map = 0x3;
608                 else
609                         hpriv->mask_port_map = 0xf;
610                 dev_info(&pdev->dev,
611                           "Disabling your PATA port. Use the boot option 'ahci.marvell_enable=0' to avoid this.\n");
612         }
613 
614         ahci_save_initial_config(&pdev->dev, hpriv);
615 }
616 
617 static int ahci_pci_reset_controller(struct ata_host *host)
618 {
619         struct pci_dev *pdev = to_pci_dev(host->dev);
620 
621         ahci_reset_controller(host);
622 
623         if (pdev->vendor == PCI_VENDOR_ID_INTEL) {
624                 struct ahci_host_priv *hpriv = host->private_data;
625                 u16 tmp16;
626 
627                 /* configure PCS */
628                 pci_read_config_word(pdev, 0x92, &tmp16);
629                 if ((tmp16 & hpriv->port_map) != hpriv->port_map) {
630                         tmp16 |= hpriv->port_map;
631                         pci_write_config_word(pdev, 0x92, tmp16);
632                 }
633         }
634 
635         return 0;
636 }
637 
638 static void ahci_pci_init_controller(struct ata_host *host)
639 {
640         struct ahci_host_priv *hpriv = host->private_data;
641         struct pci_dev *pdev = to_pci_dev(host->dev);
642         void __iomem *port_mmio;
643         u32 tmp;
644         int mv;
645 
646         if (hpriv->flags & AHCI_HFLAG_MV_PATA) {
647                 if (pdev->device == 0x6121)
648                         mv = 2;
649                 else
650                         mv = 4;
651                 port_mmio = __ahci_port_base(host, mv);
652 
653                 writel(0, port_mmio + PORT_IRQ_MASK);
654 
655                 /* clear port IRQ */
656                 tmp = readl(port_mmio + PORT_IRQ_STAT);
657                 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
658                 if (tmp)
659                         writel(tmp, port_mmio + PORT_IRQ_STAT);
660         }
661 
662         ahci_init_controller(host);
663 }
664 
665 static int ahci_vt8251_hardreset(struct ata_link *link, unsigned int *class,
666                                  unsigned long deadline)
667 {
668         struct ata_port *ap = link->ap;
669         struct ahci_host_priv *hpriv = ap->host->private_data;
670         bool online;
671         int rc;
672 
673         DPRINTK("ENTER\n");
674 
675         ahci_stop_engine(ap);
676 
677         rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
678                                  deadline, &online, NULL);
679 
680         hpriv->start_engine(ap);
681 
682         DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
683 
684         /* vt8251 doesn't clear BSY on signature FIS reception,
685          * request follow-up softreset.
686          */
687         return online ? -EAGAIN : rc;
688 }
689 
690 static int ahci_p5wdh_hardreset(struct ata_link *link, unsigned int *class,
691                                 unsigned long deadline)
692 {
693         struct ata_port *ap = link->ap;
694         struct ahci_port_priv *pp = ap->private_data;
695         struct ahci_host_priv *hpriv = ap->host->private_data;
696         u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
697         struct ata_taskfile tf;
698         bool online;
699         int rc;
700 
701         ahci_stop_engine(ap);
702 
703         /* clear D2H reception area to properly wait for D2H FIS */
704         ata_tf_init(link->device, &tf);
705         tf.command = ATA_BUSY;
706         ata_tf_to_fis(&tf, 0, 0, d2h_fis);
707 
708         rc = sata_link_hardreset(link, sata_ehc_deb_timing(&link->eh_context),
709                                  deadline, &online, NULL);
710 
711         hpriv->start_engine(ap);
712 
713         /* The pseudo configuration device on SIMG4726 attached to
714          * ASUS P5W-DH Deluxe doesn't send signature FIS after
715          * hardreset if no device is attached to the first downstream
716          * port && the pseudo device locks up on SRST w/ PMP==0.  To
717          * work around this, wait for !BSY only briefly.  If BSY isn't
718          * cleared, perform CLO and proceed to IDENTIFY (achieved by
719          * ATA_LFLAG_NO_SRST and ATA_LFLAG_ASSUME_ATA).
720          *
721          * Wait for two seconds.  Devices attached to downstream port
722          * which can't process the following IDENTIFY after this will
723          * have to be reset again.  For most cases, this should
724          * suffice while making probing snappish enough.
725          */
726         if (online) {
727                 rc = ata_wait_after_reset(link, jiffies + 2 * HZ,
728                                           ahci_check_ready);
729                 if (rc)
730                         ahci_kick_engine(ap);
731         }
732         return rc;
733 }
734 
735 /*
736  * ahci_avn_hardreset - attempt more aggressive recovery of Avoton ports.
737  *
738  * It has been observed with some SSDs that the timing of events in the
739  * link synchronization phase can leave the port in a state that can not
740  * be recovered by a SATA-hard-reset alone.  The failing signature is
741  * SStatus.DET stuck at 1 ("Device presence detected but Phy
742  * communication not established").  It was found that unloading and
743  * reloading the driver when this problem occurs allows the drive
744  * connection to be recovered (DET advanced to 0x3).  The critical
745  * component of reloading the driver is that the port state machines are
746  * reset by bouncing "port enable" in the AHCI PCS configuration
747  * register.  So, reproduce that effect by bouncing a port whenever we
748  * see DET==1 after a reset.
749  */
750 static int ahci_avn_hardreset(struct ata_link *link, unsigned int *class,
751                               unsigned long deadline)
752 {
753         const unsigned long *timing = sata_ehc_deb_timing(&link->eh_context);
754         struct ata_port *ap = link->ap;
755         struct ahci_port_priv *pp = ap->private_data;
756         struct ahci_host_priv *hpriv = ap->host->private_data;
757         u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
758         unsigned long tmo = deadline - jiffies;
759         struct ata_taskfile tf;
760         bool online;
761         int rc, i;
762 
763         DPRINTK("ENTER\n");
764 
765         ahci_stop_engine(ap);
766 
767         for (i = 0; i < 2; i++) {
768                 u16 val;
769                 u32 sstatus;
770                 int port = ap->port_no;
771                 struct ata_host *host = ap->host;
772                 struct pci_dev *pdev = to_pci_dev(host->dev);
773 
774                 /* clear D2H reception area to properly wait for D2H FIS */
775                 ata_tf_init(link->device, &tf);
776                 tf.command = ATA_BUSY;
777                 ata_tf_to_fis(&tf, 0, 0, d2h_fis);
778 
779                 rc = sata_link_hardreset(link, timing, deadline, &online,
780                                 ahci_check_ready);
781 
782                 if (sata_scr_read(link, SCR_STATUS, &sstatus) != 0 ||
783                                 (sstatus & 0xf) != 1)
784                         break;
785 
786                 ata_link_printk(link, KERN_INFO, "avn bounce port%d\n",
787                                 port);
788 
789                 pci_read_config_word(pdev, 0x92, &val);
790                 val &= ~(1 << port);
791                 pci_write_config_word(pdev, 0x92, val);
792                 ata_msleep(ap, 1000);
793                 val |= 1 << port;
794                 pci_write_config_word(pdev, 0x92, val);
795                 deadline += tmo;
796         }
797 
798         hpriv->start_engine(ap);
799 
800         if (online)
801                 *class = ahci_dev_classify(ap);
802 
803         DPRINTK("EXIT, rc=%d, class=%u\n", rc, *class);
804         return rc;
805 }
806 
807 
808 #ifdef CONFIG_PM
809 static void ahci_pci_disable_interrupts(struct ata_host *host)
810 {
811         struct ahci_host_priv *hpriv = host->private_data;
812         void __iomem *mmio = hpriv->mmio;
813         u32 ctl;
814 
815         /* AHCI spec rev1.1 section 8.3.3:
816          * Software must disable interrupts prior to requesting a
817          * transition of the HBA to D3 state.
818          */
819         ctl = readl(mmio + HOST_CTL);
820         ctl &= ~HOST_IRQ_EN;
821         writel(ctl, mmio + HOST_CTL);
822         readl(mmio + HOST_CTL); /* flush */
823 }
824 
825 static int ahci_pci_device_runtime_suspend(struct device *dev)
826 {
827         struct pci_dev *pdev = to_pci_dev(dev);
828         struct ata_host *host = pci_get_drvdata(pdev);
829 
830         ahci_pci_disable_interrupts(host);
831         return 0;
832 }
833 
834 static int ahci_pci_device_runtime_resume(struct device *dev)
835 {
836         struct pci_dev *pdev = to_pci_dev(dev);
837         struct ata_host *host = pci_get_drvdata(pdev);
838         int rc;
839 
840         rc = ahci_pci_reset_controller(host);
841         if (rc)
842                 return rc;
843         ahci_pci_init_controller(host);
844         return 0;
845 }
846 
847 #ifdef CONFIG_PM_SLEEP
848 static int ahci_pci_device_suspend(struct device *dev)
849 {
850         struct pci_dev *pdev = to_pci_dev(dev);
851         struct ata_host *host = pci_get_drvdata(pdev);
852         struct ahci_host_priv *hpriv = host->private_data;
853 
854         if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
855                 dev_err(&pdev->dev,
856                         "BIOS update required for suspend/resume\n");
857                 return -EIO;
858         }
859 
860         ahci_pci_disable_interrupts(host);
861         return ata_host_suspend(host, PMSG_SUSPEND);
862 }
863 
864 static int ahci_pci_device_resume(struct device *dev)
865 {
866         struct pci_dev *pdev = to_pci_dev(dev);
867         struct ata_host *host = pci_get_drvdata(pdev);
868         int rc;
869 
870         /* Apple BIOS helpfully mangles the registers on resume */
871         if (is_mcp89_apple(pdev))
872                 ahci_mcp89_apple_enable(pdev);
873 
874         if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
875                 rc = ahci_pci_reset_controller(host);
876                 if (rc)
877                         return rc;
878 
879                 ahci_pci_init_controller(host);
880         }
881 
882         ata_host_resume(host);
883 
884         return 0;
885 }
886 #endif
887 
888 #endif /* CONFIG_PM */
889 
890 static int ahci_configure_dma_masks(struct pci_dev *pdev, int using_dac)
891 {
892         int rc;
893 
894         /*
895          * If the device fixup already set the dma_mask to some non-standard
896          * value, don't extend it here. This happens on STA2X11, for example.
897          */
898         if (pdev->dma_mask && pdev->dma_mask < DMA_BIT_MASK(32))
899                 return 0;
900 
901         if (using_dac &&
902             !dma_set_mask(&pdev->dev, DMA_BIT_MASK(64))) {
903                 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
904                 if (rc) {
905                         rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
906                         if (rc) {
907                                 dev_err(&pdev->dev,
908                                         "64-bit DMA enable failed\n");
909                                 return rc;
910                         }
911                 }
912         } else {
913                 rc = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
914                 if (rc) {
915                         dev_err(&pdev->dev, "32-bit DMA enable failed\n");
916                         return rc;
917                 }
918                 rc = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
919                 if (rc) {
920                         dev_err(&pdev->dev,
921                                 "32-bit consistent DMA enable failed\n");
922                         return rc;
923                 }
924         }
925         return 0;
926 }
927 
928 static void ahci_pci_print_info(struct ata_host *host)
929 {
930         struct pci_dev *pdev = to_pci_dev(host->dev);
931         u16 cc;
932         const char *scc_s;
933 
934         pci_read_config_word(pdev, 0x0a, &cc);
935         if (cc == PCI_CLASS_STORAGE_IDE)
936                 scc_s = "IDE";
937         else if (cc == PCI_CLASS_STORAGE_SATA)
938                 scc_s = "SATA";
939         else if (cc == PCI_CLASS_STORAGE_RAID)
940                 scc_s = "RAID";
941         else
942                 scc_s = "unknown";
943 
944         ahci_print_info(host, scc_s);
945 }
946 
947 /* On ASUS P5W DH Deluxe, the second port of PCI device 00:1f.2 is
948  * hardwired to on-board SIMG 4726.  The chipset is ICH8 and doesn't
949  * support PMP and the 4726 either directly exports the device
950  * attached to the first downstream port or acts as a hardware storage
951  * controller and emulate a single ATA device (can be RAID 0/1 or some
952  * other configuration).
953  *
954  * When there's no device attached to the first downstream port of the
955  * 4726, "Config Disk" appears, which is a pseudo ATA device to
956  * configure the 4726.  However, ATA emulation of the device is very
957  * lame.  It doesn't send signature D2H Reg FIS after the initial
958  * hardreset, pukes on SRST w/ PMP==0 and has bunch of other issues.
959  *
960  * The following function works around the problem by always using
961  * hardreset on the port and not depending on receiving signature FIS
962  * afterward.  If signature FIS isn't received soon, ATA class is
963  * assumed without follow-up softreset.
964  */
965 static void ahci_p5wdh_workaround(struct ata_host *host)
966 {
967         static const struct dmi_system_id sysids[] = {
968                 {
969                         .ident = "P5W DH Deluxe",
970                         .matches = {
971                                 DMI_MATCH(DMI_SYS_VENDOR,
972                                           "ASUSTEK COMPUTER INC"),
973                                 DMI_MATCH(DMI_PRODUCT_NAME, "P5W DH Deluxe"),
974                         },
975                 },
976                 { }
977         };
978         struct pci_dev *pdev = to_pci_dev(host->dev);
979 
980         if (pdev->bus->number == 0 && pdev->devfn == PCI_DEVFN(0x1f, 2) &&
981             dmi_check_system(sysids)) {
982                 struct ata_port *ap = host->ports[1];
983 
984                 dev_info(&pdev->dev,
985                          "enabling ASUS P5W DH Deluxe on-board SIMG4726 workaround\n");
986 
987                 ap->ops = &ahci_p5wdh_ops;
988                 ap->link.flags |= ATA_LFLAG_NO_SRST | ATA_LFLAG_ASSUME_ATA;
989         }
990 }
991 
992 /*
993  * Macbook7,1 firmware forcibly disables MCP89 AHCI and changes PCI ID when
994  * booting in BIOS compatibility mode.  We restore the registers but not ID.
995  */
996 static void ahci_mcp89_apple_enable(struct pci_dev *pdev)
997 {
998         u32 val;
999 
1000         printk(KERN_INFO "ahci: enabling MCP89 AHCI mode\n");
1001 
1002         pci_read_config_dword(pdev, 0xf8, &val);
1003         val |= 1 << 0x1b;
1004         /* the following changes the device ID, but appears not to affect function */
1005         /* val = (val & ~0xf0000000) | 0x80000000; */
1006         pci_write_config_dword(pdev, 0xf8, val);
1007 
1008         pci_read_config_dword(pdev, 0x54c, &val);
1009         val |= 1 << 0xc;
1010         pci_write_config_dword(pdev, 0x54c, val);
1011 
1012         pci_read_config_dword(pdev, 0x4a4, &val);
1013         val &= 0xff;
1014         val |= 0x01060100;
1015         pci_write_config_dword(pdev, 0x4a4, val);
1016 
1017         pci_read_config_dword(pdev, 0x54c, &val);
1018         val &= ~(1 << 0xc);
1019         pci_write_config_dword(pdev, 0x54c, val);
1020 
1021         pci_read_config_dword(pdev, 0xf8, &val);
1022         val &= ~(1 << 0x1b);
1023         pci_write_config_dword(pdev, 0xf8, val);
1024 }
1025 
1026 static bool is_mcp89_apple(struct pci_dev *pdev)
1027 {
1028         return pdev->vendor == PCI_VENDOR_ID_NVIDIA &&
1029                 pdev->device == PCI_DEVICE_ID_NVIDIA_NFORCE_MCP89_SATA &&
1030                 pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1031                 pdev->subsystem_device == 0xcb89;
1032 }
1033 
1034 /* only some SB600 ahci controllers can do 64bit DMA */
1035 static bool ahci_sb600_enable_64bit(struct pci_dev *pdev)
1036 {
1037         static const struct dmi_system_id sysids[] = {
1038                 /*
1039                  * The oldest version known to be broken is 0901 and
1040                  * working is 1501 which was released on 2007-10-26.
1041                  * Enable 64bit DMA on 1501 and anything newer.
1042                  *
1043                  * Please read bko#9412 for more info.
1044                  */
1045                 {
1046                         .ident = "ASUS M2A-VM",
1047                         .matches = {
1048                                 DMI_MATCH(DMI_BOARD_VENDOR,
1049                                           "ASUSTeK Computer INC."),
1050                                 DMI_MATCH(DMI_BOARD_NAME, "M2A-VM"),
1051                         },
1052                         .driver_data = "20071026",      /* yyyymmdd */
1053                 },
1054                 /*
1055                  * All BIOS versions for the MSI K9A2 Platinum (MS-7376)
1056                  * support 64bit DMA.
1057                  *
1058                  * BIOS versions earlier than 1.5 had the Manufacturer DMI
1059                  * fields as "MICRO-STAR INTERANTIONAL CO.,LTD".
1060                  * This spelling mistake was fixed in BIOS version 1.5, so
1061                  * 1.5 and later have the Manufacturer as
1062                  * "MICRO-STAR INTERNATIONAL CO.,LTD".
1063                  * So try to match on DMI_BOARD_VENDOR of "MICRO-STAR INTER".
1064                  *
1065                  * BIOS versions earlier than 1.9 had a Board Product Name
1066                  * DMI field of "MS-7376". This was changed to be
1067                  * "K9A2 Platinum (MS-7376)" in version 1.9, but we can still
1068                  * match on DMI_BOARD_NAME of "MS-7376".
1069                  */
1070                 {
1071                         .ident = "MSI K9A2 Platinum",
1072                         .matches = {
1073                                 DMI_MATCH(DMI_BOARD_VENDOR,
1074                                           "MICRO-STAR INTER"),
1075                                 DMI_MATCH(DMI_BOARD_NAME, "MS-7376"),
1076                         },
1077                 },
1078                 /*
1079                  * All BIOS versions for the MSI K9AGM2 (MS-7327) support
1080                  * 64bit DMA.
1081                  *
1082                  * This board also had the typo mentioned above in the
1083                  * Manufacturer DMI field (fixed in BIOS version 1.5), so
1084                  * match on DMI_BOARD_VENDOR of "MICRO-STAR INTER" again.
1085                  */
1086                 {
1087                         .ident = "MSI K9AGM2",
1088                         .matches = {
1089                                 DMI_MATCH(DMI_BOARD_VENDOR,
1090                                           "MICRO-STAR INTER"),
1091                                 DMI_MATCH(DMI_BOARD_NAME, "MS-7327"),
1092                         },
1093                 },
1094                 /*
1095                  * All BIOS versions for the Asus M3A support 64bit DMA.
1096                  * (all release versions from 0301 to 1206 were tested)
1097                  */
1098                 {
1099                         .ident = "ASUS M3A",
1100                         .matches = {
1101                                 DMI_MATCH(DMI_BOARD_VENDOR,
1102                                           "ASUSTeK Computer INC."),
1103                                 DMI_MATCH(DMI_BOARD_NAME, "M3A"),
1104                         },
1105                 },
1106                 { }
1107         };
1108         const struct dmi_system_id *match;
1109         int year, month, date;
1110         char buf[9];
1111 
1112         match = dmi_first_match(sysids);
1113         if (pdev->bus->number != 0 || pdev->devfn != PCI_DEVFN(0x12, 0) ||
1114             !match)
1115                 return false;
1116 
1117         if (!match->driver_data)
1118                 goto enable_64bit;
1119 
1120         dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1121         snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1122 
1123         if (strcmp(buf, match->driver_data) >= 0)
1124                 goto enable_64bit;
1125         else {
1126                 dev_warn(&pdev->dev,
1127                          "%s: BIOS too old, forcing 32bit DMA, update BIOS\n",
1128                          match->ident);
1129                 return false;
1130         }
1131 
1132 enable_64bit:
1133         dev_warn(&pdev->dev, "%s: enabling 64bit DMA\n", match->ident);
1134         return true;
1135 }
1136 
1137 static bool ahci_broken_system_poweroff(struct pci_dev *pdev)
1138 {
1139         static const struct dmi_system_id broken_systems[] = {
1140                 {
1141                         .ident = "HP Compaq nx6310",
1142                         .matches = {
1143                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1144                                 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq nx6310"),
1145                         },
1146                         /* PCI slot number of the controller */
1147                         .driver_data = (void *)0x1FUL,
1148                 },
1149                 {
1150                         .ident = "HP Compaq 6720s",
1151                         .matches = {
1152                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1153                                 DMI_MATCH(DMI_PRODUCT_NAME, "HP Compaq 6720s"),
1154                         },
1155                         /* PCI slot number of the controller */
1156                         .driver_data = (void *)0x1FUL,
1157                 },
1158 
1159                 { }     /* terminate list */
1160         };
1161         const struct dmi_system_id *dmi = dmi_first_match(broken_systems);
1162 
1163         if (dmi) {
1164                 unsigned long slot = (unsigned long)dmi->driver_data;
1165                 /* apply the quirk only to on-board controllers */
1166                 return slot == PCI_SLOT(pdev->devfn);
1167         }
1168 
1169         return false;
1170 }
1171 
1172 static bool ahci_broken_suspend(struct pci_dev *pdev)
1173 {
1174         static const struct dmi_system_id sysids[] = {
1175                 /*
1176                  * On HP dv[4-6] and HDX18 with earlier BIOSen, link
1177                  * to the harddisk doesn't become online after
1178                  * resuming from STR.  Warn and fail suspend.
1179                  *
1180                  * http://bugzilla.kernel.org/show_bug.cgi?id=12276
1181                  *
1182                  * Use dates instead of versions to match as HP is
1183                  * apparently recycling both product and version
1184                  * strings.
1185                  *
1186                  * http://bugzilla.kernel.org/show_bug.cgi?id=15462
1187                  */
1188                 {
1189                         .ident = "dv4",
1190                         .matches = {
1191                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1192                                 DMI_MATCH(DMI_PRODUCT_NAME,
1193                                           "HP Pavilion dv4 Notebook PC"),
1194                         },
1195                         .driver_data = "20090105",      /* F.30 */
1196                 },
1197                 {
1198                         .ident = "dv5",
1199                         .matches = {
1200                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1201                                 DMI_MATCH(DMI_PRODUCT_NAME,
1202                                           "HP Pavilion dv5 Notebook PC"),
1203                         },
1204                         .driver_data = "20090506",      /* F.16 */
1205                 },
1206                 {
1207                         .ident = "dv6",
1208                         .matches = {
1209                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1210                                 DMI_MATCH(DMI_PRODUCT_NAME,
1211                                           "HP Pavilion dv6 Notebook PC"),
1212                         },
1213                         .driver_data = "20090423",      /* F.21 */
1214                 },
1215                 {
1216                         .ident = "HDX18",
1217                         .matches = {
1218                                 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
1219                                 DMI_MATCH(DMI_PRODUCT_NAME,
1220                                           "HP HDX18 Notebook PC"),
1221                         },
1222                         .driver_data = "20090430",      /* F.23 */
1223                 },
1224                 /*
1225                  * Acer eMachines G725 has the same problem.  BIOS
1226                  * V1.03 is known to be broken.  V3.04 is known to
1227                  * work.  Between, there are V1.06, V2.06 and V3.03
1228                  * that we don't have much idea about.  For now,
1229                  * blacklist anything older than V3.04.
1230                  *
1231                  * http://bugzilla.kernel.org/show_bug.cgi?id=15104
1232                  */
1233                 {
1234                         .ident = "G725",
1235                         .matches = {
1236                                 DMI_MATCH(DMI_SYS_VENDOR, "eMachines"),
1237                                 DMI_MATCH(DMI_PRODUCT_NAME, "eMachines G725"),
1238                         },
1239                         .driver_data = "20091216",      /* V3.04 */
1240                 },
1241                 { }     /* terminate list */
1242         };
1243         const struct dmi_system_id *dmi = dmi_first_match(sysids);
1244         int year, month, date;
1245         char buf[9];
1246 
1247         if (!dmi || pdev->bus->number || pdev->devfn != PCI_DEVFN(0x1f, 2))
1248                 return false;
1249 
1250         dmi_get_date(DMI_BIOS_DATE, &year, &month, &date);
1251         snprintf(buf, sizeof(buf), "%04d%02d%02d", year, month, date);
1252 
1253         return strcmp(buf, dmi->driver_data) < 0;
1254 }
1255 
1256 static bool ahci_broken_online(struct pci_dev *pdev)
1257 {
1258 #define ENCODE_BUSDEVFN(bus, slot, func)                        \
1259         (void *)(unsigned long)(((bus) << 8) | PCI_DEVFN((slot), (func)))
1260         static const struct dmi_system_id sysids[] = {
1261                 /*
1262                  * There are several gigabyte boards which use
1263                  * SIMG5723s configured as hardware RAID.  Certain
1264                  * 5723 firmware revisions shipped there keep the link
1265                  * online but fail to answer properly to SRST or
1266                  * IDENTIFY when no device is attached downstream
1267                  * causing libata to retry quite a few times leading
1268                  * to excessive detection delay.
1269                  *
1270                  * As these firmwares respond to the second reset try
1271                  * with invalid device signature, considering unknown
1272                  * sig as offline works around the problem acceptably.
1273                  */
1274                 {
1275                         .ident = "EP45-DQ6",
1276                         .matches = {
1277                                 DMI_MATCH(DMI_BOARD_VENDOR,
1278                                           "Gigabyte Technology Co., Ltd."),
1279                                 DMI_MATCH(DMI_BOARD_NAME, "EP45-DQ6"),
1280                         },
1281                         .driver_data = ENCODE_BUSDEVFN(0x0a, 0x00, 0),
1282                 },
1283                 {
1284                         .ident = "EP45-DS5",
1285                         .matches = {
1286                                 DMI_MATCH(DMI_BOARD_VENDOR,
1287                                           "Gigabyte Technology Co., Ltd."),
1288                                 DMI_MATCH(DMI_BOARD_NAME, "EP45-DS5"),
1289                         },
1290                         .driver_data = ENCODE_BUSDEVFN(0x03, 0x00, 0),
1291                 },
1292                 { }     /* terminate list */
1293         };
1294 #undef ENCODE_BUSDEVFN
1295         const struct dmi_system_id *dmi = dmi_first_match(sysids);
1296         unsigned int val;
1297 
1298         if (!dmi)
1299                 return false;
1300 
1301         val = (unsigned long)dmi->driver_data;
1302 
1303         return pdev->bus->number == (val >> 8) && pdev->devfn == (val & 0xff);
1304 }
1305 
1306 static bool ahci_broken_devslp(struct pci_dev *pdev)
1307 {
1308         /* device with broken DEVSLP but still showing SDS capability */
1309         static const struct pci_device_id ids[] = {
1310                 { PCI_VDEVICE(INTEL, 0x0f23)}, /* Valleyview SoC */
1311                 {}
1312         };
1313 
1314         return pci_match_id(ids, pdev);
1315 }
1316 
1317 #ifdef CONFIG_ATA_ACPI
1318 static void ahci_gtf_filter_workaround(struct ata_host *host)
1319 {
1320         static const struct dmi_system_id sysids[] = {
1321                 /*
1322                  * Aspire 3810T issues a bunch of SATA enable commands
1323                  * via _GTF including an invalid one and one which is
1324                  * rejected by the device.  Among the successful ones
1325                  * is FPDMA non-zero offset enable which when enabled
1326                  * only on the drive side leads to NCQ command
1327                  * failures.  Filter it out.
1328                  */
1329                 {
1330                         .ident = "Aspire 3810T",
1331                         .matches = {
1332                                 DMI_MATCH(DMI_SYS_VENDOR, "Acer"),
1333                                 DMI_MATCH(DMI_PRODUCT_NAME, "Aspire 3810T"),
1334                         },
1335                         .driver_data = (void *)ATA_ACPI_FILTER_FPDMA_OFFSET,
1336                 },
1337                 { }
1338         };
1339         const struct dmi_system_id *dmi = dmi_first_match(sysids);
1340         unsigned int filter;
1341         int i;
1342 
1343         if (!dmi)
1344                 return;
1345 
1346         filter = (unsigned long)dmi->driver_data;
1347         dev_info(host->dev, "applying extra ACPI _GTF filter 0x%x for %s\n",
1348                  filter, dmi->ident);
1349 
1350         for (i = 0; i < host->n_ports; i++) {
1351                 struct ata_port *ap = host->ports[i];
1352                 struct ata_link *link;
1353                 struct ata_device *dev;
1354 
1355                 ata_for_each_link(link, ap, EDGE)
1356                         ata_for_each_dev(dev, link, ALL)
1357                                 dev->gtf_filter |= filter;
1358         }
1359 }
1360 #else
1361 static inline void ahci_gtf_filter_workaround(struct ata_host *host)
1362 {}
1363 #endif
1364 
1365 #ifdef CONFIG_ARM64
1366 /*
1367  * Due to ERRATA#22536, ThunderX needs to handle HOST_IRQ_STAT differently.
1368  * Workaround is to make sure all pending IRQs are served before leaving
1369  * handler.
1370  */
1371 static irqreturn_t ahci_thunderx_irq_handler(int irq, void *dev_instance)
1372 {
1373         struct ata_host *host = dev_instance;
1374         struct ahci_host_priv *hpriv;
1375         unsigned int rc = 0;
1376         void __iomem *mmio;
1377         u32 irq_stat, irq_masked;
1378         unsigned int handled = 1;
1379 
1380         VPRINTK("ENTER\n");
1381         hpriv = host->private_data;
1382         mmio = hpriv->mmio;
1383         irq_stat = readl(mmio + HOST_IRQ_STAT);
1384         if (!irq_stat)
1385                 return IRQ_NONE;
1386 
1387         do {
1388                 irq_masked = irq_stat & hpriv->port_map;
1389                 spin_lock(&host->lock);
1390                 rc = ahci_handle_port_intr(host, irq_masked);
1391                 if (!rc)
1392                         handled = 0;
1393                 writel(irq_stat, mmio + HOST_IRQ_STAT);
1394                 irq_stat = readl(mmio + HOST_IRQ_STAT);
1395                 spin_unlock(&host->lock);
1396         } while (irq_stat);
1397         VPRINTK("EXIT\n");
1398 
1399         return IRQ_RETVAL(handled);
1400 }
1401 #endif
1402 
1403 /*
1404  * ahci_init_msix() - optionally enable per-port MSI-X otherwise defer
1405  * to single msi.
1406  */
1407 static int ahci_init_msix(struct pci_dev *pdev, unsigned int n_ports,
1408                           struct ahci_host_priv *hpriv, unsigned long flags)
1409 {
1410         int nvec, i, rc;
1411 
1412         /* Do not init MSI-X if MSI is disabled for the device */
1413         if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1414                 return -ENODEV;
1415 
1416         nvec = pci_msix_vec_count(pdev);
1417         if (nvec < 0)
1418                 return nvec;
1419 
1420         /*
1421          * Proper MSI-X implementations will have a vector per-port.
1422          * Barring that, we prefer single-MSI over single-MSIX.  If this
1423          * check fails (not enough MSI-X vectors for all ports) we will
1424          * be called again with the flag clear iff ahci_init_msi()
1425          * fails.
1426          */
1427         if (flags & AHCI_HFLAG_MULTI_MSIX) {
1428                 if (nvec < n_ports)
1429                         return -ENODEV;
1430                 nvec = n_ports;
1431         } else if (nvec) {
1432                 nvec = 1;
1433         } else {
1434                 /*
1435                  * Emit dev_err() since this was the non-legacy irq
1436                  * method of last resort.
1437                  */
1438                 rc = -ENODEV;
1439                 goto fail;
1440         }
1441 
1442         for (i = 0; i < nvec; i++)
1443                 hpriv->msix[i].entry = i;
1444         rc = pci_enable_msix_exact(pdev, hpriv->msix, nvec);
1445         if (rc < 0)
1446                 goto fail;
1447 
1448         if (nvec > 1)
1449                 hpriv->flags |= AHCI_HFLAG_MULTI_MSIX;
1450         hpriv->irq = hpriv->msix[0].vector; /* for single msi-x */
1451 
1452         return nvec;
1453 fail:
1454         dev_err(&pdev->dev,
1455                 "failed to enable MSI-X with error %d, # of vectors: %d\n",
1456                 rc, nvec);
1457 
1458         return rc;
1459 }
1460 
1461 static int ahci_init_msi(struct pci_dev *pdev, unsigned int n_ports,
1462                         struct ahci_host_priv *hpriv)
1463 {
1464         int rc, nvec;
1465 
1466         if (hpriv->flags & AHCI_HFLAG_NO_MSI)
1467                 return -ENODEV;
1468 
1469         nvec = pci_msi_vec_count(pdev);
1470         if (nvec < 0)
1471                 return nvec;
1472 
1473         /*
1474          * If number of MSIs is less than number of ports then Sharing Last
1475          * Message mode could be enforced. In this case assume that advantage
1476          * of multipe MSIs is negated and use single MSI mode instead.
1477          */
1478         if (nvec < n_ports)
1479                 goto single_msi;
1480 
1481         rc = pci_enable_msi_exact(pdev, nvec);
1482         if (rc == -ENOSPC)
1483                 goto single_msi;
1484         if (rc < 0)
1485                 return rc;
1486 
1487         /* fallback to single MSI mode if the controller enforced MRSM mode */
1488         if (readl(hpriv->mmio + HOST_CTL) & HOST_MRSM) {
1489                 pci_disable_msi(pdev);
1490                 printk(KERN_INFO "ahci: MRSM is on, fallback to single MSI\n");
1491                 goto single_msi;
1492         }
1493 
1494         if (nvec > 1)
1495                 hpriv->flags |= AHCI_HFLAG_MULTI_MSI;
1496 
1497         goto out;
1498 
1499 single_msi:
1500         nvec = 1;
1501 
1502         rc = pci_enable_msi(pdev);
1503         if (rc < 0)
1504                 return rc;
1505 out:
1506         hpriv->irq = pdev->irq;
1507 
1508         return nvec;
1509 }
1510 
1511 static int ahci_init_interrupts(struct pci_dev *pdev, unsigned int n_ports,
1512                                 struct ahci_host_priv *hpriv)
1513 {
1514         int nvec;
1515 
1516         /*
1517          * Try to enable per-port MSI-X.  If the host is not capable
1518          * fall back to single MSI before finally attempting single
1519          * MSI-X.
1520          */
1521         nvec = ahci_init_msix(pdev, n_ports, hpriv, AHCI_HFLAG_MULTI_MSIX);
1522         if (nvec >= 0)
1523                 return nvec;
1524 
1525         nvec = ahci_init_msi(pdev, n_ports, hpriv);
1526         if (nvec >= 0)
1527                 return nvec;
1528 
1529         /* try single-msix */
1530         nvec = ahci_init_msix(pdev, n_ports, hpriv, 0);
1531         if (nvec >= 0)
1532                 return nvec;
1533 
1534         /* legacy intx interrupts */
1535         pci_intx(pdev, 1);
1536         hpriv->irq = pdev->irq;
1537 
1538         return 0;
1539 }
1540 
1541 static int ahci_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
1542 {
1543         unsigned int board_id = ent->driver_data;
1544         struct ata_port_info pi = ahci_port_info[board_id];
1545         const struct ata_port_info *ppi[] = { &pi, NULL };
1546         struct device *dev = &pdev->dev;
1547         struct ahci_host_priv *hpriv;
1548         struct ata_host *host;
1549         int n_ports, i, rc;
1550         int ahci_pci_bar = AHCI_PCI_BAR_STANDARD;
1551 
1552         VPRINTK("ENTER\n");
1553 
1554         WARN_ON((int)ATA_MAX_QUEUE > AHCI_MAX_CMDS);
1555 
1556         ata_print_version_once(&pdev->dev, DRV_VERSION);
1557 
1558         /* The AHCI driver can only drive the SATA ports, the PATA driver
1559            can drive them all so if both drivers are selected make sure
1560            AHCI stays out of the way */
1561         if (pdev->vendor == PCI_VENDOR_ID_MARVELL && !marvell_enable)
1562                 return -ENODEV;
1563 
1564         /* Apple BIOS on MCP89 prevents us using AHCI */
1565         if (is_mcp89_apple(pdev))
1566                 ahci_mcp89_apple_enable(pdev);
1567 
1568         /* Promise's PDC42819 is a SAS/SATA controller that has an AHCI mode.
1569          * At the moment, we can only use the AHCI mode. Let the users know
1570          * that for SAS drives they're out of luck.
1571          */
1572         if (pdev->vendor == PCI_VENDOR_ID_PROMISE)
1573                 dev_info(&pdev->dev,
1574                          "PDC42819 can only drive SATA devices with this driver\n");
1575 
1576         /* Some devices use non-standard BARs */
1577         if (pdev->vendor == PCI_VENDOR_ID_STMICRO && pdev->device == 0xCC06)
1578                 ahci_pci_bar = AHCI_PCI_BAR_STA2X11;
1579         else if (pdev->vendor == 0x1c44 && pdev->device == 0x8000)
1580                 ahci_pci_bar = AHCI_PCI_BAR_ENMOTUS;
1581         else if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1582                 ahci_pci_bar = AHCI_PCI_BAR_CAVIUM;
1583 
1584         /* acquire resources */
1585         rc = pcim_enable_device(pdev);
1586         if (rc)
1587                 return rc;
1588 
1589         if (pdev->vendor == PCI_VENDOR_ID_INTEL &&
1590             (pdev->device == 0x2652 || pdev->device == 0x2653)) {
1591                 u8 map;
1592 
1593                 /* ICH6s share the same PCI ID for both piix and ahci
1594                  * modes.  Enabling ahci mode while MAP indicates
1595                  * combined mode is a bad idea.  Yield to ata_piix.
1596                  */
1597                 pci_read_config_byte(pdev, ICH_MAP, &map);
1598                 if (map & 0x3) {
1599                         dev_info(&pdev->dev,
1600                                  "controller is in combined mode, can't enable AHCI mode\n");
1601                         return -ENODEV;
1602                 }
1603         }
1604 
1605         /* AHCI controllers often implement SFF compatible interface.
1606          * Grab all PCI BARs just in case.
1607          */
1608         rc = pcim_iomap_regions_request_all(pdev, 1 << ahci_pci_bar, DRV_NAME);
1609         if (rc == -EBUSY)
1610                 pcim_pin_device(pdev);
1611         if (rc)
1612                 return rc;
1613 
1614         hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
1615         if (!hpriv)
1616                 return -ENOMEM;
1617         hpriv->flags |= (unsigned long)pi.private_data;
1618 
1619         /* MCP65 revision A1 and A2 can't do MSI */
1620         if (board_id == board_ahci_mcp65 &&
1621             (pdev->revision == 0xa1 || pdev->revision == 0xa2))
1622                 hpriv->flags |= AHCI_HFLAG_NO_MSI;
1623 
1624         /* SB800 does NOT need the workaround to ignore SERR_INTERNAL */
1625         if (board_id == board_ahci_sb700 && pdev->revision >= 0x40)
1626                 hpriv->flags &= ~AHCI_HFLAG_IGN_SERR_INTERNAL;
1627 
1628         /* only some SB600s can do 64bit DMA */
1629         if (ahci_sb600_enable_64bit(pdev))
1630                 hpriv->flags &= ~AHCI_HFLAG_32BIT_ONLY;
1631 
1632         hpriv->mmio = pcim_iomap_table(pdev)[ahci_pci_bar];
1633 
1634         /* must set flag prior to save config in order to take effect */
1635         if (ahci_broken_devslp(pdev))
1636                 hpriv->flags |= AHCI_HFLAG_NO_DEVSLP;
1637 
1638 #ifdef CONFIG_ARM64
1639         if (pdev->vendor == 0x177d && pdev->device == 0xa01c)
1640                 hpriv->irq_handler = ahci_thunderx_irq_handler;
1641 #endif
1642 
1643         /* save initial config */
1644         ahci_pci_save_initial_config(pdev, hpriv);
1645 
1646         /* prepare host */
1647         if (hpriv->cap & HOST_CAP_NCQ) {
1648                 pi.flags |= ATA_FLAG_NCQ;
1649                 /*
1650                  * Auto-activate optimization is supposed to be
1651                  * supported on all AHCI controllers indicating NCQ
1652                  * capability, but it seems to be broken on some
1653                  * chipsets including NVIDIAs.
1654                  */
1655                 if (!(hpriv->flags & AHCI_HFLAG_NO_FPDMA_AA))
1656                         pi.flags |= ATA_FLAG_FPDMA_AA;
1657 
1658                 /*
1659                  * All AHCI controllers should be forward-compatible
1660                  * with the new auxiliary field. This code should be
1661                  * conditionalized if any buggy AHCI controllers are
1662                  * encountered.
1663                  */
1664                 pi.flags |= ATA_FLAG_FPDMA_AUX;
1665         }
1666 
1667         if (hpriv->cap & HOST_CAP_PMP)
1668                 pi.flags |= ATA_FLAG_PMP;
1669 
1670         ahci_set_em_messages(hpriv, &pi);
1671 
1672         if (ahci_broken_system_poweroff(pdev)) {
1673                 pi.flags |= ATA_FLAG_NO_POWEROFF_SPINDOWN;
1674                 dev_info(&pdev->dev,
1675                         "quirky BIOS, skipping spindown on poweroff\n");
1676         }
1677 
1678         if (ahci_broken_suspend(pdev)) {
1679                 hpriv->flags |= AHCI_HFLAG_NO_SUSPEND;
1680                 dev_warn(&pdev->dev,
1681                          "BIOS update required for suspend/resume\n");
1682         }
1683 
1684         if (ahci_broken_online(pdev)) {
1685                 hpriv->flags |= AHCI_HFLAG_SRST_TOUT_IS_OFFLINE;
1686                 dev_info(&pdev->dev,
1687                          "online status unreliable, applying workaround\n");
1688         }
1689 
1690         /* CAP.NP sometimes indicate the index of the last enabled
1691          * port, at other times, that of the last possible port, so
1692          * determining the maximum port number requires looking at
1693          * both CAP.NP and port_map.
1694          */
1695         n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
1696 
1697         host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
1698         if (!host)
1699                 return -ENOMEM;
1700         host->private_data = hpriv;
1701         hpriv->msix = devm_kzalloc(&pdev->dev,
1702                         sizeof(struct msix_entry) * n_ports, GFP_KERNEL);
1703         if (!hpriv->msix)
1704                 return -ENOMEM;
1705         ahci_init_interrupts(pdev, n_ports, hpriv);
1706 
1707         if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
1708                 host->flags |= ATA_HOST_PARALLEL_SCAN;
1709         else
1710                 dev_info(&pdev->dev, "SSS flag set, parallel bus scan disabled\n");
1711 
1712         if (pi.flags & ATA_FLAG_EM)
1713                 ahci_reset_em(host);
1714 
1715         for (i = 0; i < host->n_ports; i++) {
1716                 struct ata_port *ap = host->ports[i];
1717 
1718                 ata_port_pbar_desc(ap, ahci_pci_bar, -1, "abar");
1719                 ata_port_pbar_desc(ap, ahci_pci_bar,
1720                                    0x100 + ap->port_no * 0x80, "port");
1721 
1722                 /* set enclosure management message type */
1723                 if (ap->flags & ATA_FLAG_EM)
1724                         ap->em_message_type = hpriv->em_msg_type;
1725 
1726 
1727                 /* disabled/not-implemented port */
1728                 if (!(hpriv->port_map & (1 << i)))
1729                         ap->ops = &ata_dummy_port_ops;
1730         }
1731 
1732         /* apply workaround for ASUS P5W DH Deluxe mainboard */
1733         ahci_p5wdh_workaround(host);
1734 
1735         /* apply gtf filter quirk */
1736         ahci_gtf_filter_workaround(host);
1737 
1738         /* initialize adapter */
1739         rc = ahci_configure_dma_masks(pdev, hpriv->cap & HOST_CAP_64);
1740         if (rc)
1741                 return rc;
1742 
1743         rc = ahci_pci_reset_controller(host);
1744         if (rc)
1745                 return rc;
1746 
1747         ahci_pci_init_controller(host);
1748         ahci_pci_print_info(host);
1749 
1750         pci_set_master(pdev);
1751 
1752         rc = ahci_host_activate(host, &ahci_sht);
1753         if (rc)
1754                 return rc;
1755 
1756         pm_runtime_put_noidle(&pdev->dev);
1757         return 0;
1758 }
1759 
1760 static void ahci_remove_one(struct pci_dev *pdev)
1761 {
1762         pm_runtime_get_noresume(&pdev->dev);
1763         ata_pci_remove_one(pdev);
1764 }
1765 
1766 module_pci_driver(ahci_pci_driver);
1767 
1768 MODULE_AUTHOR("Jeff Garzik");
1769 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1770 MODULE_LICENSE("GPL");
1771 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1772 MODULE_VERSION(DRV_VERSION);
1773 

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