Version:  2.0.40 2.2.26 2.4.37 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9

Linux/drivers/acpi/acpi_lpss.c

  1 /*
  2  * ACPI support for Intel Lynxpoint LPSS.
  3  *
  4  * Copyright (C) 2013, Intel Corporation
  5  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
  6  *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License version 2 as
 10  * published by the Free Software Foundation.
 11  */
 12 
 13 #include <linux/acpi.h>
 14 #include <linux/clkdev.h>
 15 #include <linux/clk-provider.h>
 16 #include <linux/err.h>
 17 #include <linux/io.h>
 18 #include <linux/mutex.h>
 19 #include <linux/platform_device.h>
 20 #include <linux/platform_data/clk-lpss.h>
 21 #include <linux/pm_domain.h>
 22 #include <linux/pm_runtime.h>
 23 #include <linux/delay.h>
 24 
 25 #include "internal.h"
 26 
 27 ACPI_MODULE_NAME("acpi_lpss");
 28 
 29 #ifdef CONFIG_X86_INTEL_LPSS
 30 
 31 #include <asm/cpu_device_id.h>
 32 #include <asm/intel-family.h>
 33 #include <asm/iosf_mbi.h>
 34 #include <asm/pmc_atom.h>
 35 
 36 #define LPSS_ADDR(desc) ((unsigned long)&desc)
 37 
 38 #define LPSS_CLK_SIZE   0x04
 39 #define LPSS_LTR_SIZE   0x18
 40 
 41 /* Offsets relative to LPSS_PRIVATE_OFFSET */
 42 #define LPSS_CLK_DIVIDER_DEF_MASK       (BIT(1) | BIT(16))
 43 #define LPSS_RESETS                     0x04
 44 #define LPSS_RESETS_RESET_FUNC          BIT(0)
 45 #define LPSS_RESETS_RESET_APB           BIT(1)
 46 #define LPSS_GENERAL                    0x08
 47 #define LPSS_GENERAL_LTR_MODE_SW        BIT(2)
 48 #define LPSS_GENERAL_UART_RTS_OVRD      BIT(3)
 49 #define LPSS_SW_LTR                     0x10
 50 #define LPSS_AUTO_LTR                   0x14
 51 #define LPSS_LTR_SNOOP_REQ              BIT(15)
 52 #define LPSS_LTR_SNOOP_MASK             0x0000FFFF
 53 #define LPSS_LTR_SNOOP_LAT_1US          0x800
 54 #define LPSS_LTR_SNOOP_LAT_32US         0xC00
 55 #define LPSS_LTR_SNOOP_LAT_SHIFT        5
 56 #define LPSS_LTR_SNOOP_LAT_CUTOFF       3000
 57 #define LPSS_LTR_MAX_VAL                0x3FF
 58 #define LPSS_TX_INT                     0x20
 59 #define LPSS_TX_INT_MASK                BIT(1)
 60 
 61 #define LPSS_PRV_REG_COUNT              9
 62 
 63 /* LPSS Flags */
 64 #define LPSS_CLK                        BIT(0)
 65 #define LPSS_CLK_GATE                   BIT(1)
 66 #define LPSS_CLK_DIVIDER                BIT(2)
 67 #define LPSS_LTR                        BIT(3)
 68 #define LPSS_SAVE_CTX                   BIT(4)
 69 #define LPSS_NO_D3_DELAY                BIT(5)
 70 
 71 struct lpss_private_data;
 72 
 73 struct lpss_device_desc {
 74         unsigned int flags;
 75         const char *clk_con_id;
 76         unsigned int prv_offset;
 77         size_t prv_size_override;
 78         struct property_entry *properties;
 79         void (*setup)(struct lpss_private_data *pdata);
 80 };
 81 
 82 static const struct lpss_device_desc lpss_dma_desc = {
 83         .flags = LPSS_CLK,
 84 };
 85 
 86 struct lpss_private_data {
 87         void __iomem *mmio_base;
 88         resource_size_t mmio_size;
 89         unsigned int fixed_clk_rate;
 90         struct clk *clk;
 91         const struct lpss_device_desc *dev_desc;
 92         u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
 93 };
 94 
 95 /* LPSS run time quirks */
 96 static unsigned int lpss_quirks;
 97 
 98 /*
 99  * LPSS_QUIRK_ALWAYS_POWER_ON: override power state for LPSS DMA device.
100  *
101  * The LPSS DMA controller has neither _PS0 nor _PS3 method. Moreover
102  * it can be powered off automatically whenever the last LPSS device goes down.
103  * In case of no power any access to the DMA controller will hang the system.
104  * The behaviour is reproduced on some HP laptops based on Intel BayTrail as
105  * well as on ASuS T100TA transformer.
106  *
107  * This quirk overrides power state of entire LPSS island to keep DMA powered
108  * on whenever we have at least one other device in use.
109  */
110 #define LPSS_QUIRK_ALWAYS_POWER_ON      BIT(0)
111 
112 /* UART Component Parameter Register */
113 #define LPSS_UART_CPR                   0xF4
114 #define LPSS_UART_CPR_AFCE              BIT(4)
115 
116 static void lpss_uart_setup(struct lpss_private_data *pdata)
117 {
118         unsigned int offset;
119         u32 val;
120 
121         offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
122         val = readl(pdata->mmio_base + offset);
123         writel(val | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
124 
125         val = readl(pdata->mmio_base + LPSS_UART_CPR);
126         if (!(val & LPSS_UART_CPR_AFCE)) {
127                 offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
128                 val = readl(pdata->mmio_base + offset);
129                 val |= LPSS_GENERAL_UART_RTS_OVRD;
130                 writel(val, pdata->mmio_base + offset);
131         }
132 }
133 
134 static void lpss_deassert_reset(struct lpss_private_data *pdata)
135 {
136         unsigned int offset;
137         u32 val;
138 
139         offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
140         val = readl(pdata->mmio_base + offset);
141         val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
142         writel(val, pdata->mmio_base + offset);
143 }
144 
145 #define LPSS_I2C_ENABLE                 0x6c
146 
147 static void byt_i2c_setup(struct lpss_private_data *pdata)
148 {
149         lpss_deassert_reset(pdata);
150 
151         if (readl(pdata->mmio_base + pdata->dev_desc->prv_offset))
152                 pdata->fixed_clk_rate = 133000000;
153 
154         writel(0, pdata->mmio_base + LPSS_I2C_ENABLE);
155 }
156 
157 static const struct lpss_device_desc lpt_dev_desc = {
158         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
159         .prv_offset = 0x800,
160 };
161 
162 static const struct lpss_device_desc lpt_i2c_dev_desc = {
163         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_LTR,
164         .prv_offset = 0x800,
165 };
166 
167 static struct property_entry uart_properties[] = {
168         PROPERTY_ENTRY_U32("reg-io-width", 4),
169         PROPERTY_ENTRY_U32("reg-shift", 2),
170         PROPERTY_ENTRY_BOOL("snps,uart-16550-compatible"),
171         { },
172 };
173 
174 static const struct lpss_device_desc lpt_uart_dev_desc = {
175         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_LTR,
176         .clk_con_id = "baudclk",
177         .prv_offset = 0x800,
178         .setup = lpss_uart_setup,
179         .properties = uart_properties,
180 };
181 
182 static const struct lpss_device_desc lpt_sdio_dev_desc = {
183         .flags = LPSS_LTR,
184         .prv_offset = 0x1000,
185         .prv_size_override = 0x1018,
186 };
187 
188 static const struct lpss_device_desc byt_pwm_dev_desc = {
189         .flags = LPSS_SAVE_CTX,
190 };
191 
192 static const struct lpss_device_desc bsw_pwm_dev_desc = {
193         .flags = LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
194 };
195 
196 static const struct lpss_device_desc byt_uart_dev_desc = {
197         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
198         .clk_con_id = "baudclk",
199         .prv_offset = 0x800,
200         .setup = lpss_uart_setup,
201         .properties = uart_properties,
202 };
203 
204 static const struct lpss_device_desc bsw_uart_dev_desc = {
205         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
206                         | LPSS_NO_D3_DELAY,
207         .clk_con_id = "baudclk",
208         .prv_offset = 0x800,
209         .setup = lpss_uart_setup,
210         .properties = uart_properties,
211 };
212 
213 static const struct lpss_device_desc byt_spi_dev_desc = {
214         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX,
215         .prv_offset = 0x400,
216 };
217 
218 static const struct lpss_device_desc byt_sdio_dev_desc = {
219         .flags = LPSS_CLK,
220 };
221 
222 static const struct lpss_device_desc byt_i2c_dev_desc = {
223         .flags = LPSS_CLK | LPSS_SAVE_CTX,
224         .prv_offset = 0x800,
225         .setup = byt_i2c_setup,
226 };
227 
228 static const struct lpss_device_desc bsw_i2c_dev_desc = {
229         .flags = LPSS_CLK | LPSS_SAVE_CTX | LPSS_NO_D3_DELAY,
230         .prv_offset = 0x800,
231         .setup = byt_i2c_setup,
232 };
233 
234 static const struct lpss_device_desc bsw_spi_dev_desc = {
235         .flags = LPSS_CLK | LPSS_CLK_GATE | LPSS_CLK_DIVIDER | LPSS_SAVE_CTX
236                         | LPSS_NO_D3_DELAY,
237         .prv_offset = 0x400,
238         .setup = lpss_deassert_reset,
239 };
240 
241 #define ICPU(model)     { X86_VENDOR_INTEL, 6, model, X86_FEATURE_ANY, }
242 
243 static const struct x86_cpu_id lpss_cpu_ids[] = {
244         ICPU(INTEL_FAM6_ATOM_SILVERMONT1),      /* Valleyview, Bay Trail */
245         ICPU(INTEL_FAM6_ATOM_AIRMONT),  /* Braswell, Cherry Trail */
246         {}
247 };
248 
249 #else
250 
251 #define LPSS_ADDR(desc) (0UL)
252 
253 #endif /* CONFIG_X86_INTEL_LPSS */
254 
255 static const struct acpi_device_id acpi_lpss_device_ids[] = {
256         /* Generic LPSS devices */
257         { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
258 
259         /* Lynxpoint LPSS devices */
260         { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
261         { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
262         { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
263         { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
264         { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
265         { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
266         { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
267         { "INT33C7", },
268 
269         /* BayTrail LPSS devices */
270         { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
271         { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
272         { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
273         { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
274         { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
275         { "INT33B2", },
276         { "INT33FC", },
277 
278         /* Braswell LPSS devices */
279         { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
280         { "8086228A", LPSS_ADDR(bsw_uart_dev_desc) },
281         { "8086228E", LPSS_ADDR(bsw_spi_dev_desc) },
282         { "808622C1", LPSS_ADDR(bsw_i2c_dev_desc) },
283 
284         /* Broadwell LPSS devices */
285         { "INT3430", LPSS_ADDR(lpt_dev_desc) },
286         { "INT3431", LPSS_ADDR(lpt_dev_desc) },
287         { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
288         { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
289         { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
290         { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
291         { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
292         { "INT3437", },
293 
294         /* Wildcat Point LPSS devices */
295         { "INT3438", LPSS_ADDR(lpt_dev_desc) },
296 
297         { }
298 };
299 
300 #ifdef CONFIG_X86_INTEL_LPSS
301 
302 static int is_memory(struct acpi_resource *res, void *not_used)
303 {
304         struct resource r;
305         return !acpi_dev_resource_memory(res, &r);
306 }
307 
308 /* LPSS main clock device. */
309 static struct platform_device *lpss_clk_dev;
310 
311 static inline void lpt_register_clock_device(void)
312 {
313         lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
314 }
315 
316 static int register_device_clock(struct acpi_device *adev,
317                                  struct lpss_private_data *pdata)
318 {
319         const struct lpss_device_desc *dev_desc = pdata->dev_desc;
320         const char *devname = dev_name(&adev->dev);
321         struct clk *clk = ERR_PTR(-ENODEV);
322         struct lpss_clk_data *clk_data;
323         const char *parent, *clk_name;
324         void __iomem *prv_base;
325 
326         if (!lpss_clk_dev)
327                 lpt_register_clock_device();
328 
329         clk_data = platform_get_drvdata(lpss_clk_dev);
330         if (!clk_data)
331                 return -ENODEV;
332         clk = clk_data->clk;
333 
334         if (!pdata->mmio_base
335             || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
336                 return -ENODATA;
337 
338         parent = clk_data->name;
339         prv_base = pdata->mmio_base + dev_desc->prv_offset;
340 
341         if (pdata->fixed_clk_rate) {
342                 clk = clk_register_fixed_rate(NULL, devname, parent, 0,
343                                               pdata->fixed_clk_rate);
344                 goto out;
345         }
346 
347         if (dev_desc->flags & LPSS_CLK_GATE) {
348                 clk = clk_register_gate(NULL, devname, parent, 0,
349                                         prv_base, 0, 0, NULL);
350                 parent = devname;
351         }
352 
353         if (dev_desc->flags & LPSS_CLK_DIVIDER) {
354                 /* Prevent division by zero */
355                 if (!readl(prv_base))
356                         writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
357 
358                 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
359                 if (!clk_name)
360                         return -ENOMEM;
361                 clk = clk_register_fractional_divider(NULL, clk_name, parent,
362                                                       0, prv_base,
363                                                       1, 15, 16, 15, 0, NULL);
364                 parent = clk_name;
365 
366                 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
367                 if (!clk_name) {
368                         kfree(parent);
369                         return -ENOMEM;
370                 }
371                 clk = clk_register_gate(NULL, clk_name, parent,
372                                         CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
373                                         prv_base, 31, 0, NULL);
374                 kfree(parent);
375                 kfree(clk_name);
376         }
377 out:
378         if (IS_ERR(clk))
379                 return PTR_ERR(clk);
380 
381         pdata->clk = clk;
382         clk_register_clkdev(clk, dev_desc->clk_con_id, devname);
383         return 0;
384 }
385 
386 static int acpi_lpss_create_device(struct acpi_device *adev,
387                                    const struct acpi_device_id *id)
388 {
389         const struct lpss_device_desc *dev_desc;
390         struct lpss_private_data *pdata;
391         struct resource_entry *rentry;
392         struct list_head resource_list;
393         struct platform_device *pdev;
394         int ret;
395 
396         dev_desc = (const struct lpss_device_desc *)id->driver_data;
397         if (!dev_desc) {
398                 pdev = acpi_create_platform_device(adev, NULL);
399                 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
400         }
401         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
402         if (!pdata)
403                 return -ENOMEM;
404 
405         INIT_LIST_HEAD(&resource_list);
406         ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
407         if (ret < 0)
408                 goto err_out;
409 
410         list_for_each_entry(rentry, &resource_list, node)
411                 if (resource_type(rentry->res) == IORESOURCE_MEM) {
412                         if (dev_desc->prv_size_override)
413                                 pdata->mmio_size = dev_desc->prv_size_override;
414                         else
415                                 pdata->mmio_size = resource_size(rentry->res);
416                         pdata->mmio_base = ioremap(rentry->res->start,
417                                                    pdata->mmio_size);
418                         break;
419                 }
420 
421         acpi_dev_free_resource_list(&resource_list);
422 
423         if (!pdata->mmio_base) {
424                 ret = -ENOMEM;
425                 goto err_out;
426         }
427 
428         pdata->dev_desc = dev_desc;
429 
430         if (dev_desc->setup)
431                 dev_desc->setup(pdata);
432 
433         if (dev_desc->flags & LPSS_CLK) {
434                 ret = register_device_clock(adev, pdata);
435                 if (ret) {
436                         /* Skip the device, but continue the namespace scan. */
437                         ret = 0;
438                         goto err_out;
439                 }
440         }
441 
442         /*
443          * This works around a known issue in ACPI tables where LPSS devices
444          * have _PS0 and _PS3 without _PSC (and no power resources), so
445          * acpi_bus_init_power() will assume that the BIOS has put them into D0.
446          */
447         ret = acpi_device_fix_up_power(adev);
448         if (ret) {
449                 /* Skip the device, but continue the namespace scan. */
450                 ret = 0;
451                 goto err_out;
452         }
453 
454         adev->driver_data = pdata;
455         pdev = acpi_create_platform_device(adev, dev_desc->properties);
456         if (!IS_ERR_OR_NULL(pdev)) {
457                 return 1;
458         }
459 
460         ret = PTR_ERR(pdev);
461         adev->driver_data = NULL;
462 
463  err_out:
464         kfree(pdata);
465         return ret;
466 }
467 
468 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
469 {
470         return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
471 }
472 
473 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
474                              unsigned int reg)
475 {
476         writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
477 }
478 
479 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
480 {
481         struct acpi_device *adev;
482         struct lpss_private_data *pdata;
483         unsigned long flags;
484         int ret;
485 
486         ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
487         if (WARN_ON(ret))
488                 return ret;
489 
490         spin_lock_irqsave(&dev->power.lock, flags);
491         if (pm_runtime_suspended(dev)) {
492                 ret = -EAGAIN;
493                 goto out;
494         }
495         pdata = acpi_driver_data(adev);
496         if (WARN_ON(!pdata || !pdata->mmio_base)) {
497                 ret = -ENODEV;
498                 goto out;
499         }
500         *val = __lpss_reg_read(pdata, reg);
501 
502  out:
503         spin_unlock_irqrestore(&dev->power.lock, flags);
504         return ret;
505 }
506 
507 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
508                              char *buf)
509 {
510         u32 ltr_value = 0;
511         unsigned int reg;
512         int ret;
513 
514         reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
515         ret = lpss_reg_read(dev, reg, &ltr_value);
516         if (ret)
517                 return ret;
518 
519         return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
520 }
521 
522 static ssize_t lpss_ltr_mode_show(struct device *dev,
523                                   struct device_attribute *attr, char *buf)
524 {
525         u32 ltr_mode = 0;
526         char *outstr;
527         int ret;
528 
529         ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
530         if (ret)
531                 return ret;
532 
533         outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
534         return sprintf(buf, "%s\n", outstr);
535 }
536 
537 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
538 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
539 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
540 
541 static struct attribute *lpss_attrs[] = {
542         &dev_attr_auto_ltr.attr,
543         &dev_attr_sw_ltr.attr,
544         &dev_attr_ltr_mode.attr,
545         NULL,
546 };
547 
548 static struct attribute_group lpss_attr_group = {
549         .attrs = lpss_attrs,
550         .name = "lpss_ltr",
551 };
552 
553 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
554 {
555         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
556         u32 ltr_mode, ltr_val;
557 
558         ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
559         if (val < 0) {
560                 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
561                         ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
562                         __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
563                 }
564                 return;
565         }
566         ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
567         if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
568                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
569                 val = LPSS_LTR_MAX_VAL;
570         } else if (val > LPSS_LTR_MAX_VAL) {
571                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
572                 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
573         } else {
574                 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
575         }
576         ltr_val |= val;
577         __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
578         if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
579                 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
580                 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
581         }
582 }
583 
584 #ifdef CONFIG_PM
585 /**
586  * acpi_lpss_save_ctx() - Save the private registers of LPSS device
587  * @dev: LPSS device
588  * @pdata: pointer to the private data of the LPSS device
589  *
590  * Most LPSS devices have private registers which may loose their context when
591  * the device is powered down. acpi_lpss_save_ctx() saves those registers into
592  * prv_reg_ctx array.
593  */
594 static void acpi_lpss_save_ctx(struct device *dev,
595                                struct lpss_private_data *pdata)
596 {
597         unsigned int i;
598 
599         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
600                 unsigned long offset = i * sizeof(u32);
601 
602                 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
603                 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
604                         pdata->prv_reg_ctx[i], offset);
605         }
606 }
607 
608 /**
609  * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
610  * @dev: LPSS device
611  * @pdata: pointer to the private data of the LPSS device
612  *
613  * Restores the registers that were previously stored with acpi_lpss_save_ctx().
614  */
615 static void acpi_lpss_restore_ctx(struct device *dev,
616                                   struct lpss_private_data *pdata)
617 {
618         unsigned int i;
619 
620         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
621                 unsigned long offset = i * sizeof(u32);
622 
623                 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
624                 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
625                         pdata->prv_reg_ctx[i], offset);
626         }
627 }
628 
629 static void acpi_lpss_d3_to_d0_delay(struct lpss_private_data *pdata)
630 {
631         /*
632          * The following delay is needed or the subsequent write operations may
633          * fail. The LPSS devices are actually PCI devices and the PCI spec
634          * expects 10ms delay before the device can be accessed after D3 to D0
635          * transition. However some platforms like BSW does not need this delay.
636          */
637         unsigned int delay = 10;        /* default 10ms delay */
638 
639         if (pdata->dev_desc->flags & LPSS_NO_D3_DELAY)
640                 delay = 0;
641 
642         msleep(delay);
643 }
644 
645 static int acpi_lpss_activate(struct device *dev)
646 {
647         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
648         int ret;
649 
650         ret = acpi_dev_runtime_resume(dev);
651         if (ret)
652                 return ret;
653 
654         acpi_lpss_d3_to_d0_delay(pdata);
655 
656         /*
657          * This is called only on ->probe() stage where a device is either in
658          * known state defined by BIOS or most likely powered off. Due to this
659          * we have to deassert reset line to be sure that ->probe() will
660          * recognize the device.
661          */
662         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
663                 lpss_deassert_reset(pdata);
664 
665         return 0;
666 }
667 
668 static void acpi_lpss_dismiss(struct device *dev)
669 {
670         acpi_dev_runtime_suspend(dev);
671 }
672 
673 #ifdef CONFIG_PM_SLEEP
674 static int acpi_lpss_suspend_late(struct device *dev)
675 {
676         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
677         int ret;
678 
679         ret = pm_generic_suspend_late(dev);
680         if (ret)
681                 return ret;
682 
683         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
684                 acpi_lpss_save_ctx(dev, pdata);
685 
686         return acpi_dev_suspend_late(dev);
687 }
688 
689 static int acpi_lpss_resume_early(struct device *dev)
690 {
691         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
692         int ret;
693 
694         ret = acpi_dev_resume_early(dev);
695         if (ret)
696                 return ret;
697 
698         acpi_lpss_d3_to_d0_delay(pdata);
699 
700         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
701                 acpi_lpss_restore_ctx(dev, pdata);
702 
703         return pm_generic_resume_early(dev);
704 }
705 #endif /* CONFIG_PM_SLEEP */
706 
707 /* IOSF SB for LPSS island */
708 #define LPSS_IOSF_UNIT_LPIOEP           0xA0
709 #define LPSS_IOSF_UNIT_LPIO1            0xAB
710 #define LPSS_IOSF_UNIT_LPIO2            0xAC
711 
712 #define LPSS_IOSF_PMCSR                 0x84
713 #define LPSS_PMCSR_D0                   0
714 #define LPSS_PMCSR_D3hot                3
715 #define LPSS_PMCSR_Dx_MASK              GENMASK(1, 0)
716 
717 #define LPSS_IOSF_GPIODEF0              0x154
718 #define LPSS_GPIODEF0_DMA1_D3           BIT(2)
719 #define LPSS_GPIODEF0_DMA2_D3           BIT(3)
720 #define LPSS_GPIODEF0_DMA_D3_MASK       GENMASK(3, 2)
721 
722 static DEFINE_MUTEX(lpss_iosf_mutex);
723 
724 static void lpss_iosf_enter_d3_state(void)
725 {
726         u32 value1 = 0;
727         u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK;
728         u32 value2 = LPSS_PMCSR_D3hot;
729         u32 mask2 = LPSS_PMCSR_Dx_MASK;
730         /*
731          * PMC provides an information about actual status of the LPSS devices.
732          * Here we read the values related to LPSS power island, i.e. LPSS
733          * devices, excluding both LPSS DMA controllers, along with SCC domain.
734          */
735         u32 func_dis, d3_sts_0, pmc_status, pmc_mask = 0xfe000ffe;
736         int ret;
737 
738         ret = pmc_atom_read(PMC_FUNC_DIS, &func_dis);
739         if (ret)
740                 return;
741 
742         mutex_lock(&lpss_iosf_mutex);
743 
744         ret = pmc_atom_read(PMC_D3_STS_0, &d3_sts_0);
745         if (ret)
746                 goto exit;
747 
748         /*
749          * Get the status of entire LPSS power island per device basis.
750          * Shutdown both LPSS DMA controllers if and only if all other devices
751          * are already in D3hot.
752          */
753         pmc_status = (~(d3_sts_0 | func_dis)) & pmc_mask;
754         if (pmc_status)
755                 goto exit;
756 
757         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
758                         LPSS_IOSF_PMCSR, value2, mask2);
759 
760         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
761                         LPSS_IOSF_PMCSR, value2, mask2);
762 
763         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
764                         LPSS_IOSF_GPIODEF0, value1, mask1);
765 exit:
766         mutex_unlock(&lpss_iosf_mutex);
767 }
768 
769 static void lpss_iosf_exit_d3_state(void)
770 {
771         u32 value1 = LPSS_GPIODEF0_DMA1_D3 | LPSS_GPIODEF0_DMA2_D3;
772         u32 mask1 = LPSS_GPIODEF0_DMA_D3_MASK;
773         u32 value2 = LPSS_PMCSR_D0;
774         u32 mask2 = LPSS_PMCSR_Dx_MASK;
775 
776         mutex_lock(&lpss_iosf_mutex);
777 
778         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIOEP, MBI_CR_WRITE,
779                         LPSS_IOSF_GPIODEF0, value1, mask1);
780 
781         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO2, MBI_CFG_WRITE,
782                         LPSS_IOSF_PMCSR, value2, mask2);
783 
784         iosf_mbi_modify(LPSS_IOSF_UNIT_LPIO1, MBI_CFG_WRITE,
785                         LPSS_IOSF_PMCSR, value2, mask2);
786 
787         mutex_unlock(&lpss_iosf_mutex);
788 }
789 
790 static int acpi_lpss_runtime_suspend(struct device *dev)
791 {
792         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
793         int ret;
794 
795         ret = pm_generic_runtime_suspend(dev);
796         if (ret)
797                 return ret;
798 
799         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
800                 acpi_lpss_save_ctx(dev, pdata);
801 
802         ret = acpi_dev_runtime_suspend(dev);
803 
804         /*
805          * This call must be last in the sequence, otherwise PMC will return
806          * wrong status for devices being about to be powered off. See
807          * lpss_iosf_enter_d3_state() for further information.
808          */
809         if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
810                 lpss_iosf_enter_d3_state();
811 
812         return ret;
813 }
814 
815 static int acpi_lpss_runtime_resume(struct device *dev)
816 {
817         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
818         int ret;
819 
820         /*
821          * This call is kept first to be in symmetry with
822          * acpi_lpss_runtime_suspend() one.
823          */
824         if (lpss_quirks & LPSS_QUIRK_ALWAYS_POWER_ON && iosf_mbi_available())
825                 lpss_iosf_exit_d3_state();
826 
827         ret = acpi_dev_runtime_resume(dev);
828         if (ret)
829                 return ret;
830 
831         acpi_lpss_d3_to_d0_delay(pdata);
832 
833         if (pdata->dev_desc->flags & LPSS_SAVE_CTX)
834                 acpi_lpss_restore_ctx(dev, pdata);
835 
836         return pm_generic_runtime_resume(dev);
837 }
838 #endif /* CONFIG_PM */
839 
840 static struct dev_pm_domain acpi_lpss_pm_domain = {
841 #ifdef CONFIG_PM
842         .activate = acpi_lpss_activate,
843         .dismiss = acpi_lpss_dismiss,
844 #endif
845         .ops = {
846 #ifdef CONFIG_PM
847 #ifdef CONFIG_PM_SLEEP
848                 .prepare = acpi_subsys_prepare,
849                 .complete = pm_complete_with_resume_check,
850                 .suspend = acpi_subsys_suspend,
851                 .suspend_late = acpi_lpss_suspend_late,
852                 .resume_early = acpi_lpss_resume_early,
853                 .freeze = acpi_subsys_freeze,
854                 .poweroff = acpi_subsys_suspend,
855                 .poweroff_late = acpi_lpss_suspend_late,
856                 .restore_early = acpi_lpss_resume_early,
857 #endif
858                 .runtime_suspend = acpi_lpss_runtime_suspend,
859                 .runtime_resume = acpi_lpss_runtime_resume,
860 #endif
861         },
862 };
863 
864 static int acpi_lpss_platform_notify(struct notifier_block *nb,
865                                      unsigned long action, void *data)
866 {
867         struct platform_device *pdev = to_platform_device(data);
868         struct lpss_private_data *pdata;
869         struct acpi_device *adev;
870         const struct acpi_device_id *id;
871 
872         id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
873         if (!id || !id->driver_data)
874                 return 0;
875 
876         if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
877                 return 0;
878 
879         pdata = acpi_driver_data(adev);
880         if (!pdata)
881                 return 0;
882 
883         if (pdata->mmio_base &&
884             pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
885                 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
886                 return 0;
887         }
888 
889         switch (action) {
890         case BUS_NOTIFY_BIND_DRIVER:
891                 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
892                 break;
893         case BUS_NOTIFY_DRIVER_NOT_BOUND:
894         case BUS_NOTIFY_UNBOUND_DRIVER:
895                 dev_pm_domain_set(&pdev->dev, NULL);
896                 break;
897         case BUS_NOTIFY_ADD_DEVICE:
898                 dev_pm_domain_set(&pdev->dev, &acpi_lpss_pm_domain);
899                 if (pdata->dev_desc->flags & LPSS_LTR)
900                         return sysfs_create_group(&pdev->dev.kobj,
901                                                   &lpss_attr_group);
902                 break;
903         case BUS_NOTIFY_DEL_DEVICE:
904                 if (pdata->dev_desc->flags & LPSS_LTR)
905                         sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
906                 dev_pm_domain_set(&pdev->dev, NULL);
907                 break;
908         default:
909                 break;
910         }
911 
912         return 0;
913 }
914 
915 static struct notifier_block acpi_lpss_nb = {
916         .notifier_call = acpi_lpss_platform_notify,
917 };
918 
919 static void acpi_lpss_bind(struct device *dev)
920 {
921         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
922 
923         if (!pdata || !pdata->mmio_base || !(pdata->dev_desc->flags & LPSS_LTR))
924                 return;
925 
926         if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
927                 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
928         else
929                 dev_err(dev, "MMIO size insufficient to access LTR\n");
930 }
931 
932 static void acpi_lpss_unbind(struct device *dev)
933 {
934         dev->power.set_latency_tolerance = NULL;
935 }
936 
937 static struct acpi_scan_handler lpss_handler = {
938         .ids = acpi_lpss_device_ids,
939         .attach = acpi_lpss_create_device,
940         .bind = acpi_lpss_bind,
941         .unbind = acpi_lpss_unbind,
942 };
943 
944 void __init acpi_lpss_init(void)
945 {
946         const struct x86_cpu_id *id;
947         int ret;
948 
949         ret = lpt_clk_init();
950         if (ret)
951                 return;
952 
953         id = x86_match_cpu(lpss_cpu_ids);
954         if (id)
955                 lpss_quirks |= LPSS_QUIRK_ALWAYS_POWER_ON;
956 
957         bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
958         acpi_scan_add_handler(&lpss_handler);
959 }
960 
961 #else
962 
963 static struct acpi_scan_handler lpss_handler = {
964         .ids = acpi_lpss_device_ids,
965 };
966 
967 void __init acpi_lpss_init(void)
968 {
969         acpi_scan_add_handler(&lpss_handler);
970 }
971 
972 #endif /* CONFIG_X86_INTEL_LPSS */
973 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us