Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/drivers/acpi/acpi_lpss.c

  1 /*
  2  * ACPI support for Intel Lynxpoint LPSS.
  3  *
  4  * Copyright (C) 2013, Intel Corporation
  5  * Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
  6  *          Rafael J. Wysocki <rafael.j.wysocki@intel.com>
  7  *
  8  * This program is free software; you can redistribute it and/or modify
  9  * it under the terms of the GNU General Public License version 2 as
 10  * published by the Free Software Foundation.
 11  */
 12 
 13 #include <linux/acpi.h>
 14 #include <linux/clk.h>
 15 #include <linux/clkdev.h>
 16 #include <linux/clk-provider.h>
 17 #include <linux/err.h>
 18 #include <linux/io.h>
 19 #include <linux/platform_device.h>
 20 #include <linux/platform_data/clk-lpss.h>
 21 #include <linux/pm_runtime.h>
 22 #include <linux/delay.h>
 23 
 24 #include "internal.h"
 25 
 26 ACPI_MODULE_NAME("acpi_lpss");
 27 
 28 #ifdef CONFIG_X86_INTEL_LPSS
 29 
 30 #define LPSS_ADDR(desc) ((unsigned long)&desc)
 31 
 32 #define LPSS_CLK_SIZE   0x04
 33 #define LPSS_LTR_SIZE   0x18
 34 
 35 /* Offsets relative to LPSS_PRIVATE_OFFSET */
 36 #define LPSS_CLK_DIVIDER_DEF_MASK       (BIT(1) | BIT(16))
 37 #define LPSS_RESETS                     0x04
 38 #define LPSS_RESETS_RESET_FUNC          BIT(0)
 39 #define LPSS_RESETS_RESET_APB           BIT(1)
 40 #define LPSS_GENERAL                    0x08
 41 #define LPSS_GENERAL_LTR_MODE_SW        BIT(2)
 42 #define LPSS_GENERAL_UART_RTS_OVRD      BIT(3)
 43 #define LPSS_SW_LTR                     0x10
 44 #define LPSS_AUTO_LTR                   0x14
 45 #define LPSS_LTR_SNOOP_REQ              BIT(15)
 46 #define LPSS_LTR_SNOOP_MASK             0x0000FFFF
 47 #define LPSS_LTR_SNOOP_LAT_1US          0x800
 48 #define LPSS_LTR_SNOOP_LAT_32US         0xC00
 49 #define LPSS_LTR_SNOOP_LAT_SHIFT        5
 50 #define LPSS_LTR_SNOOP_LAT_CUTOFF       3000
 51 #define LPSS_LTR_MAX_VAL                0x3FF
 52 #define LPSS_TX_INT                     0x20
 53 #define LPSS_TX_INT_MASK                BIT(1)
 54 
 55 #define LPSS_PRV_REG_COUNT              9
 56 
 57 struct lpss_shared_clock {
 58         const char *name;
 59         unsigned long rate;
 60         struct clk *clk;
 61 };
 62 
 63 struct lpss_private_data;
 64 
 65 struct lpss_device_desc {
 66         bool clk_required;
 67         const char *clkdev_name;
 68         bool ltr_required;
 69         unsigned int prv_offset;
 70         size_t prv_size_override;
 71         bool clk_divider;
 72         bool clk_gate;
 73         bool save_ctx;
 74         struct lpss_shared_clock *shared_clock;
 75         void (*setup)(struct lpss_private_data *pdata);
 76 };
 77 
 78 static struct lpss_device_desc lpss_dma_desc = {
 79         .clk_required = true,
 80         .clkdev_name = "hclk",
 81 };
 82 
 83 struct lpss_private_data {
 84         void __iomem *mmio_base;
 85         resource_size_t mmio_size;
 86         struct clk *clk;
 87         const struct lpss_device_desc *dev_desc;
 88         u32 prv_reg_ctx[LPSS_PRV_REG_COUNT];
 89 };
 90 
 91 static void lpss_uart_setup(struct lpss_private_data *pdata)
 92 {
 93         unsigned int offset;
 94         u32 reg;
 95 
 96         offset = pdata->dev_desc->prv_offset + LPSS_TX_INT;
 97         reg = readl(pdata->mmio_base + offset);
 98         writel(reg | LPSS_TX_INT_MASK, pdata->mmio_base + offset);
 99 
100         offset = pdata->dev_desc->prv_offset + LPSS_GENERAL;
101         reg = readl(pdata->mmio_base + offset);
102         writel(reg | LPSS_GENERAL_UART_RTS_OVRD, pdata->mmio_base + offset);
103 }
104 
105 static void lpss_i2c_setup(struct lpss_private_data *pdata)
106 {
107         unsigned int offset;
108         u32 val;
109 
110         offset = pdata->dev_desc->prv_offset + LPSS_RESETS;
111         val = readl(pdata->mmio_base + offset);
112         val |= LPSS_RESETS_RESET_APB | LPSS_RESETS_RESET_FUNC;
113         writel(val, pdata->mmio_base + offset);
114 }
115 
116 static struct lpss_device_desc wpt_dev_desc = {
117         .clk_required = true,
118         .prv_offset = 0x800,
119         .ltr_required = true,
120         .clk_divider = true,
121         .clk_gate = true,
122 };
123 
124 static struct lpss_device_desc lpt_dev_desc = {
125         .clk_required = true,
126         .prv_offset = 0x800,
127         .ltr_required = true,
128         .clk_divider = true,
129         .clk_gate = true,
130 };
131 
132 static struct lpss_device_desc lpt_i2c_dev_desc = {
133         .clk_required = true,
134         .prv_offset = 0x800,
135         .ltr_required = true,
136         .clk_gate = true,
137 };
138 
139 static struct lpss_device_desc lpt_uart_dev_desc = {
140         .clk_required = true,
141         .prv_offset = 0x800,
142         .ltr_required = true,
143         .clk_divider = true,
144         .clk_gate = true,
145         .setup = lpss_uart_setup,
146 };
147 
148 static struct lpss_device_desc lpt_sdio_dev_desc = {
149         .prv_offset = 0x1000,
150         .prv_size_override = 0x1018,
151         .ltr_required = true,
152 };
153 
154 static struct lpss_shared_clock pwm_clock = {
155         .name = "pwm_clk",
156         .rate = 25000000,
157 };
158 
159 static struct lpss_device_desc byt_pwm_dev_desc = {
160         .clk_required = true,
161         .save_ctx = true,
162         .shared_clock = &pwm_clock,
163 };
164 
165 static struct lpss_device_desc byt_uart_dev_desc = {
166         .clk_required = true,
167         .prv_offset = 0x800,
168         .clk_divider = true,
169         .clk_gate = true,
170         .save_ctx = true,
171         .setup = lpss_uart_setup,
172 };
173 
174 static struct lpss_device_desc byt_spi_dev_desc = {
175         .clk_required = true,
176         .prv_offset = 0x400,
177         .clk_divider = true,
178         .clk_gate = true,
179         .save_ctx = true,
180 };
181 
182 static struct lpss_device_desc byt_sdio_dev_desc = {
183         .clk_required = true,
184 };
185 
186 static struct lpss_shared_clock i2c_clock = {
187         .name = "i2c_clk",
188         .rate = 100000000,
189 };
190 
191 static struct lpss_device_desc byt_i2c_dev_desc = {
192         .clk_required = true,
193         .prv_offset = 0x800,
194         .save_ctx = true,
195         .shared_clock = &i2c_clock,
196         .setup = lpss_i2c_setup,
197 };
198 
199 static struct lpss_shared_clock bsw_pwm_clock = {
200         .name = "pwm_clk",
201         .rate = 19200000,
202 };
203 
204 static struct lpss_device_desc bsw_pwm_dev_desc = {
205         .clk_required = true,
206         .save_ctx = true,
207         .shared_clock = &bsw_pwm_clock,
208 };
209 
210 #else
211 
212 #define LPSS_ADDR(desc) (0UL)
213 
214 #endif /* CONFIG_X86_INTEL_LPSS */
215 
216 static const struct acpi_device_id acpi_lpss_device_ids[] = {
217         /* Generic LPSS devices */
218         { "INTL9C60", LPSS_ADDR(lpss_dma_desc) },
219 
220         /* Lynxpoint LPSS devices */
221         { "INT33C0", LPSS_ADDR(lpt_dev_desc) },
222         { "INT33C1", LPSS_ADDR(lpt_dev_desc) },
223         { "INT33C2", LPSS_ADDR(lpt_i2c_dev_desc) },
224         { "INT33C3", LPSS_ADDR(lpt_i2c_dev_desc) },
225         { "INT33C4", LPSS_ADDR(lpt_uart_dev_desc) },
226         { "INT33C5", LPSS_ADDR(lpt_uart_dev_desc) },
227         { "INT33C6", LPSS_ADDR(lpt_sdio_dev_desc) },
228         { "INT33C7", },
229 
230         /* BayTrail LPSS devices */
231         { "80860F09", LPSS_ADDR(byt_pwm_dev_desc) },
232         { "80860F0A", LPSS_ADDR(byt_uart_dev_desc) },
233         { "80860F0E", LPSS_ADDR(byt_spi_dev_desc) },
234         { "80860F14", LPSS_ADDR(byt_sdio_dev_desc) },
235         { "80860F41", LPSS_ADDR(byt_i2c_dev_desc) },
236         { "INT33B2", },
237         { "INT33FC", },
238 
239         /* Braswell LPSS devices */
240         { "80862288", LPSS_ADDR(bsw_pwm_dev_desc) },
241         { "8086228A", LPSS_ADDR(byt_uart_dev_desc) },
242         { "8086228E", LPSS_ADDR(byt_spi_dev_desc) },
243         { "808622C1", LPSS_ADDR(byt_i2c_dev_desc) },
244 
245         { "INT3430", LPSS_ADDR(lpt_dev_desc) },
246         { "INT3431", LPSS_ADDR(lpt_dev_desc) },
247         { "INT3432", LPSS_ADDR(lpt_i2c_dev_desc) },
248         { "INT3433", LPSS_ADDR(lpt_i2c_dev_desc) },
249         { "INT3434", LPSS_ADDR(lpt_uart_dev_desc) },
250         { "INT3435", LPSS_ADDR(lpt_uart_dev_desc) },
251         { "INT3436", LPSS_ADDR(lpt_sdio_dev_desc) },
252         { "INT3437", },
253 
254         { "INT3438", LPSS_ADDR(wpt_dev_desc) },
255 
256         { }
257 };
258 
259 #ifdef CONFIG_X86_INTEL_LPSS
260 
261 static int is_memory(struct acpi_resource *res, void *not_used)
262 {
263         struct resource r;
264         return !acpi_dev_resource_memory(res, &r);
265 }
266 
267 /* LPSS main clock device. */
268 static struct platform_device *lpss_clk_dev;
269 
270 static inline void lpt_register_clock_device(void)
271 {
272         lpss_clk_dev = platform_device_register_simple("clk-lpt", -1, NULL, 0);
273 }
274 
275 static int register_device_clock(struct acpi_device *adev,
276                                  struct lpss_private_data *pdata)
277 {
278         const struct lpss_device_desc *dev_desc = pdata->dev_desc;
279         struct lpss_shared_clock *shared_clock = dev_desc->shared_clock;
280         const char *devname = dev_name(&adev->dev);
281         struct clk *clk = ERR_PTR(-ENODEV);
282         struct lpss_clk_data *clk_data;
283         const char *parent, *clk_name;
284         void __iomem *prv_base;
285 
286         if (!lpss_clk_dev)
287                 lpt_register_clock_device();
288 
289         clk_data = platform_get_drvdata(lpss_clk_dev);
290         if (!clk_data)
291                 return -ENODEV;
292 
293         if (dev_desc->clkdev_name) {
294                 clk_register_clkdev(clk_data->clk, dev_desc->clkdev_name,
295                                     devname);
296                 return 0;
297         }
298 
299         if (!pdata->mmio_base
300             || pdata->mmio_size < dev_desc->prv_offset + LPSS_CLK_SIZE)
301                 return -ENODATA;
302 
303         parent = clk_data->name;
304         prv_base = pdata->mmio_base + dev_desc->prv_offset;
305 
306         if (shared_clock) {
307                 clk = shared_clock->clk;
308                 if (!clk) {
309                         clk = clk_register_fixed_rate(NULL, shared_clock->name,
310                                                       "lpss_clk", 0,
311                                                       shared_clock->rate);
312                         shared_clock->clk = clk;
313                 }
314                 parent = shared_clock->name;
315         }
316 
317         if (dev_desc->clk_gate) {
318                 clk = clk_register_gate(NULL, devname, parent, 0,
319                                         prv_base, 0, 0, NULL);
320                 parent = devname;
321         }
322 
323         if (dev_desc->clk_divider) {
324                 /* Prevent division by zero */
325                 if (!readl(prv_base))
326                         writel(LPSS_CLK_DIVIDER_DEF_MASK, prv_base);
327 
328                 clk_name = kasprintf(GFP_KERNEL, "%s-div", devname);
329                 if (!clk_name)
330                         return -ENOMEM;
331                 clk = clk_register_fractional_divider(NULL, clk_name, parent,
332                                                       0, prv_base,
333                                                       1, 15, 16, 15, 0, NULL);
334                 parent = clk_name;
335 
336                 clk_name = kasprintf(GFP_KERNEL, "%s-update", devname);
337                 if (!clk_name) {
338                         kfree(parent);
339                         return -ENOMEM;
340                 }
341                 clk = clk_register_gate(NULL, clk_name, parent,
342                                         CLK_SET_RATE_PARENT | CLK_SET_RATE_GATE,
343                                         prv_base, 31, 0, NULL);
344                 kfree(parent);
345                 kfree(clk_name);
346         }
347 
348         if (IS_ERR(clk))
349                 return PTR_ERR(clk);
350 
351         pdata->clk = clk;
352         clk_register_clkdev(clk, NULL, devname);
353         return 0;
354 }
355 
356 static int acpi_lpss_create_device(struct acpi_device *adev,
357                                    const struct acpi_device_id *id)
358 {
359         struct lpss_device_desc *dev_desc;
360         struct lpss_private_data *pdata;
361         struct resource_list_entry *rentry;
362         struct list_head resource_list;
363         struct platform_device *pdev;
364         int ret;
365 
366         dev_desc = (struct lpss_device_desc *)id->driver_data;
367         if (!dev_desc) {
368                 pdev = acpi_create_platform_device(adev);
369                 return IS_ERR_OR_NULL(pdev) ? PTR_ERR(pdev) : 1;
370         }
371         pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
372         if (!pdata)
373                 return -ENOMEM;
374 
375         INIT_LIST_HEAD(&resource_list);
376         ret = acpi_dev_get_resources(adev, &resource_list, is_memory, NULL);
377         if (ret < 0)
378                 goto err_out;
379 
380         list_for_each_entry(rentry, &resource_list, node)
381                 if (resource_type(&rentry->res) == IORESOURCE_MEM) {
382                         if (dev_desc->prv_size_override)
383                                 pdata->mmio_size = dev_desc->prv_size_override;
384                         else
385                                 pdata->mmio_size = resource_size(&rentry->res);
386                         pdata->mmio_base = ioremap(rentry->res.start,
387                                                    pdata->mmio_size);
388                         break;
389                 }
390 
391         acpi_dev_free_resource_list(&resource_list);
392 
393         pdata->dev_desc = dev_desc;
394 
395         if (dev_desc->clk_required) {
396                 ret = register_device_clock(adev, pdata);
397                 if (ret) {
398                         /* Skip the device, but continue the namespace scan. */
399                         ret = 0;
400                         goto err_out;
401                 }
402         }
403 
404         /*
405          * This works around a known issue in ACPI tables where LPSS devices
406          * have _PS0 and _PS3 without _PSC (and no power resources), so
407          * acpi_bus_init_power() will assume that the BIOS has put them into D0.
408          */
409         ret = acpi_device_fix_up_power(adev);
410         if (ret) {
411                 /* Skip the device, but continue the namespace scan. */
412                 ret = 0;
413                 goto err_out;
414         }
415 
416         if (dev_desc->setup)
417                 dev_desc->setup(pdata);
418 
419         adev->driver_data = pdata;
420         pdev = acpi_create_platform_device(adev);
421         if (!IS_ERR_OR_NULL(pdev)) {
422                 return 1;
423         }
424 
425         ret = PTR_ERR(pdev);
426         adev->driver_data = NULL;
427 
428  err_out:
429         kfree(pdata);
430         return ret;
431 }
432 
433 static u32 __lpss_reg_read(struct lpss_private_data *pdata, unsigned int reg)
434 {
435         return readl(pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
436 }
437 
438 static void __lpss_reg_write(u32 val, struct lpss_private_data *pdata,
439                              unsigned int reg)
440 {
441         writel(val, pdata->mmio_base + pdata->dev_desc->prv_offset + reg);
442 }
443 
444 static int lpss_reg_read(struct device *dev, unsigned int reg, u32 *val)
445 {
446         struct acpi_device *adev;
447         struct lpss_private_data *pdata;
448         unsigned long flags;
449         int ret;
450 
451         ret = acpi_bus_get_device(ACPI_HANDLE(dev), &adev);
452         if (WARN_ON(ret))
453                 return ret;
454 
455         spin_lock_irqsave(&dev->power.lock, flags);
456         if (pm_runtime_suspended(dev)) {
457                 ret = -EAGAIN;
458                 goto out;
459         }
460         pdata = acpi_driver_data(adev);
461         if (WARN_ON(!pdata || !pdata->mmio_base)) {
462                 ret = -ENODEV;
463                 goto out;
464         }
465         *val = __lpss_reg_read(pdata, reg);
466 
467  out:
468         spin_unlock_irqrestore(&dev->power.lock, flags);
469         return ret;
470 }
471 
472 static ssize_t lpss_ltr_show(struct device *dev, struct device_attribute *attr,
473                              char *buf)
474 {
475         u32 ltr_value = 0;
476         unsigned int reg;
477         int ret;
478 
479         reg = strcmp(attr->attr.name, "auto_ltr") ? LPSS_SW_LTR : LPSS_AUTO_LTR;
480         ret = lpss_reg_read(dev, reg, &ltr_value);
481         if (ret)
482                 return ret;
483 
484         return snprintf(buf, PAGE_SIZE, "%08x\n", ltr_value);
485 }
486 
487 static ssize_t lpss_ltr_mode_show(struct device *dev,
488                                   struct device_attribute *attr, char *buf)
489 {
490         u32 ltr_mode = 0;
491         char *outstr;
492         int ret;
493 
494         ret = lpss_reg_read(dev, LPSS_GENERAL, &ltr_mode);
495         if (ret)
496                 return ret;
497 
498         outstr = (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) ? "sw" : "auto";
499         return sprintf(buf, "%s\n", outstr);
500 }
501 
502 static DEVICE_ATTR(auto_ltr, S_IRUSR, lpss_ltr_show, NULL);
503 static DEVICE_ATTR(sw_ltr, S_IRUSR, lpss_ltr_show, NULL);
504 static DEVICE_ATTR(ltr_mode, S_IRUSR, lpss_ltr_mode_show, NULL);
505 
506 static struct attribute *lpss_attrs[] = {
507         &dev_attr_auto_ltr.attr,
508         &dev_attr_sw_ltr.attr,
509         &dev_attr_ltr_mode.attr,
510         NULL,
511 };
512 
513 static struct attribute_group lpss_attr_group = {
514         .attrs = lpss_attrs,
515         .name = "lpss_ltr",
516 };
517 
518 static void acpi_lpss_set_ltr(struct device *dev, s32 val)
519 {
520         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
521         u32 ltr_mode, ltr_val;
522 
523         ltr_mode = __lpss_reg_read(pdata, LPSS_GENERAL);
524         if (val < 0) {
525                 if (ltr_mode & LPSS_GENERAL_LTR_MODE_SW) {
526                         ltr_mode &= ~LPSS_GENERAL_LTR_MODE_SW;
527                         __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
528                 }
529                 return;
530         }
531         ltr_val = __lpss_reg_read(pdata, LPSS_SW_LTR) & ~LPSS_LTR_SNOOP_MASK;
532         if (val >= LPSS_LTR_SNOOP_LAT_CUTOFF) {
533                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US;
534                 val = LPSS_LTR_MAX_VAL;
535         } else if (val > LPSS_LTR_MAX_VAL) {
536                 ltr_val |= LPSS_LTR_SNOOP_LAT_32US | LPSS_LTR_SNOOP_REQ;
537                 val >>= LPSS_LTR_SNOOP_LAT_SHIFT;
538         } else {
539                 ltr_val |= LPSS_LTR_SNOOP_LAT_1US | LPSS_LTR_SNOOP_REQ;
540         }
541         ltr_val |= val;
542         __lpss_reg_write(ltr_val, pdata, LPSS_SW_LTR);
543         if (!(ltr_mode & LPSS_GENERAL_LTR_MODE_SW)) {
544                 ltr_mode |= LPSS_GENERAL_LTR_MODE_SW;
545                 __lpss_reg_write(ltr_mode, pdata, LPSS_GENERAL);
546         }
547 }
548 
549 #ifdef CONFIG_PM
550 /**
551  * acpi_lpss_save_ctx() - Save the private registers of LPSS device
552  * @dev: LPSS device
553  *
554  * Most LPSS devices have private registers which may loose their context when
555  * the device is powered down. acpi_lpss_save_ctx() saves those registers into
556  * prv_reg_ctx array.
557  */
558 static void acpi_lpss_save_ctx(struct device *dev)
559 {
560         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
561         unsigned int i;
562 
563         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
564                 unsigned long offset = i * sizeof(u32);
565 
566                 pdata->prv_reg_ctx[i] = __lpss_reg_read(pdata, offset);
567                 dev_dbg(dev, "saving 0x%08x from LPSS reg at offset 0x%02lx\n",
568                         pdata->prv_reg_ctx[i], offset);
569         }
570 }
571 
572 /**
573  * acpi_lpss_restore_ctx() - Restore the private registers of LPSS device
574  * @dev: LPSS device
575  *
576  * Restores the registers that were previously stored with acpi_lpss_save_ctx().
577  */
578 static void acpi_lpss_restore_ctx(struct device *dev)
579 {
580         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
581         unsigned int i;
582 
583         /*
584          * The following delay is needed or the subsequent write operations may
585          * fail. The LPSS devices are actually PCI devices and the PCI spec
586          * expects 10ms delay before the device can be accessed after D3 to D0
587          * transition.
588          */
589         msleep(10);
590 
591         for (i = 0; i < LPSS_PRV_REG_COUNT; i++) {
592                 unsigned long offset = i * sizeof(u32);
593 
594                 __lpss_reg_write(pdata->prv_reg_ctx[i], pdata, offset);
595                 dev_dbg(dev, "restoring 0x%08x to LPSS reg at offset 0x%02lx\n",
596                         pdata->prv_reg_ctx[i], offset);
597         }
598 }
599 
600 #ifdef CONFIG_PM_SLEEP
601 static int acpi_lpss_suspend_late(struct device *dev)
602 {
603         int ret = pm_generic_suspend_late(dev);
604 
605         if (ret)
606                 return ret;
607 
608         acpi_lpss_save_ctx(dev);
609         return acpi_dev_suspend_late(dev);
610 }
611 
612 static int acpi_lpss_resume_early(struct device *dev)
613 {
614         int ret = acpi_dev_resume_early(dev);
615 
616         if (ret)
617                 return ret;
618 
619         acpi_lpss_restore_ctx(dev);
620         return pm_generic_resume_early(dev);
621 }
622 #endif /* CONFIG_PM_SLEEP */
623 
624 #ifdef CONFIG_PM_RUNTIME
625 static int acpi_lpss_runtime_suspend(struct device *dev)
626 {
627         int ret = pm_generic_runtime_suspend(dev);
628 
629         if (ret)
630                 return ret;
631 
632         acpi_lpss_save_ctx(dev);
633         return acpi_dev_runtime_suspend(dev);
634 }
635 
636 static int acpi_lpss_runtime_resume(struct device *dev)
637 {
638         int ret = acpi_dev_runtime_resume(dev);
639 
640         if (ret)
641                 return ret;
642 
643         acpi_lpss_restore_ctx(dev);
644         return pm_generic_runtime_resume(dev);
645 }
646 #endif /* CONFIG_PM_RUNTIME */
647 #endif /* CONFIG_PM */
648 
649 static struct dev_pm_domain acpi_lpss_pm_domain = {
650         .ops = {
651 #ifdef CONFIG_PM_SLEEP
652                 .prepare = acpi_subsys_prepare,
653                 .complete = acpi_subsys_complete,
654                 .suspend = acpi_subsys_suspend,
655                 .suspend_late = acpi_lpss_suspend_late,
656                 .resume_early = acpi_lpss_resume_early,
657                 .freeze = acpi_subsys_freeze,
658                 .poweroff = acpi_subsys_suspend,
659                 .poweroff_late = acpi_lpss_suspend_late,
660                 .restore_early = acpi_lpss_resume_early,
661 #endif
662 #ifdef CONFIG_PM_RUNTIME
663                 .runtime_suspend = acpi_lpss_runtime_suspend,
664                 .runtime_resume = acpi_lpss_runtime_resume,
665 #endif
666         },
667 };
668 
669 static int acpi_lpss_platform_notify(struct notifier_block *nb,
670                                      unsigned long action, void *data)
671 {
672         struct platform_device *pdev = to_platform_device(data);
673         struct lpss_private_data *pdata;
674         struct acpi_device *adev;
675         const struct acpi_device_id *id;
676 
677         id = acpi_match_device(acpi_lpss_device_ids, &pdev->dev);
678         if (!id || !id->driver_data)
679                 return 0;
680 
681         if (acpi_bus_get_device(ACPI_HANDLE(&pdev->dev), &adev))
682                 return 0;
683 
684         pdata = acpi_driver_data(adev);
685         if (!pdata || !pdata->mmio_base)
686                 return 0;
687 
688         if (pdata->mmio_size < pdata->dev_desc->prv_offset + LPSS_LTR_SIZE) {
689                 dev_err(&pdev->dev, "MMIO size insufficient to access LTR\n");
690                 return 0;
691         }
692 
693         switch (action) {
694         case BUS_NOTIFY_BOUND_DRIVER:
695                 if (pdata->dev_desc->save_ctx)
696                         pdev->dev.pm_domain = &acpi_lpss_pm_domain;
697                 break;
698         case BUS_NOTIFY_UNBOUND_DRIVER:
699                 if (pdata->dev_desc->save_ctx)
700                         pdev->dev.pm_domain = NULL;
701                 break;
702         case BUS_NOTIFY_ADD_DEVICE:
703                 if (pdata->dev_desc->ltr_required)
704                         return sysfs_create_group(&pdev->dev.kobj,
705                                                   &lpss_attr_group);
706         case BUS_NOTIFY_DEL_DEVICE:
707                 if (pdata->dev_desc->ltr_required)
708                         sysfs_remove_group(&pdev->dev.kobj, &lpss_attr_group);
709         default:
710                 break;
711         }
712 
713         return 0;
714 }
715 
716 static struct notifier_block acpi_lpss_nb = {
717         .notifier_call = acpi_lpss_platform_notify,
718 };
719 
720 static void acpi_lpss_bind(struct device *dev)
721 {
722         struct lpss_private_data *pdata = acpi_driver_data(ACPI_COMPANION(dev));
723 
724         if (!pdata || !pdata->mmio_base || !pdata->dev_desc->ltr_required)
725                 return;
726 
727         if (pdata->mmio_size >= pdata->dev_desc->prv_offset + LPSS_LTR_SIZE)
728                 dev->power.set_latency_tolerance = acpi_lpss_set_ltr;
729         else
730                 dev_err(dev, "MMIO size insufficient to access LTR\n");
731 }
732 
733 static void acpi_lpss_unbind(struct device *dev)
734 {
735         dev->power.set_latency_tolerance = NULL;
736 }
737 
738 static struct acpi_scan_handler lpss_handler = {
739         .ids = acpi_lpss_device_ids,
740         .attach = acpi_lpss_create_device,
741         .bind = acpi_lpss_bind,
742         .unbind = acpi_lpss_unbind,
743 };
744 
745 void __init acpi_lpss_init(void)
746 {
747         if (!lpt_clk_init()) {
748                 bus_register_notifier(&platform_bus_type, &acpi_lpss_nb);
749                 acpi_scan_add_handler(&lpss_handler);
750         }
751 }
752 
753 #else
754 
755 static struct acpi_scan_handler lpss_handler = {
756         .ids = acpi_lpss_device_ids,
757 };
758 
759 void __init acpi_lpss_init(void)
760 {
761         acpi_scan_add_handler(&lpss_handler);
762 }
763 
764 #endif /* CONFIG_X86_INTEL_LPSS */
765 

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