Version:  2.0.40 2.2.26 2.4.37 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2

Linux/arch/x86/kernel/cpu/common.c

  1 #include <linux/bootmem.h>
  2 #include <linux/linkage.h>
  3 #include <linux/bitops.h>
  4 #include <linux/kernel.h>
  5 #include <linux/module.h>
  6 #include <linux/percpu.h>
  7 #include <linux/string.h>
  8 #include <linux/ctype.h>
  9 #include <linux/delay.h>
 10 #include <linux/sched.h>
 11 #include <linux/init.h>
 12 #include <linux/kprobes.h>
 13 #include <linux/kgdb.h>
 14 #include <linux/smp.h>
 15 #include <linux/io.h>
 16 
 17 #include <asm/stackprotector.h>
 18 #include <asm/perf_event.h>
 19 #include <asm/mmu_context.h>
 20 #include <asm/archrandom.h>
 21 #include <asm/hypervisor.h>
 22 #include <asm/processor.h>
 23 #include <asm/tlbflush.h>
 24 #include <asm/debugreg.h>
 25 #include <asm/sections.h>
 26 #include <asm/vsyscall.h>
 27 #include <linux/topology.h>
 28 #include <linux/cpumask.h>
 29 #include <asm/pgtable.h>
 30 #include <linux/atomic.h>
 31 #include <asm/proto.h>
 32 #include <asm/setup.h>
 33 #include <asm/apic.h>
 34 #include <asm/desc.h>
 35 #include <asm/fpu/internal.h>
 36 #include <asm/mtrr.h>
 37 #include <linux/numa.h>
 38 #include <asm/asm.h>
 39 #include <asm/cpu.h>
 40 #include <asm/mce.h>
 41 #include <asm/msr.h>
 42 #include <asm/pat.h>
 43 #include <asm/microcode.h>
 44 #include <asm/microcode_intel.h>
 45 
 46 #ifdef CONFIG_X86_LOCAL_APIC
 47 #include <asm/uv/uv.h>
 48 #endif
 49 
 50 #include "cpu.h"
 51 
 52 /* all of these masks are initialized in setup_cpu_local_masks() */
 53 cpumask_var_t cpu_initialized_mask;
 54 cpumask_var_t cpu_callout_mask;
 55 cpumask_var_t cpu_callin_mask;
 56 
 57 /* representing cpus for which sibling maps can be computed */
 58 cpumask_var_t cpu_sibling_setup_mask;
 59 
 60 /* correctly size the local cpu masks */
 61 void __init setup_cpu_local_masks(void)
 62 {
 63         alloc_bootmem_cpumask_var(&cpu_initialized_mask);
 64         alloc_bootmem_cpumask_var(&cpu_callin_mask);
 65         alloc_bootmem_cpumask_var(&cpu_callout_mask);
 66         alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
 67 }
 68 
 69 static void default_init(struct cpuinfo_x86 *c)
 70 {
 71 #ifdef CONFIG_X86_64
 72         cpu_detect_cache_sizes(c);
 73 #else
 74         /* Not much we can do here... */
 75         /* Check if at least it has cpuid */
 76         if (c->cpuid_level == -1) {
 77                 /* No cpuid. It must be an ancient CPU */
 78                 if (c->x86 == 4)
 79                         strcpy(c->x86_model_id, "486");
 80                 else if (c->x86 == 3)
 81                         strcpy(c->x86_model_id, "386");
 82         }
 83 #endif
 84 }
 85 
 86 static const struct cpu_dev default_cpu = {
 87         .c_init         = default_init,
 88         .c_vendor       = "Unknown",
 89         .c_x86_vendor   = X86_VENDOR_UNKNOWN,
 90 };
 91 
 92 static const struct cpu_dev *this_cpu = &default_cpu;
 93 
 94 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
 95 #ifdef CONFIG_X86_64
 96         /*
 97          * We need valid kernel segments for data and code in long mode too
 98          * IRET will check the segment types  kkeil 2000/10/28
 99          * Also sysret mandates a special GDT layout
100          *
101          * TLS descriptors are currently at a different place compared to i386.
102          * Hopefully nobody expects them at a fixed place (Wine?)
103          */
104         [GDT_ENTRY_KERNEL32_CS]         = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
105         [GDT_ENTRY_KERNEL_CS]           = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
106         [GDT_ENTRY_KERNEL_DS]           = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
107         [GDT_ENTRY_DEFAULT_USER32_CS]   = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
108         [GDT_ENTRY_DEFAULT_USER_DS]     = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
109         [GDT_ENTRY_DEFAULT_USER_CS]     = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
110 #else
111         [GDT_ENTRY_KERNEL_CS]           = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
112         [GDT_ENTRY_KERNEL_DS]           = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
113         [GDT_ENTRY_DEFAULT_USER_CS]     = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
114         [GDT_ENTRY_DEFAULT_USER_DS]     = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
115         /*
116          * Segments used for calling PnP BIOS have byte granularity.
117          * They code segments and data segments have fixed 64k limits,
118          * the transfer segment sizes are set at run time.
119          */
120         /* 32-bit code */
121         [GDT_ENTRY_PNPBIOS_CS32]        = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
122         /* 16-bit code */
123         [GDT_ENTRY_PNPBIOS_CS16]        = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
124         /* 16-bit data */
125         [GDT_ENTRY_PNPBIOS_DS]          = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
126         /* 16-bit data */
127         [GDT_ENTRY_PNPBIOS_TS1]         = GDT_ENTRY_INIT(0x0092, 0, 0),
128         /* 16-bit data */
129         [GDT_ENTRY_PNPBIOS_TS2]         = GDT_ENTRY_INIT(0x0092, 0, 0),
130         /*
131          * The APM segments have byte granularity and their bases
132          * are set at run time.  All have 64k limits.
133          */
134         /* 32-bit code */
135         [GDT_ENTRY_APMBIOS_BASE]        = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
136         /* 16-bit code */
137         [GDT_ENTRY_APMBIOS_BASE+1]      = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
138         /* data */
139         [GDT_ENTRY_APMBIOS_BASE+2]      = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
140 
141         [GDT_ENTRY_ESPFIX_SS]           = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
142         [GDT_ENTRY_PERCPU]              = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
143         GDT_STACK_CANARY_INIT
144 #endif
145 } };
146 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
147 
148 static int __init x86_mpx_setup(char *s)
149 {
150         /* require an exact match without trailing characters */
151         if (strlen(s))
152                 return 0;
153 
154         /* do not emit a message if the feature is not present */
155         if (!boot_cpu_has(X86_FEATURE_MPX))
156                 return 1;
157 
158         setup_clear_cpu_cap(X86_FEATURE_MPX);
159         pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
160         return 1;
161 }
162 __setup("nompx", x86_mpx_setup);
163 
164 #ifdef CONFIG_X86_32
165 static int cachesize_override = -1;
166 static int disable_x86_serial_nr = 1;
167 
168 static int __init cachesize_setup(char *str)
169 {
170         get_option(&str, &cachesize_override);
171         return 1;
172 }
173 __setup("cachesize=", cachesize_setup);
174 
175 static int __init x86_sep_setup(char *s)
176 {
177         setup_clear_cpu_cap(X86_FEATURE_SEP);
178         return 1;
179 }
180 __setup("nosep", x86_sep_setup);
181 
182 /* Standard macro to see if a specific flag is changeable */
183 static inline int flag_is_changeable_p(u32 flag)
184 {
185         u32 f1, f2;
186 
187         /*
188          * Cyrix and IDT cpus allow disabling of CPUID
189          * so the code below may return different results
190          * when it is executed before and after enabling
191          * the CPUID. Add "volatile" to not allow gcc to
192          * optimize the subsequent calls to this function.
193          */
194         asm volatile ("pushfl           \n\t"
195                       "pushfl           \n\t"
196                       "popl %0          \n\t"
197                       "movl %0, %1      \n\t"
198                       "xorl %2, %0      \n\t"
199                       "pushl %0         \n\t"
200                       "popfl            \n\t"
201                       "pushfl           \n\t"
202                       "popl %0          \n\t"
203                       "popfl            \n\t"
204 
205                       : "=&r" (f1), "=&r" (f2)
206                       : "ir" (flag));
207 
208         return ((f1^f2) & flag) != 0;
209 }
210 
211 /* Probe for the CPUID instruction */
212 int have_cpuid_p(void)
213 {
214         return flag_is_changeable_p(X86_EFLAGS_ID);
215 }
216 
217 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
218 {
219         unsigned long lo, hi;
220 
221         if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
222                 return;
223 
224         /* Disable processor serial number: */
225 
226         rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
227         lo |= 0x200000;
228         wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
229 
230         printk(KERN_NOTICE "CPU serial number disabled.\n");
231         clear_cpu_cap(c, X86_FEATURE_PN);
232 
233         /* Disabling the serial number may affect the cpuid level */
234         c->cpuid_level = cpuid_eax(0);
235 }
236 
237 static int __init x86_serial_nr_setup(char *s)
238 {
239         disable_x86_serial_nr = 0;
240         return 1;
241 }
242 __setup("serialnumber", x86_serial_nr_setup);
243 #else
244 static inline int flag_is_changeable_p(u32 flag)
245 {
246         return 1;
247 }
248 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
249 {
250 }
251 #endif
252 
253 static __init int setup_disable_smep(char *arg)
254 {
255         setup_clear_cpu_cap(X86_FEATURE_SMEP);
256         return 1;
257 }
258 __setup("nosmep", setup_disable_smep);
259 
260 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
261 {
262         if (cpu_has(c, X86_FEATURE_SMEP))
263                 cr4_set_bits(X86_CR4_SMEP);
264 }
265 
266 static __init int setup_disable_smap(char *arg)
267 {
268         setup_clear_cpu_cap(X86_FEATURE_SMAP);
269         return 1;
270 }
271 __setup("nosmap", setup_disable_smap);
272 
273 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
274 {
275         unsigned long eflags;
276 
277         /* This should have been cleared long ago */
278         raw_local_save_flags(eflags);
279         BUG_ON(eflags & X86_EFLAGS_AC);
280 
281         if (cpu_has(c, X86_FEATURE_SMAP)) {
282 #ifdef CONFIG_X86_SMAP
283                 cr4_set_bits(X86_CR4_SMAP);
284 #else
285                 cr4_clear_bits(X86_CR4_SMAP);
286 #endif
287         }
288 }
289 
290 /*
291  * Some CPU features depend on higher CPUID levels, which may not always
292  * be available due to CPUID level capping or broken virtualization
293  * software.  Add those features to this table to auto-disable them.
294  */
295 struct cpuid_dependent_feature {
296         u32 feature;
297         u32 level;
298 };
299 
300 static const struct cpuid_dependent_feature
301 cpuid_dependent_features[] = {
302         { X86_FEATURE_MWAIT,            0x00000005 },
303         { X86_FEATURE_DCA,              0x00000009 },
304         { X86_FEATURE_XSAVE,            0x0000000d },
305         { 0, 0 }
306 };
307 
308 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
309 {
310         const struct cpuid_dependent_feature *df;
311 
312         for (df = cpuid_dependent_features; df->feature; df++) {
313 
314                 if (!cpu_has(c, df->feature))
315                         continue;
316                 /*
317                  * Note: cpuid_level is set to -1 if unavailable, but
318                  * extended_extended_level is set to 0 if unavailable
319                  * and the legitimate extended levels are all negative
320                  * when signed; hence the weird messing around with
321                  * signs here...
322                  */
323                 if (!((s32)df->level < 0 ?
324                      (u32)df->level > (u32)c->extended_cpuid_level :
325                      (s32)df->level > (s32)c->cpuid_level))
326                         continue;
327 
328                 clear_cpu_cap(c, df->feature);
329                 if (!warn)
330                         continue;
331 
332                 printk(KERN_WARNING
333                        "CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
334                                 x86_cap_flag(df->feature), df->level);
335         }
336 }
337 
338 /*
339  * Naming convention should be: <Name> [(<Codename>)]
340  * This table only is used unless init_<vendor>() below doesn't set it;
341  * in particular, if CPUID levels 0x80000002..4 are supported, this
342  * isn't used
343  */
344 
345 /* Look up CPU names by table lookup. */
346 static const char *table_lookup_model(struct cpuinfo_x86 *c)
347 {
348 #ifdef CONFIG_X86_32
349         const struct legacy_cpu_model_info *info;
350 
351         if (c->x86_model >= 16)
352                 return NULL;    /* Range check */
353 
354         if (!this_cpu)
355                 return NULL;
356 
357         info = this_cpu->legacy_models;
358 
359         while (info->family) {
360                 if (info->family == c->x86)
361                         return info->model_names[c->x86_model];
362                 info++;
363         }
364 #endif
365         return NULL;            /* Not found */
366 }
367 
368 __u32 cpu_caps_cleared[NCAPINTS];
369 __u32 cpu_caps_set[NCAPINTS];
370 
371 void load_percpu_segment(int cpu)
372 {
373 #ifdef CONFIG_X86_32
374         loadsegment(fs, __KERNEL_PERCPU);
375 #else
376         loadsegment(gs, 0);
377         wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
378 #endif
379         load_stack_canary_segment();
380 }
381 
382 /*
383  * Current gdt points %fs at the "master" per-cpu area: after this,
384  * it's on the real one.
385  */
386 void switch_to_new_gdt(int cpu)
387 {
388         struct desc_ptr gdt_descr;
389 
390         gdt_descr.address = (long)get_cpu_gdt_table(cpu);
391         gdt_descr.size = GDT_SIZE - 1;
392         load_gdt(&gdt_descr);
393         /* Reload the per-cpu base */
394 
395         load_percpu_segment(cpu);
396 }
397 
398 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
399 
400 static void get_model_name(struct cpuinfo_x86 *c)
401 {
402         unsigned int *v;
403         char *p, *q, *s;
404 
405         if (c->extended_cpuid_level < 0x80000004)
406                 return;
407 
408         v = (unsigned int *)c->x86_model_id;
409         cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
410         cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
411         cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
412         c->x86_model_id[48] = 0;
413 
414         /* Trim whitespace */
415         p = q = s = &c->x86_model_id[0];
416 
417         while (*p == ' ')
418                 p++;
419 
420         while (*p) {
421                 /* Note the last non-whitespace index */
422                 if (!isspace(*p))
423                         s = q;
424 
425                 *q++ = *p++;
426         }
427 
428         *(s + 1) = '\0';
429 }
430 
431 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
432 {
433         unsigned int n, dummy, ebx, ecx, edx, l2size;
434 
435         n = c->extended_cpuid_level;
436 
437         if (n >= 0x80000005) {
438                 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
439                 c->x86_cache_size = (ecx>>24) + (edx>>24);
440 #ifdef CONFIG_X86_64
441                 /* On K8 L1 TLB is inclusive, so don't count it */
442                 c->x86_tlbsize = 0;
443 #endif
444         }
445 
446         if (n < 0x80000006)     /* Some chips just has a large L1. */
447                 return;
448 
449         cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
450         l2size = ecx >> 16;
451 
452 #ifdef CONFIG_X86_64
453         c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
454 #else
455         /* do processor-specific cache resizing */
456         if (this_cpu->legacy_cache_size)
457                 l2size = this_cpu->legacy_cache_size(c, l2size);
458 
459         /* Allow user to override all this if necessary. */
460         if (cachesize_override != -1)
461                 l2size = cachesize_override;
462 
463         if (l2size == 0)
464                 return;         /* Again, no L2 cache is possible */
465 #endif
466 
467         c->x86_cache_size = l2size;
468 }
469 
470 u16 __read_mostly tlb_lli_4k[NR_INFO];
471 u16 __read_mostly tlb_lli_2m[NR_INFO];
472 u16 __read_mostly tlb_lli_4m[NR_INFO];
473 u16 __read_mostly tlb_lld_4k[NR_INFO];
474 u16 __read_mostly tlb_lld_2m[NR_INFO];
475 u16 __read_mostly tlb_lld_4m[NR_INFO];
476 u16 __read_mostly tlb_lld_1g[NR_INFO];
477 
478 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
479 {
480         if (this_cpu->c_detect_tlb)
481                 this_cpu->c_detect_tlb(c);
482 
483         pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
484                 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
485                 tlb_lli_4m[ENTRIES]);
486 
487         pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
488                 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
489                 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
490 }
491 
492 void detect_ht(struct cpuinfo_x86 *c)
493 {
494 #ifdef CONFIG_SMP
495         u32 eax, ebx, ecx, edx;
496         int index_msb, core_bits;
497         static bool printed;
498 
499         if (!cpu_has(c, X86_FEATURE_HT))
500                 return;
501 
502         if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
503                 goto out;
504 
505         if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
506                 return;
507 
508         cpuid(1, &eax, &ebx, &ecx, &edx);
509 
510         smp_num_siblings = (ebx & 0xff0000) >> 16;
511 
512         if (smp_num_siblings == 1) {
513                 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
514                 goto out;
515         }
516 
517         if (smp_num_siblings <= 1)
518                 goto out;
519 
520         index_msb = get_count_order(smp_num_siblings);
521         c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
522 
523         smp_num_siblings = smp_num_siblings / c->x86_max_cores;
524 
525         index_msb = get_count_order(smp_num_siblings);
526 
527         core_bits = get_count_order(c->x86_max_cores);
528 
529         c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
530                                        ((1 << core_bits) - 1);
531 
532 out:
533         if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
534                 printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
535                        c->phys_proc_id);
536                 printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
537                        c->cpu_core_id);
538                 printed = 1;
539         }
540 #endif
541 }
542 
543 static void get_cpu_vendor(struct cpuinfo_x86 *c)
544 {
545         char *v = c->x86_vendor_id;
546         int i;
547 
548         for (i = 0; i < X86_VENDOR_NUM; i++) {
549                 if (!cpu_devs[i])
550                         break;
551 
552                 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
553                     (cpu_devs[i]->c_ident[1] &&
554                      !strcmp(v, cpu_devs[i]->c_ident[1]))) {
555 
556                         this_cpu = cpu_devs[i];
557                         c->x86_vendor = this_cpu->c_x86_vendor;
558                         return;
559                 }
560         }
561 
562         printk_once(KERN_ERR
563                         "CPU: vendor_id '%s' unknown, using generic init.\n" \
564                         "CPU: Your system may be unstable.\n", v);
565 
566         c->x86_vendor = X86_VENDOR_UNKNOWN;
567         this_cpu = &default_cpu;
568 }
569 
570 void cpu_detect(struct cpuinfo_x86 *c)
571 {
572         /* Get vendor name */
573         cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
574               (unsigned int *)&c->x86_vendor_id[0],
575               (unsigned int *)&c->x86_vendor_id[8],
576               (unsigned int *)&c->x86_vendor_id[4]);
577 
578         c->x86 = 4;
579         /* Intel-defined flags: level 0x00000001 */
580         if (c->cpuid_level >= 0x00000001) {
581                 u32 junk, tfms, cap0, misc;
582 
583                 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
584                 c->x86 = (tfms >> 8) & 0xf;
585                 c->x86_model = (tfms >> 4) & 0xf;
586                 c->x86_mask = tfms & 0xf;
587 
588                 if (c->x86 == 0xf)
589                         c->x86 += (tfms >> 20) & 0xff;
590                 if (c->x86 >= 0x6)
591                         c->x86_model += ((tfms >> 16) & 0xf) << 4;
592 
593                 if (cap0 & (1<<19)) {
594                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
595                         c->x86_cache_alignment = c->x86_clflush_size;
596                 }
597         }
598 }
599 
600 void get_cpu_cap(struct cpuinfo_x86 *c)
601 {
602         u32 tfms, xlvl;
603         u32 ebx;
604 
605         /* Intel-defined flags: level 0x00000001 */
606         if (c->cpuid_level >= 0x00000001) {
607                 u32 capability, excap;
608 
609                 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
610                 c->x86_capability[0] = capability;
611                 c->x86_capability[4] = excap;
612         }
613 
614         /* Additional Intel-defined flags: level 0x00000007 */
615         if (c->cpuid_level >= 0x00000007) {
616                 u32 eax, ebx, ecx, edx;
617 
618                 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
619 
620                 c->x86_capability[9] = ebx;
621         }
622 
623         /* Extended state features: level 0x0000000d */
624         if (c->cpuid_level >= 0x0000000d) {
625                 u32 eax, ebx, ecx, edx;
626 
627                 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
628 
629                 c->x86_capability[10] = eax;
630         }
631 
632         /* Additional Intel-defined flags: level 0x0000000F */
633         if (c->cpuid_level >= 0x0000000F) {
634                 u32 eax, ebx, ecx, edx;
635 
636                 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
637                 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
638                 c->x86_capability[11] = edx;
639                 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
640                         /* will be overridden if occupancy monitoring exists */
641                         c->x86_cache_max_rmid = ebx;
642 
643                         /* QoS sub-leaf, EAX=0Fh, ECX=1 */
644                         cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
645                         c->x86_capability[12] = edx;
646                         if (cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) {
647                                 c->x86_cache_max_rmid = ecx;
648                                 c->x86_cache_occ_scale = ebx;
649                         }
650                 } else {
651                         c->x86_cache_max_rmid = -1;
652                         c->x86_cache_occ_scale = -1;
653                 }
654         }
655 
656         /* AMD-defined flags: level 0x80000001 */
657         xlvl = cpuid_eax(0x80000000);
658         c->extended_cpuid_level = xlvl;
659 
660         if ((xlvl & 0xffff0000) == 0x80000000) {
661                 if (xlvl >= 0x80000001) {
662                         c->x86_capability[1] = cpuid_edx(0x80000001);
663                         c->x86_capability[6] = cpuid_ecx(0x80000001);
664                 }
665         }
666 
667         if (c->extended_cpuid_level >= 0x80000008) {
668                 u32 eax = cpuid_eax(0x80000008);
669 
670                 c->x86_virt_bits = (eax >> 8) & 0xff;
671                 c->x86_phys_bits = eax & 0xff;
672         }
673 #ifdef CONFIG_X86_32
674         else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
675                 c->x86_phys_bits = 36;
676 #endif
677 
678         if (c->extended_cpuid_level >= 0x80000007)
679                 c->x86_power = cpuid_edx(0x80000007);
680 
681         init_scattered_cpuid_features(c);
682 }
683 
684 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
685 {
686 #ifdef CONFIG_X86_32
687         int i;
688 
689         /*
690          * First of all, decide if this is a 486 or higher
691          * It's a 486 if we can modify the AC flag
692          */
693         if (flag_is_changeable_p(X86_EFLAGS_AC))
694                 c->x86 = 4;
695         else
696                 c->x86 = 3;
697 
698         for (i = 0; i < X86_VENDOR_NUM; i++)
699                 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
700                         c->x86_vendor_id[0] = 0;
701                         cpu_devs[i]->c_identify(c);
702                         if (c->x86_vendor_id[0]) {
703                                 get_cpu_vendor(c);
704                                 break;
705                         }
706                 }
707 #endif
708 }
709 
710 /*
711  * Do minimum CPU detection early.
712  * Fields really needed: vendor, cpuid_level, family, model, mask,
713  * cache alignment.
714  * The others are not touched to avoid unwanted side effects.
715  *
716  * WARNING: this function is only called on the BP.  Don't add code here
717  * that is supposed to run on all CPUs.
718  */
719 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
720 {
721 #ifdef CONFIG_X86_64
722         c->x86_clflush_size = 64;
723         c->x86_phys_bits = 36;
724         c->x86_virt_bits = 48;
725 #else
726         c->x86_clflush_size = 32;
727         c->x86_phys_bits = 32;
728         c->x86_virt_bits = 32;
729 #endif
730         c->x86_cache_alignment = c->x86_clflush_size;
731 
732         memset(&c->x86_capability, 0, sizeof c->x86_capability);
733         c->extended_cpuid_level = 0;
734 
735         if (!have_cpuid_p())
736                 identify_cpu_without_cpuid(c);
737 
738         /* cyrix could have cpuid enabled via c_identify()*/
739         if (!have_cpuid_p())
740                 return;
741 
742         cpu_detect(c);
743         get_cpu_vendor(c);
744         get_cpu_cap(c);
745 
746         if (this_cpu->c_early_init)
747                 this_cpu->c_early_init(c);
748 
749         c->cpu_index = 0;
750         filter_cpuid_features(c, false);
751 
752         if (this_cpu->c_bsp_init)
753                 this_cpu->c_bsp_init(c);
754 
755         setup_force_cpu_cap(X86_FEATURE_ALWAYS);
756         fpu__init_system(c);
757 }
758 
759 void __init early_cpu_init(void)
760 {
761         const struct cpu_dev *const *cdev;
762         int count = 0;
763 
764 #ifdef CONFIG_PROCESSOR_SELECT
765         printk(KERN_INFO "KERNEL supported cpus:\n");
766 #endif
767 
768         for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
769                 const struct cpu_dev *cpudev = *cdev;
770 
771                 if (count >= X86_VENDOR_NUM)
772                         break;
773                 cpu_devs[count] = cpudev;
774                 count++;
775 
776 #ifdef CONFIG_PROCESSOR_SELECT
777                 {
778                         unsigned int j;
779 
780                         for (j = 0; j < 2; j++) {
781                                 if (!cpudev->c_ident[j])
782                                         continue;
783                                 printk(KERN_INFO "  %s %s\n", cpudev->c_vendor,
784                                         cpudev->c_ident[j]);
785                         }
786                 }
787 #endif
788         }
789         early_identify_cpu(&boot_cpu_data);
790 }
791 
792 /*
793  * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
794  * unfortunately, that's not true in practice because of early VIA
795  * chips and (more importantly) broken virtualizers that are not easy
796  * to detect. In the latter case it doesn't even *fail* reliably, so
797  * probing for it doesn't even work. Disable it completely on 32-bit
798  * unless we can find a reliable way to detect all the broken cases.
799  * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
800  */
801 static void detect_nopl(struct cpuinfo_x86 *c)
802 {
803 #ifdef CONFIG_X86_32
804         clear_cpu_cap(c, X86_FEATURE_NOPL);
805 #else
806         set_cpu_cap(c, X86_FEATURE_NOPL);
807 #endif
808 }
809 
810 static void generic_identify(struct cpuinfo_x86 *c)
811 {
812         c->extended_cpuid_level = 0;
813 
814         if (!have_cpuid_p())
815                 identify_cpu_without_cpuid(c);
816 
817         /* cyrix could have cpuid enabled via c_identify()*/
818         if (!have_cpuid_p())
819                 return;
820 
821         cpu_detect(c);
822 
823         get_cpu_vendor(c);
824 
825         get_cpu_cap(c);
826 
827         if (c->cpuid_level >= 0x00000001) {
828                 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
829 #ifdef CONFIG_X86_32
830 # ifdef CONFIG_SMP
831                 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
832 # else
833                 c->apicid = c->initial_apicid;
834 # endif
835 #endif
836                 c->phys_proc_id = c->initial_apicid;
837         }
838 
839         get_model_name(c); /* Default name */
840 
841         detect_nopl(c);
842 }
843 
844 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
845 {
846         /*
847          * The heavy lifting of max_rmid and cache_occ_scale are handled
848          * in get_cpu_cap().  Here we just set the max_rmid for the boot_cpu
849          * in case CQM bits really aren't there in this CPU.
850          */
851         if (c != &boot_cpu_data) {
852                 boot_cpu_data.x86_cache_max_rmid =
853                         min(boot_cpu_data.x86_cache_max_rmid,
854                             c->x86_cache_max_rmid);
855         }
856 }
857 
858 /*
859  * This does the hard work of actually picking apart the CPU stuff...
860  */
861 static void identify_cpu(struct cpuinfo_x86 *c)
862 {
863         int i;
864 
865         c->loops_per_jiffy = loops_per_jiffy;
866         c->x86_cache_size = -1;
867         c->x86_vendor = X86_VENDOR_UNKNOWN;
868         c->x86_model = c->x86_mask = 0; /* So far unknown... */
869         c->x86_vendor_id[0] = '\0'; /* Unset */
870         c->x86_model_id[0] = '\0';  /* Unset */
871         c->x86_max_cores = 1;
872         c->x86_coreid_bits = 0;
873 #ifdef CONFIG_X86_64
874         c->x86_clflush_size = 64;
875         c->x86_phys_bits = 36;
876         c->x86_virt_bits = 48;
877 #else
878         c->cpuid_level = -1;    /* CPUID not detected */
879         c->x86_clflush_size = 32;
880         c->x86_phys_bits = 32;
881         c->x86_virt_bits = 32;
882 #endif
883         c->x86_cache_alignment = c->x86_clflush_size;
884         memset(&c->x86_capability, 0, sizeof c->x86_capability);
885 
886         generic_identify(c);
887 
888         if (this_cpu->c_identify)
889                 this_cpu->c_identify(c);
890 
891         /* Clear/Set all flags overriden by options, after probe */
892         for (i = 0; i < NCAPINTS; i++) {
893                 c->x86_capability[i] &= ~cpu_caps_cleared[i];
894                 c->x86_capability[i] |= cpu_caps_set[i];
895         }
896 
897 #ifdef CONFIG_X86_64
898         c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
899 #endif
900 
901         /*
902          * Vendor-specific initialization.  In this section we
903          * canonicalize the feature flags, meaning if there are
904          * features a certain CPU supports which CPUID doesn't
905          * tell us, CPUID claiming incorrect flags, or other bugs,
906          * we handle them here.
907          *
908          * At the end of this section, c->x86_capability better
909          * indicate the features this CPU genuinely supports!
910          */
911         if (this_cpu->c_init)
912                 this_cpu->c_init(c);
913 
914         /* Disable the PN if appropriate */
915         squash_the_stupid_serial_number(c);
916 
917         /* Set up SMEP/SMAP */
918         setup_smep(c);
919         setup_smap(c);
920 
921         /*
922          * The vendor-specific functions might have changed features.
923          * Now we do "generic changes."
924          */
925 
926         /* Filter out anything that depends on CPUID levels we don't have */
927         filter_cpuid_features(c, true);
928 
929         /* If the model name is still unset, do table lookup. */
930         if (!c->x86_model_id[0]) {
931                 const char *p;
932                 p = table_lookup_model(c);
933                 if (p)
934                         strcpy(c->x86_model_id, p);
935                 else
936                         /* Last resort... */
937                         sprintf(c->x86_model_id, "%02x/%02x",
938                                 c->x86, c->x86_model);
939         }
940 
941 #ifdef CONFIG_X86_64
942         detect_ht(c);
943 #endif
944 
945         init_hypervisor(c);
946         x86_init_rdrand(c);
947         x86_init_cache_qos(c);
948 
949         /*
950          * Clear/Set all flags overriden by options, need do it
951          * before following smp all cpus cap AND.
952          */
953         for (i = 0; i < NCAPINTS; i++) {
954                 c->x86_capability[i] &= ~cpu_caps_cleared[i];
955                 c->x86_capability[i] |= cpu_caps_set[i];
956         }
957 
958         /*
959          * On SMP, boot_cpu_data holds the common feature set between
960          * all CPUs; so make sure that we indicate which features are
961          * common between the CPUs.  The first time this routine gets
962          * executed, c == &boot_cpu_data.
963          */
964         if (c != &boot_cpu_data) {
965                 /* AND the already accumulated flags with these */
966                 for (i = 0; i < NCAPINTS; i++)
967                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
968 
969                 /* OR, i.e. replicate the bug flags */
970                 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
971                         c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
972         }
973 
974         /* Init Machine Check Exception if available. */
975         mcheck_cpu_init(c);
976 
977         select_idle_routine(c);
978 
979 #ifdef CONFIG_NUMA
980         numa_add_cpu(smp_processor_id());
981 #endif
982 }
983 
984 /*
985  * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
986  * on 32-bit kernels:
987  */
988 #ifdef CONFIG_X86_32
989 void enable_sep_cpu(void)
990 {
991         struct tss_struct *tss;
992         int cpu;
993 
994         cpu = get_cpu();
995         tss = &per_cpu(cpu_tss, cpu);
996 
997         if (!boot_cpu_has(X86_FEATURE_SEP))
998                 goto out;
999 
1000         /*
1001          * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1002          * see the big comment in struct x86_hw_tss's definition.
1003          */
1004 
1005         tss->x86_tss.ss1 = __KERNEL_CS;
1006         wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1007 
1008         wrmsr(MSR_IA32_SYSENTER_ESP,
1009               (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack),
1010               0);
1011 
1012         wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1013 
1014 out:
1015         put_cpu();
1016 }
1017 #endif
1018 
1019 void __init identify_boot_cpu(void)
1020 {
1021         identify_cpu(&boot_cpu_data);
1022         init_amd_e400_c1e_mask();
1023 #ifdef CONFIG_X86_32
1024         sysenter_setup();
1025         enable_sep_cpu();
1026 #endif
1027         cpu_detect_tlb(&boot_cpu_data);
1028 }
1029 
1030 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1031 {
1032         BUG_ON(c == &boot_cpu_data);
1033         identify_cpu(c);
1034 #ifdef CONFIG_X86_32
1035         enable_sep_cpu();
1036 #endif
1037         mtrr_ap_init();
1038 }
1039 
1040 struct msr_range {
1041         unsigned        min;
1042         unsigned        max;
1043 };
1044 
1045 static const struct msr_range msr_range_array[] = {
1046         { 0x00000000, 0x00000418},
1047         { 0xc0000000, 0xc000040b},
1048         { 0xc0010000, 0xc0010142},
1049         { 0xc0011000, 0xc001103b},
1050 };
1051 
1052 static void __print_cpu_msr(void)
1053 {
1054         unsigned index_min, index_max;
1055         unsigned index;
1056         u64 val;
1057         int i;
1058 
1059         for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1060                 index_min = msr_range_array[i].min;
1061                 index_max = msr_range_array[i].max;
1062 
1063                 for (index = index_min; index < index_max; index++) {
1064                         if (rdmsrl_safe(index, &val))
1065                                 continue;
1066                         printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
1067                 }
1068         }
1069 }
1070 
1071 static int show_msr;
1072 
1073 static __init int setup_show_msr(char *arg)
1074 {
1075         int num;
1076 
1077         get_option(&arg, &num);
1078 
1079         if (num > 0)
1080                 show_msr = num;
1081         return 1;
1082 }
1083 __setup("show_msr=", setup_show_msr);
1084 
1085 static __init int setup_noclflush(char *arg)
1086 {
1087         setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1088         setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1089         return 1;
1090 }
1091 __setup("noclflush", setup_noclflush);
1092 
1093 void print_cpu_info(struct cpuinfo_x86 *c)
1094 {
1095         const char *vendor = NULL;
1096 
1097         if (c->x86_vendor < X86_VENDOR_NUM) {
1098                 vendor = this_cpu->c_vendor;
1099         } else {
1100                 if (c->cpuid_level >= 0)
1101                         vendor = c->x86_vendor_id;
1102         }
1103 
1104         if (vendor && !strstr(c->x86_model_id, vendor))
1105                 printk(KERN_CONT "%s ", vendor);
1106 
1107         if (c->x86_model_id[0])
1108                 printk(KERN_CONT "%s", c->x86_model_id);
1109         else
1110                 printk(KERN_CONT "%d86", c->x86);
1111 
1112         printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model);
1113 
1114         if (c->x86_mask || c->cpuid_level >= 0)
1115                 printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask);
1116         else
1117                 printk(KERN_CONT ")\n");
1118 
1119         print_cpu_msr(c);
1120 }
1121 
1122 void print_cpu_msr(struct cpuinfo_x86 *c)
1123 {
1124         if (c->cpu_index < show_msr)
1125                 __print_cpu_msr();
1126 }
1127 
1128 static __init int setup_disablecpuid(char *arg)
1129 {
1130         int bit;
1131 
1132         if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1133                 setup_clear_cpu_cap(bit);
1134         else
1135                 return 0;
1136 
1137         return 1;
1138 }
1139 __setup("clearcpuid=", setup_disablecpuid);
1140 
1141 #ifdef CONFIG_X86_64
1142 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1143 struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1,
1144                                     (unsigned long) debug_idt_table };
1145 
1146 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1147                      irq_stack_union) __aligned(PAGE_SIZE) __visible;
1148 
1149 /*
1150  * The following percpu variables are hot.  Align current_task to
1151  * cacheline size such that they fall in the same cacheline.
1152  */
1153 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1154         &init_task;
1155 EXPORT_PER_CPU_SYMBOL(current_task);
1156 
1157 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1158         init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1159 
1160 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1161 
1162 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1163 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1164 
1165 /*
1166  * Special IST stacks which the CPU switches to when it calls
1167  * an IST-marked descriptor entry. Up to 7 stacks (hardware
1168  * limit), all of them are 4K, except the debug stack which
1169  * is 8K.
1170  */
1171 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1172           [0 ... N_EXCEPTION_STACKS - 1]        = EXCEPTION_STKSZ,
1173           [DEBUG_STACK - 1]                     = DEBUG_STKSZ
1174 };
1175 
1176 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1177         [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1178 
1179 /* May not be marked __init: used by software suspend */
1180 void syscall_init(void)
1181 {
1182         /*
1183          * LSTAR and STAR live in a bit strange symbiosis.
1184          * They both write to the same internal register. STAR allows to
1185          * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1186          */
1187         wrmsrl(MSR_STAR,  ((u64)__USER32_CS)<<48  | ((u64)__KERNEL_CS)<<32);
1188         wrmsrl(MSR_LSTAR, entry_SYSCALL_64);
1189 
1190 #ifdef CONFIG_IA32_EMULATION
1191         wrmsrl(MSR_CSTAR, entry_SYSCALL_compat);
1192         /*
1193          * This only works on Intel CPUs.
1194          * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1195          * This does not cause SYSENTER to jump to the wrong location, because
1196          * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1197          */
1198         wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1199         wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1200         wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1201 #else
1202         wrmsrl(MSR_CSTAR, ignore_sysret);
1203         wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1204         wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1205         wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1206 #endif
1207 
1208         /* Flags to clear on syscall */
1209         wrmsrl(MSR_SYSCALL_MASK,
1210                X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1211                X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1212 }
1213 
1214 /*
1215  * Copies of the original ist values from the tss are only accessed during
1216  * debugging, no special alignment required.
1217  */
1218 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1219 
1220 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1221 DEFINE_PER_CPU(int, debug_stack_usage);
1222 
1223 int is_debug_stack(unsigned long addr)
1224 {
1225         return __this_cpu_read(debug_stack_usage) ||
1226                 (addr <= __this_cpu_read(debug_stack_addr) &&
1227                  addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1228 }
1229 NOKPROBE_SYMBOL(is_debug_stack);
1230 
1231 DEFINE_PER_CPU(u32, debug_idt_ctr);
1232 
1233 void debug_stack_set_zero(void)
1234 {
1235         this_cpu_inc(debug_idt_ctr);
1236         load_current_idt();
1237 }
1238 NOKPROBE_SYMBOL(debug_stack_set_zero);
1239 
1240 void debug_stack_reset(void)
1241 {
1242         if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1243                 return;
1244         if (this_cpu_dec_return(debug_idt_ctr) == 0)
1245                 load_current_idt();
1246 }
1247 NOKPROBE_SYMBOL(debug_stack_reset);
1248 
1249 #else   /* CONFIG_X86_64 */
1250 
1251 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1252 EXPORT_PER_CPU_SYMBOL(current_task);
1253 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1254 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1255 
1256 /*
1257  * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1258  * the top of the kernel stack.  Use an extra percpu variable to track the
1259  * top of the kernel stack directly.
1260  */
1261 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1262         (unsigned long)&init_thread_union + THREAD_SIZE;
1263 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1264 
1265 #ifdef CONFIG_CC_STACKPROTECTOR
1266 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1267 #endif
1268 
1269 #endif  /* CONFIG_X86_64 */
1270 
1271 /*
1272  * Clear all 6 debug registers:
1273  */
1274 static void clear_all_debug_regs(void)
1275 {
1276         int i;
1277 
1278         for (i = 0; i < 8; i++) {
1279                 /* Ignore db4, db5 */
1280                 if ((i == 4) || (i == 5))
1281                         continue;
1282 
1283                 set_debugreg(0, i);
1284         }
1285 }
1286 
1287 #ifdef CONFIG_KGDB
1288 /*
1289  * Restore debug regs if using kgdbwait and you have a kernel debugger
1290  * connection established.
1291  */
1292 static void dbg_restore_debug_regs(void)
1293 {
1294         if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1295                 arch_kgdb_ops.correct_hw_break();
1296 }
1297 #else /* ! CONFIG_KGDB */
1298 #define dbg_restore_debug_regs()
1299 #endif /* ! CONFIG_KGDB */
1300 
1301 static void wait_for_master_cpu(int cpu)
1302 {
1303 #ifdef CONFIG_SMP
1304         /*
1305          * wait for ACK from master CPU before continuing
1306          * with AP initialization
1307          */
1308         WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1309         while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1310                 cpu_relax();
1311 #endif
1312 }
1313 
1314 /*
1315  * cpu_init() initializes state that is per-CPU. Some data is already
1316  * initialized (naturally) in the bootstrap process, such as the GDT
1317  * and IDT. We reload them nevertheless, this function acts as a
1318  * 'CPU state barrier', nothing should get across.
1319  * A lot of state is already set up in PDA init for 64 bit
1320  */
1321 #ifdef CONFIG_X86_64
1322 
1323 void cpu_init(void)
1324 {
1325         struct orig_ist *oist;
1326         struct task_struct *me;
1327         struct tss_struct *t;
1328         unsigned long v;
1329         int cpu = stack_smp_processor_id();
1330         int i;
1331 
1332         wait_for_master_cpu(cpu);
1333 
1334         /*
1335          * Initialize the CR4 shadow before doing anything that could
1336          * try to read it.
1337          */
1338         cr4_init_shadow();
1339 
1340         /*
1341          * Load microcode on this cpu if a valid microcode is available.
1342          * This is early microcode loading procedure.
1343          */
1344         load_ucode_ap();
1345 
1346         t = &per_cpu(cpu_tss, cpu);
1347         oist = &per_cpu(orig_ist, cpu);
1348 
1349 #ifdef CONFIG_NUMA
1350         if (this_cpu_read(numa_node) == 0 &&
1351             early_cpu_to_node(cpu) != NUMA_NO_NODE)
1352                 set_numa_node(early_cpu_to_node(cpu));
1353 #endif
1354 
1355         me = current;
1356 
1357         pr_debug("Initializing CPU#%d\n", cpu);
1358 
1359         cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1360 
1361         /*
1362          * Initialize the per-CPU GDT with the boot GDT,
1363          * and set up the GDT descriptor:
1364          */
1365 
1366         switch_to_new_gdt(cpu);
1367         loadsegment(fs, 0);
1368 
1369         load_current_idt();
1370 
1371         memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1372         syscall_init();
1373 
1374         wrmsrl(MSR_FS_BASE, 0);
1375         wrmsrl(MSR_KERNEL_GS_BASE, 0);
1376         barrier();
1377 
1378         x86_configure_nx();
1379         x2apic_setup();
1380 
1381         /*
1382          * set up and load the per-CPU TSS
1383          */
1384         if (!oist->ist[0]) {
1385                 char *estacks = per_cpu(exception_stacks, cpu);
1386 
1387                 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1388                         estacks += exception_stack_sizes[v];
1389                         oist->ist[v] = t->x86_tss.ist[v] =
1390                                         (unsigned long)estacks;
1391                         if (v == DEBUG_STACK-1)
1392                                 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1393                 }
1394         }
1395 
1396         t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1397 
1398         /*
1399          * <= is required because the CPU will access up to
1400          * 8 bits beyond the end of the IO permission bitmap.
1401          */
1402         for (i = 0; i <= IO_BITMAP_LONGS; i++)
1403                 t->io_bitmap[i] = ~0UL;
1404 
1405         atomic_inc(&init_mm.mm_count);
1406         me->active_mm = &init_mm;
1407         BUG_ON(me->mm);
1408         enter_lazy_tlb(&init_mm, me);
1409 
1410         load_sp0(t, &current->thread);
1411         set_tss_desc(cpu, t);
1412         load_TR_desc();
1413         load_mm_ldt(&init_mm);
1414 
1415         clear_all_debug_regs();
1416         dbg_restore_debug_regs();
1417 
1418         fpu__init_cpu();
1419 
1420         if (is_uv_system())
1421                 uv_cpu_init();
1422 }
1423 
1424 #else
1425 
1426 void cpu_init(void)
1427 {
1428         int cpu = smp_processor_id();
1429         struct task_struct *curr = current;
1430         struct tss_struct *t = &per_cpu(cpu_tss, cpu);
1431         struct thread_struct *thread = &curr->thread;
1432 
1433         wait_for_master_cpu(cpu);
1434 
1435         /*
1436          * Initialize the CR4 shadow before doing anything that could
1437          * try to read it.
1438          */
1439         cr4_init_shadow();
1440 
1441         show_ucode_info_early();
1442 
1443         printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1444 
1445         if (cpu_feature_enabled(X86_FEATURE_VME) || cpu_has_tsc || cpu_has_de)
1446                 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1447 
1448         load_current_idt();
1449         switch_to_new_gdt(cpu);
1450 
1451         /*
1452          * Set up and load the per-CPU TSS and LDT
1453          */
1454         atomic_inc(&init_mm.mm_count);
1455         curr->active_mm = &init_mm;
1456         BUG_ON(curr->mm);
1457         enter_lazy_tlb(&init_mm, curr);
1458 
1459         load_sp0(t, thread);
1460         set_tss_desc(cpu, t);
1461         load_TR_desc();
1462         load_mm_ldt(&init_mm);
1463 
1464         t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1465 
1466 #ifdef CONFIG_DOUBLEFAULT
1467         /* Set up doublefault TSS pointer in the GDT */
1468         __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1469 #endif
1470 
1471         clear_all_debug_regs();
1472         dbg_restore_debug_regs();
1473 
1474         fpu__init_cpu();
1475 }
1476 #endif
1477 
1478 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
1479 void warn_pre_alternatives(void)
1480 {
1481         WARN(1, "You're using static_cpu_has before alternatives have run!\n");
1482 }
1483 EXPORT_SYMBOL_GPL(warn_pre_alternatives);
1484 #endif
1485 
1486 inline bool __static_cpu_has_safe(u16 bit)
1487 {
1488         return boot_cpu_has(bit);
1489 }
1490 EXPORT_SYMBOL_GPL(__static_cpu_has_safe);
1491 

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