Version:  2.0.40 2.2.26 2.4.37 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

Linux/arch/x86/kernel/cpu/common.c

  1 #include <linux/bootmem.h>
  2 #include <linux/linkage.h>
  3 #include <linux/bitops.h>
  4 #include <linux/kernel.h>
  5 #include <linux/export.h>
  6 #include <linux/percpu.h>
  7 #include <linux/string.h>
  8 #include <linux/ctype.h>
  9 #include <linux/delay.h>
 10 #include <linux/sched.h>
 11 #include <linux/init.h>
 12 #include <linux/kprobes.h>
 13 #include <linux/kgdb.h>
 14 #include <linux/smp.h>
 15 #include <linux/io.h>
 16 #include <linux/syscore_ops.h>
 17 
 18 #include <asm/stackprotector.h>
 19 #include <asm/perf_event.h>
 20 #include <asm/mmu_context.h>
 21 #include <asm/archrandom.h>
 22 #include <asm/hypervisor.h>
 23 #include <asm/processor.h>
 24 #include <asm/tlbflush.h>
 25 #include <asm/debugreg.h>
 26 #include <asm/sections.h>
 27 #include <asm/vsyscall.h>
 28 #include <linux/topology.h>
 29 #include <linux/cpumask.h>
 30 #include <asm/pgtable.h>
 31 #include <linux/atomic.h>
 32 #include <asm/proto.h>
 33 #include <asm/setup.h>
 34 #include <asm/apic.h>
 35 #include <asm/desc.h>
 36 #include <asm/fpu/internal.h>
 37 #include <asm/mtrr.h>
 38 #include <linux/numa.h>
 39 #include <asm/asm.h>
 40 #include <asm/bugs.h>
 41 #include <asm/cpu.h>
 42 #include <asm/mce.h>
 43 #include <asm/msr.h>
 44 #include <asm/pat.h>
 45 #include <asm/microcode.h>
 46 #include <asm/microcode_intel.h>
 47 
 48 #ifdef CONFIG_X86_LOCAL_APIC
 49 #include <asm/uv/uv.h>
 50 #endif
 51 
 52 #include "cpu.h"
 53 
 54 /* all of these masks are initialized in setup_cpu_local_masks() */
 55 cpumask_var_t cpu_initialized_mask;
 56 cpumask_var_t cpu_callout_mask;
 57 cpumask_var_t cpu_callin_mask;
 58 
 59 /* representing cpus for which sibling maps can be computed */
 60 cpumask_var_t cpu_sibling_setup_mask;
 61 
 62 /* correctly size the local cpu masks */
 63 void __init setup_cpu_local_masks(void)
 64 {
 65         alloc_bootmem_cpumask_var(&cpu_initialized_mask);
 66         alloc_bootmem_cpumask_var(&cpu_callin_mask);
 67         alloc_bootmem_cpumask_var(&cpu_callout_mask);
 68         alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
 69 }
 70 
 71 static void default_init(struct cpuinfo_x86 *c)
 72 {
 73 #ifdef CONFIG_X86_64
 74         cpu_detect_cache_sizes(c);
 75 #else
 76         /* Not much we can do here... */
 77         /* Check if at least it has cpuid */
 78         if (c->cpuid_level == -1) {
 79                 /* No cpuid. It must be an ancient CPU */
 80                 if (c->x86 == 4)
 81                         strcpy(c->x86_model_id, "486");
 82                 else if (c->x86 == 3)
 83                         strcpy(c->x86_model_id, "386");
 84         }
 85 #endif
 86 }
 87 
 88 static const struct cpu_dev default_cpu = {
 89         .c_init         = default_init,
 90         .c_vendor       = "Unknown",
 91         .c_x86_vendor   = X86_VENDOR_UNKNOWN,
 92 };
 93 
 94 static const struct cpu_dev *this_cpu = &default_cpu;
 95 
 96 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
 97 #ifdef CONFIG_X86_64
 98         /*
 99          * We need valid kernel segments for data and code in long mode too
100          * IRET will check the segment types  kkeil 2000/10/28
101          * Also sysret mandates a special GDT layout
102          *
103          * TLS descriptors are currently at a different place compared to i386.
104          * Hopefully nobody expects them at a fixed place (Wine?)
105          */
106         [GDT_ENTRY_KERNEL32_CS]         = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
107         [GDT_ENTRY_KERNEL_CS]           = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
108         [GDT_ENTRY_KERNEL_DS]           = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
109         [GDT_ENTRY_DEFAULT_USER32_CS]   = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
110         [GDT_ENTRY_DEFAULT_USER_DS]     = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
111         [GDT_ENTRY_DEFAULT_USER_CS]     = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
112 #else
113         [GDT_ENTRY_KERNEL_CS]           = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
114         [GDT_ENTRY_KERNEL_DS]           = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
115         [GDT_ENTRY_DEFAULT_USER_CS]     = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
116         [GDT_ENTRY_DEFAULT_USER_DS]     = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
117         /*
118          * Segments used for calling PnP BIOS have byte granularity.
119          * They code segments and data segments have fixed 64k limits,
120          * the transfer segment sizes are set at run time.
121          */
122         /* 32-bit code */
123         [GDT_ENTRY_PNPBIOS_CS32]        = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
124         /* 16-bit code */
125         [GDT_ENTRY_PNPBIOS_CS16]        = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
126         /* 16-bit data */
127         [GDT_ENTRY_PNPBIOS_DS]          = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
128         /* 16-bit data */
129         [GDT_ENTRY_PNPBIOS_TS1]         = GDT_ENTRY_INIT(0x0092, 0, 0),
130         /* 16-bit data */
131         [GDT_ENTRY_PNPBIOS_TS2]         = GDT_ENTRY_INIT(0x0092, 0, 0),
132         /*
133          * The APM segments have byte granularity and their bases
134          * are set at run time.  All have 64k limits.
135          */
136         /* 32-bit code */
137         [GDT_ENTRY_APMBIOS_BASE]        = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
138         /* 16-bit code */
139         [GDT_ENTRY_APMBIOS_BASE+1]      = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
140         /* data */
141         [GDT_ENTRY_APMBIOS_BASE+2]      = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
142 
143         [GDT_ENTRY_ESPFIX_SS]           = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
144         [GDT_ENTRY_PERCPU]              = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
145         GDT_STACK_CANARY_INIT
146 #endif
147 } };
148 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
149 
150 static int __init x86_mpx_setup(char *s)
151 {
152         /* require an exact match without trailing characters */
153         if (strlen(s))
154                 return 0;
155 
156         /* do not emit a message if the feature is not present */
157         if (!boot_cpu_has(X86_FEATURE_MPX))
158                 return 1;
159 
160         setup_clear_cpu_cap(X86_FEATURE_MPX);
161         pr_info("nompx: Intel Memory Protection Extensions (MPX) disabled\n");
162         return 1;
163 }
164 __setup("nompx", x86_mpx_setup);
165 
166 static int __init x86_noinvpcid_setup(char *s)
167 {
168         /* noinvpcid doesn't accept parameters */
169         if (s)
170                 return -EINVAL;
171 
172         /* do not emit a message if the feature is not present */
173         if (!boot_cpu_has(X86_FEATURE_INVPCID))
174                 return 0;
175 
176         setup_clear_cpu_cap(X86_FEATURE_INVPCID);
177         pr_info("noinvpcid: INVPCID feature disabled\n");
178         return 0;
179 }
180 early_param("noinvpcid", x86_noinvpcid_setup);
181 
182 #ifdef CONFIG_X86_32
183 static int cachesize_override = -1;
184 static int disable_x86_serial_nr = 1;
185 
186 static int __init cachesize_setup(char *str)
187 {
188         get_option(&str, &cachesize_override);
189         return 1;
190 }
191 __setup("cachesize=", cachesize_setup);
192 
193 static int __init x86_sep_setup(char *s)
194 {
195         setup_clear_cpu_cap(X86_FEATURE_SEP);
196         return 1;
197 }
198 __setup("nosep", x86_sep_setup);
199 
200 /* Standard macro to see if a specific flag is changeable */
201 static inline int flag_is_changeable_p(u32 flag)
202 {
203         u32 f1, f2;
204 
205         /*
206          * Cyrix and IDT cpus allow disabling of CPUID
207          * so the code below may return different results
208          * when it is executed before and after enabling
209          * the CPUID. Add "volatile" to not allow gcc to
210          * optimize the subsequent calls to this function.
211          */
212         asm volatile ("pushfl           \n\t"
213                       "pushfl           \n\t"
214                       "popl %0          \n\t"
215                       "movl %0, %1      \n\t"
216                       "xorl %2, %0      \n\t"
217                       "pushl %0         \n\t"
218                       "popfl            \n\t"
219                       "pushfl           \n\t"
220                       "popl %0          \n\t"
221                       "popfl            \n\t"
222 
223                       : "=&r" (f1), "=&r" (f2)
224                       : "ir" (flag));
225 
226         return ((f1^f2) & flag) != 0;
227 }
228 
229 /* Probe for the CPUID instruction */
230 int have_cpuid_p(void)
231 {
232         return flag_is_changeable_p(X86_EFLAGS_ID);
233 }
234 
235 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
236 {
237         unsigned long lo, hi;
238 
239         if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
240                 return;
241 
242         /* Disable processor serial number: */
243 
244         rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
245         lo |= 0x200000;
246         wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
247 
248         pr_notice("CPU serial number disabled.\n");
249         clear_cpu_cap(c, X86_FEATURE_PN);
250 
251         /* Disabling the serial number may affect the cpuid level */
252         c->cpuid_level = cpuid_eax(0);
253 }
254 
255 static int __init x86_serial_nr_setup(char *s)
256 {
257         disable_x86_serial_nr = 0;
258         return 1;
259 }
260 __setup("serialnumber", x86_serial_nr_setup);
261 #else
262 static inline int flag_is_changeable_p(u32 flag)
263 {
264         return 1;
265 }
266 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
267 {
268 }
269 #endif
270 
271 static __init int setup_disable_smep(char *arg)
272 {
273         setup_clear_cpu_cap(X86_FEATURE_SMEP);
274         /* Check for things that depend on SMEP being enabled: */
275         check_mpx_erratum(&boot_cpu_data);
276         return 1;
277 }
278 __setup("nosmep", setup_disable_smep);
279 
280 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
281 {
282         if (cpu_has(c, X86_FEATURE_SMEP))
283                 cr4_set_bits(X86_CR4_SMEP);
284 }
285 
286 static __init int setup_disable_smap(char *arg)
287 {
288         setup_clear_cpu_cap(X86_FEATURE_SMAP);
289         return 1;
290 }
291 __setup("nosmap", setup_disable_smap);
292 
293 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
294 {
295         unsigned long eflags = native_save_fl();
296 
297         /* This should have been cleared long ago */
298         BUG_ON(eflags & X86_EFLAGS_AC);
299 
300         if (cpu_has(c, X86_FEATURE_SMAP)) {
301 #ifdef CONFIG_X86_SMAP
302                 cr4_set_bits(X86_CR4_SMAP);
303 #else
304                 cr4_clear_bits(X86_CR4_SMAP);
305 #endif
306         }
307 }
308 
309 /*
310  * Protection Keys are not available in 32-bit mode.
311  */
312 static bool pku_disabled;
313 
314 static __always_inline void setup_pku(struct cpuinfo_x86 *c)
315 {
316         /* check the boot processor, plus compile options for PKU: */
317         if (!cpu_feature_enabled(X86_FEATURE_PKU))
318                 return;
319         /* checks the actual processor's cpuid bits: */
320         if (!cpu_has(c, X86_FEATURE_PKU))
321                 return;
322         if (pku_disabled)
323                 return;
324 
325         cr4_set_bits(X86_CR4_PKE);
326         /*
327          * Seting X86_CR4_PKE will cause the X86_FEATURE_OSPKE
328          * cpuid bit to be set.  We need to ensure that we
329          * update that bit in this CPU's "cpu_info".
330          */
331         get_cpu_cap(c);
332 }
333 
334 #ifdef CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS
335 static __init int setup_disable_pku(char *arg)
336 {
337         /*
338          * Do not clear the X86_FEATURE_PKU bit.  All of the
339          * runtime checks are against OSPKE so clearing the
340          * bit does nothing.
341          *
342          * This way, we will see "pku" in cpuinfo, but not
343          * "ospke", which is exactly what we want.  It shows
344          * that the CPU has PKU, but the OS has not enabled it.
345          * This happens to be exactly how a system would look
346          * if we disabled the config option.
347          */
348         pr_info("x86: 'nopku' specified, disabling Memory Protection Keys\n");
349         pku_disabled = true;
350         return 1;
351 }
352 __setup("nopku", setup_disable_pku);
353 #endif /* CONFIG_X86_64 */
354 
355 /*
356  * Some CPU features depend on higher CPUID levels, which may not always
357  * be available due to CPUID level capping or broken virtualization
358  * software.  Add those features to this table to auto-disable them.
359  */
360 struct cpuid_dependent_feature {
361         u32 feature;
362         u32 level;
363 };
364 
365 static const struct cpuid_dependent_feature
366 cpuid_dependent_features[] = {
367         { X86_FEATURE_MWAIT,            0x00000005 },
368         { X86_FEATURE_DCA,              0x00000009 },
369         { X86_FEATURE_XSAVE,            0x0000000d },
370         { 0, 0 }
371 };
372 
373 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
374 {
375         const struct cpuid_dependent_feature *df;
376 
377         for (df = cpuid_dependent_features; df->feature; df++) {
378 
379                 if (!cpu_has(c, df->feature))
380                         continue;
381                 /*
382                  * Note: cpuid_level is set to -1 if unavailable, but
383                  * extended_extended_level is set to 0 if unavailable
384                  * and the legitimate extended levels are all negative
385                  * when signed; hence the weird messing around with
386                  * signs here...
387                  */
388                 if (!((s32)df->level < 0 ?
389                      (u32)df->level > (u32)c->extended_cpuid_level :
390                      (s32)df->level > (s32)c->cpuid_level))
391                         continue;
392 
393                 clear_cpu_cap(c, df->feature);
394                 if (!warn)
395                         continue;
396 
397                 pr_warn("CPU: CPU feature " X86_CAP_FMT " disabled, no CPUID level 0x%x\n",
398                         x86_cap_flag(df->feature), df->level);
399         }
400 }
401 
402 /*
403  * Naming convention should be: <Name> [(<Codename>)]
404  * This table only is used unless init_<vendor>() below doesn't set it;
405  * in particular, if CPUID levels 0x80000002..4 are supported, this
406  * isn't used
407  */
408 
409 /* Look up CPU names by table lookup. */
410 static const char *table_lookup_model(struct cpuinfo_x86 *c)
411 {
412 #ifdef CONFIG_X86_32
413         const struct legacy_cpu_model_info *info;
414 
415         if (c->x86_model >= 16)
416                 return NULL;    /* Range check */
417 
418         if (!this_cpu)
419                 return NULL;
420 
421         info = this_cpu->legacy_models;
422 
423         while (info->family) {
424                 if (info->family == c->x86)
425                         return info->model_names[c->x86_model];
426                 info++;
427         }
428 #endif
429         return NULL;            /* Not found */
430 }
431 
432 __u32 cpu_caps_cleared[NCAPINTS];
433 __u32 cpu_caps_set[NCAPINTS];
434 
435 void load_percpu_segment(int cpu)
436 {
437 #ifdef CONFIG_X86_32
438         loadsegment(fs, __KERNEL_PERCPU);
439 #else
440         __loadsegment_simple(gs, 0);
441         wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
442 #endif
443         load_stack_canary_segment();
444 }
445 
446 /*
447  * Current gdt points %fs at the "master" per-cpu area: after this,
448  * it's on the real one.
449  */
450 void switch_to_new_gdt(int cpu)
451 {
452         struct desc_ptr gdt_descr;
453 
454         gdt_descr.address = (long)get_cpu_gdt_table(cpu);
455         gdt_descr.size = GDT_SIZE - 1;
456         load_gdt(&gdt_descr);
457         /* Reload the per-cpu base */
458 
459         load_percpu_segment(cpu);
460 }
461 
462 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
463 
464 static void get_model_name(struct cpuinfo_x86 *c)
465 {
466         unsigned int *v;
467         char *p, *q, *s;
468 
469         if (c->extended_cpuid_level < 0x80000004)
470                 return;
471 
472         v = (unsigned int *)c->x86_model_id;
473         cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
474         cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
475         cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
476         c->x86_model_id[48] = 0;
477 
478         /* Trim whitespace */
479         p = q = s = &c->x86_model_id[0];
480 
481         while (*p == ' ')
482                 p++;
483 
484         while (*p) {
485                 /* Note the last non-whitespace index */
486                 if (!isspace(*p))
487                         s = q;
488 
489                 *q++ = *p++;
490         }
491 
492         *(s + 1) = '\0';
493 }
494 
495 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
496 {
497         unsigned int n, dummy, ebx, ecx, edx, l2size;
498 
499         n = c->extended_cpuid_level;
500 
501         if (n >= 0x80000005) {
502                 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
503                 c->x86_cache_size = (ecx>>24) + (edx>>24);
504 #ifdef CONFIG_X86_64
505                 /* On K8 L1 TLB is inclusive, so don't count it */
506                 c->x86_tlbsize = 0;
507 #endif
508         }
509 
510         if (n < 0x80000006)     /* Some chips just has a large L1. */
511                 return;
512 
513         cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
514         l2size = ecx >> 16;
515 
516 #ifdef CONFIG_X86_64
517         c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
518 #else
519         /* do processor-specific cache resizing */
520         if (this_cpu->legacy_cache_size)
521                 l2size = this_cpu->legacy_cache_size(c, l2size);
522 
523         /* Allow user to override all this if necessary. */
524         if (cachesize_override != -1)
525                 l2size = cachesize_override;
526 
527         if (l2size == 0)
528                 return;         /* Again, no L2 cache is possible */
529 #endif
530 
531         c->x86_cache_size = l2size;
532 }
533 
534 u16 __read_mostly tlb_lli_4k[NR_INFO];
535 u16 __read_mostly tlb_lli_2m[NR_INFO];
536 u16 __read_mostly tlb_lli_4m[NR_INFO];
537 u16 __read_mostly tlb_lld_4k[NR_INFO];
538 u16 __read_mostly tlb_lld_2m[NR_INFO];
539 u16 __read_mostly tlb_lld_4m[NR_INFO];
540 u16 __read_mostly tlb_lld_1g[NR_INFO];
541 
542 static void cpu_detect_tlb(struct cpuinfo_x86 *c)
543 {
544         if (this_cpu->c_detect_tlb)
545                 this_cpu->c_detect_tlb(c);
546 
547         pr_info("Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n",
548                 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
549                 tlb_lli_4m[ENTRIES]);
550 
551         pr_info("Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n",
552                 tlb_lld_4k[ENTRIES], tlb_lld_2m[ENTRIES],
553                 tlb_lld_4m[ENTRIES], tlb_lld_1g[ENTRIES]);
554 }
555 
556 void detect_ht(struct cpuinfo_x86 *c)
557 {
558 #ifdef CONFIG_SMP
559         u32 eax, ebx, ecx, edx;
560         int index_msb, core_bits;
561         static bool printed;
562 
563         if (!cpu_has(c, X86_FEATURE_HT))
564                 return;
565 
566         if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
567                 goto out;
568 
569         if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
570                 return;
571 
572         cpuid(1, &eax, &ebx, &ecx, &edx);
573 
574         smp_num_siblings = (ebx & 0xff0000) >> 16;
575 
576         if (smp_num_siblings == 1) {
577                 pr_info_once("CPU0: Hyper-Threading is disabled\n");
578                 goto out;
579         }
580 
581         if (smp_num_siblings <= 1)
582                 goto out;
583 
584         index_msb = get_count_order(smp_num_siblings);
585         c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
586 
587         smp_num_siblings = smp_num_siblings / c->x86_max_cores;
588 
589         index_msb = get_count_order(smp_num_siblings);
590 
591         core_bits = get_count_order(c->x86_max_cores);
592 
593         c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
594                                        ((1 << core_bits) - 1);
595 
596 out:
597         if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
598                 pr_info("CPU: Physical Processor ID: %d\n",
599                         c->phys_proc_id);
600                 pr_info("CPU: Processor Core ID: %d\n",
601                         c->cpu_core_id);
602                 printed = 1;
603         }
604 #endif
605 }
606 
607 static void get_cpu_vendor(struct cpuinfo_x86 *c)
608 {
609         char *v = c->x86_vendor_id;
610         int i;
611 
612         for (i = 0; i < X86_VENDOR_NUM; i++) {
613                 if (!cpu_devs[i])
614                         break;
615 
616                 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
617                     (cpu_devs[i]->c_ident[1] &&
618                      !strcmp(v, cpu_devs[i]->c_ident[1]))) {
619 
620                         this_cpu = cpu_devs[i];
621                         c->x86_vendor = this_cpu->c_x86_vendor;
622                         return;
623                 }
624         }
625 
626         pr_err_once("CPU: vendor_id '%s' unknown, using generic init.\n" \
627                     "CPU: Your system may be unstable.\n", v);
628 
629         c->x86_vendor = X86_VENDOR_UNKNOWN;
630         this_cpu = &default_cpu;
631 }
632 
633 void cpu_detect(struct cpuinfo_x86 *c)
634 {
635         /* Get vendor name */
636         cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
637               (unsigned int *)&c->x86_vendor_id[0],
638               (unsigned int *)&c->x86_vendor_id[8],
639               (unsigned int *)&c->x86_vendor_id[4]);
640 
641         c->x86 = 4;
642         /* Intel-defined flags: level 0x00000001 */
643         if (c->cpuid_level >= 0x00000001) {
644                 u32 junk, tfms, cap0, misc;
645 
646                 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
647                 c->x86          = x86_family(tfms);
648                 c->x86_model    = x86_model(tfms);
649                 c->x86_mask     = x86_stepping(tfms);
650 
651                 if (cap0 & (1<<19)) {
652                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
653                         c->x86_cache_alignment = c->x86_clflush_size;
654                 }
655         }
656 }
657 
658 void get_cpu_cap(struct cpuinfo_x86 *c)
659 {
660         u32 eax, ebx, ecx, edx;
661 
662         /* Intel-defined flags: level 0x00000001 */
663         if (c->cpuid_level >= 0x00000001) {
664                 cpuid(0x00000001, &eax, &ebx, &ecx, &edx);
665 
666                 c->x86_capability[CPUID_1_ECX] = ecx;
667                 c->x86_capability[CPUID_1_EDX] = edx;
668         }
669 
670         /* Thermal and Power Management Leaf: level 0x00000006 (eax) */
671         if (c->cpuid_level >= 0x00000006)
672                 c->x86_capability[CPUID_6_EAX] = cpuid_eax(0x00000006);
673 
674         /* Additional Intel-defined flags: level 0x00000007 */
675         if (c->cpuid_level >= 0x00000007) {
676                 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
677                 c->x86_capability[CPUID_7_0_EBX] = ebx;
678                 c->x86_capability[CPUID_7_ECX] = ecx;
679         }
680 
681         /* Extended state features: level 0x0000000d */
682         if (c->cpuid_level >= 0x0000000d) {
683                 cpuid_count(0x0000000d, 1, &eax, &ebx, &ecx, &edx);
684 
685                 c->x86_capability[CPUID_D_1_EAX] = eax;
686         }
687 
688         /* Additional Intel-defined flags: level 0x0000000F */
689         if (c->cpuid_level >= 0x0000000F) {
690 
691                 /* QoS sub-leaf, EAX=0Fh, ECX=0 */
692                 cpuid_count(0x0000000F, 0, &eax, &ebx, &ecx, &edx);
693                 c->x86_capability[CPUID_F_0_EDX] = edx;
694 
695                 if (cpu_has(c, X86_FEATURE_CQM_LLC)) {
696                         /* will be overridden if occupancy monitoring exists */
697                         c->x86_cache_max_rmid = ebx;
698 
699                         /* QoS sub-leaf, EAX=0Fh, ECX=1 */
700                         cpuid_count(0x0000000F, 1, &eax, &ebx, &ecx, &edx);
701                         c->x86_capability[CPUID_F_1_EDX] = edx;
702 
703                         if ((cpu_has(c, X86_FEATURE_CQM_OCCUP_LLC)) ||
704                               ((cpu_has(c, X86_FEATURE_CQM_MBM_TOTAL)) ||
705                                (cpu_has(c, X86_FEATURE_CQM_MBM_LOCAL)))) {
706                                 c->x86_cache_max_rmid = ecx;
707                                 c->x86_cache_occ_scale = ebx;
708                         }
709                 } else {
710                         c->x86_cache_max_rmid = -1;
711                         c->x86_cache_occ_scale = -1;
712                 }
713         }
714 
715         /* AMD-defined flags: level 0x80000001 */
716         eax = cpuid_eax(0x80000000);
717         c->extended_cpuid_level = eax;
718 
719         if ((eax & 0xffff0000) == 0x80000000) {
720                 if (eax >= 0x80000001) {
721                         cpuid(0x80000001, &eax, &ebx, &ecx, &edx);
722 
723                         c->x86_capability[CPUID_8000_0001_ECX] = ecx;
724                         c->x86_capability[CPUID_8000_0001_EDX] = edx;
725                 }
726         }
727 
728         if (c->extended_cpuid_level >= 0x80000007) {
729                 cpuid(0x80000007, &eax, &ebx, &ecx, &edx);
730 
731                 c->x86_capability[CPUID_8000_0007_EBX] = ebx;
732                 c->x86_power = edx;
733         }
734 
735         if (c->extended_cpuid_level >= 0x80000008) {
736                 cpuid(0x80000008, &eax, &ebx, &ecx, &edx);
737 
738                 c->x86_virt_bits = (eax >> 8) & 0xff;
739                 c->x86_phys_bits = eax & 0xff;
740                 c->x86_capability[CPUID_8000_0008_EBX] = ebx;
741         }
742 #ifdef CONFIG_X86_32
743         else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
744                 c->x86_phys_bits = 36;
745 #endif
746 
747         if (c->extended_cpuid_level >= 0x8000000a)
748                 c->x86_capability[CPUID_8000_000A_EDX] = cpuid_edx(0x8000000a);
749 
750         init_scattered_cpuid_features(c);
751 }
752 
753 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
754 {
755 #ifdef CONFIG_X86_32
756         int i;
757 
758         /*
759          * First of all, decide if this is a 486 or higher
760          * It's a 486 if we can modify the AC flag
761          */
762         if (flag_is_changeable_p(X86_EFLAGS_AC))
763                 c->x86 = 4;
764         else
765                 c->x86 = 3;
766 
767         for (i = 0; i < X86_VENDOR_NUM; i++)
768                 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
769                         c->x86_vendor_id[0] = 0;
770                         cpu_devs[i]->c_identify(c);
771                         if (c->x86_vendor_id[0]) {
772                                 get_cpu_vendor(c);
773                                 break;
774                         }
775                 }
776 #endif
777 }
778 
779 /*
780  * Do minimum CPU detection early.
781  * Fields really needed: vendor, cpuid_level, family, model, mask,
782  * cache alignment.
783  * The others are not touched to avoid unwanted side effects.
784  *
785  * WARNING: this function is only called on the BP.  Don't add code here
786  * that is supposed to run on all CPUs.
787  */
788 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
789 {
790 #ifdef CONFIG_X86_64
791         c->x86_clflush_size = 64;
792         c->x86_phys_bits = 36;
793         c->x86_virt_bits = 48;
794 #else
795         c->x86_clflush_size = 32;
796         c->x86_phys_bits = 32;
797         c->x86_virt_bits = 32;
798 #endif
799         c->x86_cache_alignment = c->x86_clflush_size;
800 
801         memset(&c->x86_capability, 0, sizeof c->x86_capability);
802         c->extended_cpuid_level = 0;
803 
804         if (!have_cpuid_p())
805                 identify_cpu_without_cpuid(c);
806 
807         /* cyrix could have cpuid enabled via c_identify()*/
808         if (have_cpuid_p()) {
809                 cpu_detect(c);
810                 get_cpu_vendor(c);
811                 get_cpu_cap(c);
812 
813                 if (this_cpu->c_early_init)
814                         this_cpu->c_early_init(c);
815 
816                 c->cpu_index = 0;
817                 filter_cpuid_features(c, false);
818 
819                 if (this_cpu->c_bsp_init)
820                         this_cpu->c_bsp_init(c);
821         }
822 
823         setup_force_cpu_cap(X86_FEATURE_ALWAYS);
824         fpu__init_system(c);
825 }
826 
827 void __init early_cpu_init(void)
828 {
829         const struct cpu_dev *const *cdev;
830         int count = 0;
831 
832 #ifdef CONFIG_PROCESSOR_SELECT
833         pr_info("KERNEL supported cpus:\n");
834 #endif
835 
836         for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
837                 const struct cpu_dev *cpudev = *cdev;
838 
839                 if (count >= X86_VENDOR_NUM)
840                         break;
841                 cpu_devs[count] = cpudev;
842                 count++;
843 
844 #ifdef CONFIG_PROCESSOR_SELECT
845                 {
846                         unsigned int j;
847 
848                         for (j = 0; j < 2; j++) {
849                                 if (!cpudev->c_ident[j])
850                                         continue;
851                                 pr_info("  %s %s\n", cpudev->c_vendor,
852                                         cpudev->c_ident[j]);
853                         }
854                 }
855 #endif
856         }
857         early_identify_cpu(&boot_cpu_data);
858 }
859 
860 /*
861  * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
862  * unfortunately, that's not true in practice because of early VIA
863  * chips and (more importantly) broken virtualizers that are not easy
864  * to detect. In the latter case it doesn't even *fail* reliably, so
865  * probing for it doesn't even work. Disable it completely on 32-bit
866  * unless we can find a reliable way to detect all the broken cases.
867  * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
868  */
869 static void detect_nopl(struct cpuinfo_x86 *c)
870 {
871 #ifdef CONFIG_X86_32
872         clear_cpu_cap(c, X86_FEATURE_NOPL);
873 #else
874         set_cpu_cap(c, X86_FEATURE_NOPL);
875 #endif
876 }
877 
878 static void detect_null_seg_behavior(struct cpuinfo_x86 *c)
879 {
880 #ifdef CONFIG_X86_64
881         /*
882          * Empirically, writing zero to a segment selector on AMD does
883          * not clear the base, whereas writing zero to a segment
884          * selector on Intel does clear the base.  Intel's behavior
885          * allows slightly faster context switches in the common case
886          * where GS is unused by the prev and next threads.
887          *
888          * Since neither vendor documents this anywhere that I can see,
889          * detect it directly instead of hardcoding the choice by
890          * vendor.
891          *
892          * I've designated AMD's behavior as the "bug" because it's
893          * counterintuitive and less friendly.
894          */
895 
896         unsigned long old_base, tmp;
897         rdmsrl(MSR_FS_BASE, old_base);
898         wrmsrl(MSR_FS_BASE, 1);
899         loadsegment(fs, 0);
900         rdmsrl(MSR_FS_BASE, tmp);
901         if (tmp != 0)
902                 set_cpu_bug(c, X86_BUG_NULL_SEG);
903         wrmsrl(MSR_FS_BASE, old_base);
904 #endif
905 }
906 
907 static void generic_identify(struct cpuinfo_x86 *c)
908 {
909         c->extended_cpuid_level = 0;
910 
911         if (!have_cpuid_p())
912                 identify_cpu_without_cpuid(c);
913 
914         /* cyrix could have cpuid enabled via c_identify()*/
915         if (!have_cpuid_p())
916                 return;
917 
918         cpu_detect(c);
919 
920         get_cpu_vendor(c);
921 
922         get_cpu_cap(c);
923 
924         if (c->cpuid_level >= 0x00000001) {
925                 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
926 #ifdef CONFIG_X86_32
927 # ifdef CONFIG_SMP
928                 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
929 # else
930                 c->apicid = c->initial_apicid;
931 # endif
932 #endif
933                 c->phys_proc_id = c->initial_apicid;
934         }
935 
936         get_model_name(c); /* Default name */
937 
938         detect_nopl(c);
939 
940         detect_null_seg_behavior(c);
941 
942         /*
943          * ESPFIX is a strange bug.  All real CPUs have it.  Paravirt
944          * systems that run Linux at CPL > 0 may or may not have the
945          * issue, but, even if they have the issue, there's absolutely
946          * nothing we can do about it because we can't use the real IRET
947          * instruction.
948          *
949          * NB: For the time being, only 32-bit kernels support
950          * X86_BUG_ESPFIX as such.  64-bit kernels directly choose
951          * whether to apply espfix using paravirt hooks.  If any
952          * non-paravirt system ever shows up that does *not* have the
953          * ESPFIX issue, we can change this.
954          */
955 #ifdef CONFIG_X86_32
956 # ifdef CONFIG_PARAVIRT
957         do {
958                 extern void native_iret(void);
959                 if (pv_cpu_ops.iret == native_iret)
960                         set_cpu_bug(c, X86_BUG_ESPFIX);
961         } while (0);
962 # else
963         set_cpu_bug(c, X86_BUG_ESPFIX);
964 # endif
965 #endif
966 }
967 
968 static void x86_init_cache_qos(struct cpuinfo_x86 *c)
969 {
970         /*
971          * The heavy lifting of max_rmid and cache_occ_scale are handled
972          * in get_cpu_cap().  Here we just set the max_rmid for the boot_cpu
973          * in case CQM bits really aren't there in this CPU.
974          */
975         if (c != &boot_cpu_data) {
976                 boot_cpu_data.x86_cache_max_rmid =
977                         min(boot_cpu_data.x86_cache_max_rmid,
978                             c->x86_cache_max_rmid);
979         }
980 }
981 
982 /*
983  * Validate that ACPI/mptables have the same information about the
984  * effective APIC id and update the package map.
985  */
986 static void validate_apic_and_package_id(struct cpuinfo_x86 *c)
987 {
988 #ifdef CONFIG_SMP
989         unsigned int apicid, cpu = smp_processor_id();
990 
991         apicid = apic->cpu_present_to_apicid(cpu);
992 
993         if (apicid != c->apicid) {
994                 pr_err(FW_BUG "CPU%u: APIC id mismatch. Firmware: %x APIC: %x\n",
995                        cpu, apicid, c->initial_apicid);
996         }
997         BUG_ON(topology_update_package_map(c->phys_proc_id, cpu));
998 #else
999         c->logical_proc_id = 0;
1000 #endif
1001 }
1002 
1003 /*
1004  * This does the hard work of actually picking apart the CPU stuff...
1005  */
1006 static void identify_cpu(struct cpuinfo_x86 *c)
1007 {
1008         int i;
1009 
1010         c->loops_per_jiffy = loops_per_jiffy;
1011         c->x86_cache_size = -1;
1012         c->x86_vendor = X86_VENDOR_UNKNOWN;
1013         c->x86_model = c->x86_mask = 0; /* So far unknown... */
1014         c->x86_vendor_id[0] = '\0'; /* Unset */
1015         c->x86_model_id[0] = '\0';  /* Unset */
1016         c->x86_max_cores = 1;
1017         c->x86_coreid_bits = 0;
1018         c->cu_id = 0xff;
1019 #ifdef CONFIG_X86_64
1020         c->x86_clflush_size = 64;
1021         c->x86_phys_bits = 36;
1022         c->x86_virt_bits = 48;
1023 #else
1024         c->cpuid_level = -1;    /* CPUID not detected */
1025         c->x86_clflush_size = 32;
1026         c->x86_phys_bits = 32;
1027         c->x86_virt_bits = 32;
1028 #endif
1029         c->x86_cache_alignment = c->x86_clflush_size;
1030         memset(&c->x86_capability, 0, sizeof c->x86_capability);
1031 
1032         generic_identify(c);
1033 
1034         if (this_cpu->c_identify)
1035                 this_cpu->c_identify(c);
1036 
1037         /* Clear/Set all flags overridden by options, after probe */
1038         for (i = 0; i < NCAPINTS; i++) {
1039                 c->x86_capability[i] &= ~cpu_caps_cleared[i];
1040                 c->x86_capability[i] |= cpu_caps_set[i];
1041         }
1042 
1043 #ifdef CONFIG_X86_64
1044         c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
1045 #endif
1046 
1047         /*
1048          * Vendor-specific initialization.  In this section we
1049          * canonicalize the feature flags, meaning if there are
1050          * features a certain CPU supports which CPUID doesn't
1051          * tell us, CPUID claiming incorrect flags, or other bugs,
1052          * we handle them here.
1053          *
1054          * At the end of this section, c->x86_capability better
1055          * indicate the features this CPU genuinely supports!
1056          */
1057         if (this_cpu->c_init)
1058                 this_cpu->c_init(c);
1059 
1060         /* Disable the PN if appropriate */
1061         squash_the_stupid_serial_number(c);
1062 
1063         /* Set up SMEP/SMAP */
1064         setup_smep(c);
1065         setup_smap(c);
1066 
1067         /*
1068          * The vendor-specific functions might have changed features.
1069          * Now we do "generic changes."
1070          */
1071 
1072         /* Filter out anything that depends on CPUID levels we don't have */
1073         filter_cpuid_features(c, true);
1074 
1075         /* If the model name is still unset, do table lookup. */
1076         if (!c->x86_model_id[0]) {
1077                 const char *p;
1078                 p = table_lookup_model(c);
1079                 if (p)
1080                         strcpy(c->x86_model_id, p);
1081                 else
1082                         /* Last resort... */
1083                         sprintf(c->x86_model_id, "%02x/%02x",
1084                                 c->x86, c->x86_model);
1085         }
1086 
1087 #ifdef CONFIG_X86_64
1088         detect_ht(c);
1089 #endif
1090 
1091         init_hypervisor(c);
1092         x86_init_rdrand(c);
1093         x86_init_cache_qos(c);
1094         setup_pku(c);
1095 
1096         /*
1097          * Clear/Set all flags overridden by options, need do it
1098          * before following smp all cpus cap AND.
1099          */
1100         for (i = 0; i < NCAPINTS; i++) {
1101                 c->x86_capability[i] &= ~cpu_caps_cleared[i];
1102                 c->x86_capability[i] |= cpu_caps_set[i];
1103         }
1104 
1105         /*
1106          * On SMP, boot_cpu_data holds the common feature set between
1107          * all CPUs; so make sure that we indicate which features are
1108          * common between the CPUs.  The first time this routine gets
1109          * executed, c == &boot_cpu_data.
1110          */
1111         if (c != &boot_cpu_data) {
1112                 /* AND the already accumulated flags with these */
1113                 for (i = 0; i < NCAPINTS; i++)
1114                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
1115 
1116                 /* OR, i.e. replicate the bug flags */
1117                 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
1118                         c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
1119         }
1120 
1121         /* Init Machine Check Exception if available. */
1122         mcheck_cpu_init(c);
1123 
1124         select_idle_routine(c);
1125 
1126 #ifdef CONFIG_NUMA
1127         numa_add_cpu(smp_processor_id());
1128 #endif
1129 }
1130 
1131 /*
1132  * Set up the CPU state needed to execute SYSENTER/SYSEXIT instructions
1133  * on 32-bit kernels:
1134  */
1135 #ifdef CONFIG_X86_32
1136 void enable_sep_cpu(void)
1137 {
1138         struct tss_struct *tss;
1139         int cpu;
1140 
1141         if (!boot_cpu_has(X86_FEATURE_SEP))
1142                 return;
1143 
1144         cpu = get_cpu();
1145         tss = &per_cpu(cpu_tss, cpu);
1146 
1147         /*
1148          * We cache MSR_IA32_SYSENTER_CS's value in the TSS's ss1 field --
1149          * see the big comment in struct x86_hw_tss's definition.
1150          */
1151 
1152         tss->x86_tss.ss1 = __KERNEL_CS;
1153         wrmsr(MSR_IA32_SYSENTER_CS, tss->x86_tss.ss1, 0);
1154 
1155         wrmsr(MSR_IA32_SYSENTER_ESP,
1156               (unsigned long)tss + offsetofend(struct tss_struct, SYSENTER_stack),
1157               0);
1158 
1159         wrmsr(MSR_IA32_SYSENTER_EIP, (unsigned long)entry_SYSENTER_32, 0);
1160 
1161         put_cpu();
1162 }
1163 #endif
1164 
1165 void __init identify_boot_cpu(void)
1166 {
1167         identify_cpu(&boot_cpu_data);
1168 #ifdef CONFIG_X86_32
1169         sysenter_setup();
1170         enable_sep_cpu();
1171 #endif
1172         cpu_detect_tlb(&boot_cpu_data);
1173 }
1174 
1175 void identify_secondary_cpu(struct cpuinfo_x86 *c)
1176 {
1177         BUG_ON(c == &boot_cpu_data);
1178         identify_cpu(c);
1179 #ifdef CONFIG_X86_32
1180         enable_sep_cpu();
1181 #endif
1182         mtrr_ap_init();
1183         validate_apic_and_package_id(c);
1184 }
1185 
1186 static __init int setup_noclflush(char *arg)
1187 {
1188         setup_clear_cpu_cap(X86_FEATURE_CLFLUSH);
1189         setup_clear_cpu_cap(X86_FEATURE_CLFLUSHOPT);
1190         return 1;
1191 }
1192 __setup("noclflush", setup_noclflush);
1193 
1194 void print_cpu_info(struct cpuinfo_x86 *c)
1195 {
1196         const char *vendor = NULL;
1197 
1198         if (c->x86_vendor < X86_VENDOR_NUM) {
1199                 vendor = this_cpu->c_vendor;
1200         } else {
1201                 if (c->cpuid_level >= 0)
1202                         vendor = c->x86_vendor_id;
1203         }
1204 
1205         if (vendor && !strstr(c->x86_model_id, vendor))
1206                 pr_cont("%s ", vendor);
1207 
1208         if (c->x86_model_id[0])
1209                 pr_cont("%s", c->x86_model_id);
1210         else
1211                 pr_cont("%d86", c->x86);
1212 
1213         pr_cont(" (family: 0x%x, model: 0x%x", c->x86, c->x86_model);
1214 
1215         if (c->x86_mask || c->cpuid_level >= 0)
1216                 pr_cont(", stepping: 0x%x)\n", c->x86_mask);
1217         else
1218                 pr_cont(")\n");
1219 }
1220 
1221 static __init int setup_disablecpuid(char *arg)
1222 {
1223         int bit;
1224 
1225         if (get_option(&arg, &bit) && bit >= 0 && bit < NCAPINTS * 32)
1226                 setup_clear_cpu_cap(bit);
1227         else
1228                 return 0;
1229 
1230         return 1;
1231 }
1232 __setup("clearcpuid=", setup_disablecpuid);
1233 
1234 #ifdef CONFIG_X86_64
1235 struct desc_ptr idt_descr __ro_after_init = {
1236         .size = NR_VECTORS * 16 - 1,
1237         .address = (unsigned long) idt_table,
1238 };
1239 const struct desc_ptr debug_idt_descr = {
1240         .size = NR_VECTORS * 16 - 1,
1241         .address = (unsigned long) debug_idt_table,
1242 };
1243 
1244 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1245                      irq_stack_union) __aligned(PAGE_SIZE) __visible;
1246 
1247 /*
1248  * The following percpu variables are hot.  Align current_task to
1249  * cacheline size such that they fall in the same cacheline.
1250  */
1251 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1252         &init_task;
1253 EXPORT_PER_CPU_SYMBOL(current_task);
1254 
1255 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1256         init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE;
1257 
1258 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1259 
1260 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1261 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1262 
1263 /*
1264  * Special IST stacks which the CPU switches to when it calls
1265  * an IST-marked descriptor entry. Up to 7 stacks (hardware
1266  * limit), all of them are 4K, except the debug stack which
1267  * is 8K.
1268  */
1269 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1270           [0 ... N_EXCEPTION_STACKS - 1]        = EXCEPTION_STKSZ,
1271           [DEBUG_STACK - 1]                     = DEBUG_STKSZ
1272 };
1273 
1274 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1275         [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1276 
1277 /* May not be marked __init: used by software suspend */
1278 void syscall_init(void)
1279 {
1280         wrmsr(MSR_STAR, 0, (__USER32_CS << 16) | __KERNEL_CS);
1281         wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
1282 
1283 #ifdef CONFIG_IA32_EMULATION
1284         wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
1285         /*
1286          * This only works on Intel CPUs.
1287          * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
1288          * This does not cause SYSENTER to jump to the wrong location, because
1289          * AMD doesn't allow SYSENTER in long mode (either 32- or 64-bit).
1290          */
1291         wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)__KERNEL_CS);
1292         wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1293         wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
1294 #else
1295         wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
1296         wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
1297         wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
1298         wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
1299 #endif
1300 
1301         /* Flags to clear on syscall */
1302         wrmsrl(MSR_SYSCALL_MASK,
1303                X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1304                X86_EFLAGS_IOPL|X86_EFLAGS_AC|X86_EFLAGS_NT);
1305 }
1306 
1307 /*
1308  * Copies of the original ist values from the tss are only accessed during
1309  * debugging, no special alignment required.
1310  */
1311 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1312 
1313 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1314 DEFINE_PER_CPU(int, debug_stack_usage);
1315 
1316 int is_debug_stack(unsigned long addr)
1317 {
1318         return __this_cpu_read(debug_stack_usage) ||
1319                 (addr <= __this_cpu_read(debug_stack_addr) &&
1320                  addr > (__this_cpu_read(debug_stack_addr) - DEBUG_STKSZ));
1321 }
1322 NOKPROBE_SYMBOL(is_debug_stack);
1323 
1324 DEFINE_PER_CPU(u32, debug_idt_ctr);
1325 
1326 void debug_stack_set_zero(void)
1327 {
1328         this_cpu_inc(debug_idt_ctr);
1329         load_current_idt();
1330 }
1331 NOKPROBE_SYMBOL(debug_stack_set_zero);
1332 
1333 void debug_stack_reset(void)
1334 {
1335         if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1336                 return;
1337         if (this_cpu_dec_return(debug_idt_ctr) == 0)
1338                 load_current_idt();
1339 }
1340 NOKPROBE_SYMBOL(debug_stack_reset);
1341 
1342 #else   /* CONFIG_X86_64 */
1343 
1344 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1345 EXPORT_PER_CPU_SYMBOL(current_task);
1346 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1347 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1348 
1349 /*
1350  * On x86_32, vm86 modifies tss.sp0, so sp0 isn't a reliable way to find
1351  * the top of the kernel stack.  Use an extra percpu variable to track the
1352  * top of the kernel stack directly.
1353  */
1354 DEFINE_PER_CPU(unsigned long, cpu_current_top_of_stack) =
1355         (unsigned long)&init_thread_union + THREAD_SIZE;
1356 EXPORT_PER_CPU_SYMBOL(cpu_current_top_of_stack);
1357 
1358 #ifdef CONFIG_CC_STACKPROTECTOR
1359 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1360 #endif
1361 
1362 #endif  /* CONFIG_X86_64 */
1363 
1364 /*
1365  * Clear all 6 debug registers:
1366  */
1367 static void clear_all_debug_regs(void)
1368 {
1369         int i;
1370 
1371         for (i = 0; i < 8; i++) {
1372                 /* Ignore db4, db5 */
1373                 if ((i == 4) || (i == 5))
1374                         continue;
1375 
1376                 set_debugreg(0, i);
1377         }
1378 }
1379 
1380 #ifdef CONFIG_KGDB
1381 /*
1382  * Restore debug regs if using kgdbwait and you have a kernel debugger
1383  * connection established.
1384  */
1385 static void dbg_restore_debug_regs(void)
1386 {
1387         if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1388                 arch_kgdb_ops.correct_hw_break();
1389 }
1390 #else /* ! CONFIG_KGDB */
1391 #define dbg_restore_debug_regs()
1392 #endif /* ! CONFIG_KGDB */
1393 
1394 static void wait_for_master_cpu(int cpu)
1395 {
1396 #ifdef CONFIG_SMP
1397         /*
1398          * wait for ACK from master CPU before continuing
1399          * with AP initialization
1400          */
1401         WARN_ON(cpumask_test_and_set_cpu(cpu, cpu_initialized_mask));
1402         while (!cpumask_test_cpu(cpu, cpu_callout_mask))
1403                 cpu_relax();
1404 #endif
1405 }
1406 
1407 /*
1408  * cpu_init() initializes state that is per-CPU. Some data is already
1409  * initialized (naturally) in the bootstrap process, such as the GDT
1410  * and IDT. We reload them nevertheless, this function acts as a
1411  * 'CPU state barrier', nothing should get across.
1412  * A lot of state is already set up in PDA init for 64 bit
1413  */
1414 #ifdef CONFIG_X86_64
1415 
1416 void cpu_init(void)
1417 {
1418         struct orig_ist *oist;
1419         struct task_struct *me;
1420         struct tss_struct *t;
1421         unsigned long v;
1422         int cpu = raw_smp_processor_id();
1423         int i;
1424 
1425         wait_for_master_cpu(cpu);
1426 
1427         /*
1428          * Initialize the CR4 shadow before doing anything that could
1429          * try to read it.
1430          */
1431         cr4_init_shadow();
1432 
1433         if (cpu)
1434                 load_ucode_ap();
1435 
1436         t = &per_cpu(cpu_tss, cpu);
1437         oist = &per_cpu(orig_ist, cpu);
1438 
1439 #ifdef CONFIG_NUMA
1440         if (this_cpu_read(numa_node) == 0 &&
1441             early_cpu_to_node(cpu) != NUMA_NO_NODE)
1442                 set_numa_node(early_cpu_to_node(cpu));
1443 #endif
1444 
1445         me = current;
1446 
1447         pr_debug("Initializing CPU#%d\n", cpu);
1448 
1449         cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1450 
1451         /*
1452          * Initialize the per-CPU GDT with the boot GDT,
1453          * and set up the GDT descriptor:
1454          */
1455 
1456         switch_to_new_gdt(cpu);
1457         loadsegment(fs, 0);
1458 
1459         load_current_idt();
1460 
1461         memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1462         syscall_init();
1463 
1464         wrmsrl(MSR_FS_BASE, 0);
1465         wrmsrl(MSR_KERNEL_GS_BASE, 0);
1466         barrier();
1467 
1468         x86_configure_nx();
1469         x2apic_setup();
1470 
1471         /*
1472          * set up and load the per-CPU TSS
1473          */
1474         if (!oist->ist[0]) {
1475                 char *estacks = per_cpu(exception_stacks, cpu);
1476 
1477                 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1478                         estacks += exception_stack_sizes[v];
1479                         oist->ist[v] = t->x86_tss.ist[v] =
1480                                         (unsigned long)estacks;
1481                         if (v == DEBUG_STACK-1)
1482                                 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1483                 }
1484         }
1485 
1486         t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1487 
1488         /*
1489          * <= is required because the CPU will access up to
1490          * 8 bits beyond the end of the IO permission bitmap.
1491          */
1492         for (i = 0; i <= IO_BITMAP_LONGS; i++)
1493                 t->io_bitmap[i] = ~0UL;
1494 
1495         atomic_inc(&init_mm.mm_count);
1496         me->active_mm = &init_mm;
1497         BUG_ON(me->mm);
1498         enter_lazy_tlb(&init_mm, me);
1499 
1500         load_sp0(t, &current->thread);
1501         set_tss_desc(cpu, t);
1502         load_TR_desc();
1503         load_mm_ldt(&init_mm);
1504 
1505         clear_all_debug_regs();
1506         dbg_restore_debug_regs();
1507 
1508         fpu__init_cpu();
1509 
1510         if (is_uv_system())
1511                 uv_cpu_init();
1512 }
1513 
1514 #else
1515 
1516 void cpu_init(void)
1517 {
1518         int cpu = smp_processor_id();
1519         struct task_struct *curr = current;
1520         struct tss_struct *t = &per_cpu(cpu_tss, cpu);
1521         struct thread_struct *thread = &curr->thread;
1522 
1523         wait_for_master_cpu(cpu);
1524 
1525         /*
1526          * Initialize the CR4 shadow before doing anything that could
1527          * try to read it.
1528          */
1529         cr4_init_shadow();
1530 
1531         show_ucode_info_early();
1532 
1533         pr_info("Initializing CPU#%d\n", cpu);
1534 
1535         if (cpu_feature_enabled(X86_FEATURE_VME) ||
1536             boot_cpu_has(X86_FEATURE_TSC) ||
1537             boot_cpu_has(X86_FEATURE_DE))
1538                 cr4_clear_bits(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1539 
1540         load_current_idt();
1541         switch_to_new_gdt(cpu);
1542 
1543         /*
1544          * Set up and load the per-CPU TSS and LDT
1545          */
1546         atomic_inc(&init_mm.mm_count);
1547         curr->active_mm = &init_mm;
1548         BUG_ON(curr->mm);
1549         enter_lazy_tlb(&init_mm, curr);
1550 
1551         load_sp0(t, thread);
1552         set_tss_desc(cpu, t);
1553         load_TR_desc();
1554         load_mm_ldt(&init_mm);
1555 
1556         t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1557 
1558 #ifdef CONFIG_DOUBLEFAULT
1559         /* Set up doublefault TSS pointer in the GDT */
1560         __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1561 #endif
1562 
1563         clear_all_debug_regs();
1564         dbg_restore_debug_regs();
1565 
1566         fpu__init_cpu();
1567 }
1568 #endif
1569 
1570 static void bsp_resume(void)
1571 {
1572         if (this_cpu->c_bsp_resume)
1573                 this_cpu->c_bsp_resume(&boot_cpu_data);
1574 }
1575 
1576 static struct syscore_ops cpu_syscore_ops = {
1577         .resume         = bsp_resume,
1578 };
1579 
1580 static int __init init_cpu_syscore(void)
1581 {
1582         register_syscore_ops(&cpu_syscore_ops);
1583         return 0;
1584 }
1585 core_initcall(init_cpu_syscore);
1586 

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