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Linux/arch/x86/kernel/cpu/common.c

  1 #include <linux/bootmem.h>
  2 #include <linux/linkage.h>
  3 #include <linux/bitops.h>
  4 #include <linux/kernel.h>
  5 #include <linux/module.h>
  6 #include <linux/percpu.h>
  7 #include <linux/string.h>
  8 #include <linux/delay.h>
  9 #include <linux/sched.h>
 10 #include <linux/init.h>
 11 #include <linux/kgdb.h>
 12 #include <linux/smp.h>
 13 #include <linux/io.h>
 14 
 15 #include <asm/stackprotector.h>
 16 #include <asm/perf_event.h>
 17 #include <asm/mmu_context.h>
 18 #include <asm/archrandom.h>
 19 #include <asm/hypervisor.h>
 20 #include <asm/processor.h>
 21 #include <asm/debugreg.h>
 22 #include <asm/sections.h>
 23 #include <linux/topology.h>
 24 #include <linux/cpumask.h>
 25 #include <asm/pgtable.h>
 26 #include <linux/atomic.h>
 27 #include <asm/proto.h>
 28 #include <asm/setup.h>
 29 #include <asm/apic.h>
 30 #include <asm/desc.h>
 31 #include <asm/i387.h>
 32 #include <asm/fpu-internal.h>
 33 #include <asm/mtrr.h>
 34 #include <linux/numa.h>
 35 #include <asm/asm.h>
 36 #include <asm/cpu.h>
 37 #include <asm/mce.h>
 38 #include <asm/msr.h>
 39 #include <asm/pat.h>
 40 #include <asm/microcode.h>
 41 #include <asm/microcode_intel.h>
 42 
 43 #ifdef CONFIG_X86_LOCAL_APIC
 44 #include <asm/uv/uv.h>
 45 #endif
 46 
 47 #include "cpu.h"
 48 
 49 /* all of these masks are initialized in setup_cpu_local_masks() */
 50 cpumask_var_t cpu_initialized_mask;
 51 cpumask_var_t cpu_callout_mask;
 52 cpumask_var_t cpu_callin_mask;
 53 
 54 /* representing cpus for which sibling maps can be computed */
 55 cpumask_var_t cpu_sibling_setup_mask;
 56 
 57 /* correctly size the local cpu masks */
 58 void __init setup_cpu_local_masks(void)
 59 {
 60         alloc_bootmem_cpumask_var(&cpu_initialized_mask);
 61         alloc_bootmem_cpumask_var(&cpu_callin_mask);
 62         alloc_bootmem_cpumask_var(&cpu_callout_mask);
 63         alloc_bootmem_cpumask_var(&cpu_sibling_setup_mask);
 64 }
 65 
 66 static void default_init(struct cpuinfo_x86 *c)
 67 {
 68 #ifdef CONFIG_X86_64
 69         cpu_detect_cache_sizes(c);
 70 #else
 71         /* Not much we can do here... */
 72         /* Check if at least it has cpuid */
 73         if (c->cpuid_level == -1) {
 74                 /* No cpuid. It must be an ancient CPU */
 75                 if (c->x86 == 4)
 76                         strcpy(c->x86_model_id, "486");
 77                 else if (c->x86 == 3)
 78                         strcpy(c->x86_model_id, "386");
 79         }
 80 #endif
 81 }
 82 
 83 static const struct cpu_dev default_cpu = {
 84         .c_init         = default_init,
 85         .c_vendor       = "Unknown",
 86         .c_x86_vendor   = X86_VENDOR_UNKNOWN,
 87 };
 88 
 89 static const struct cpu_dev *this_cpu = &default_cpu;
 90 
 91 DEFINE_PER_CPU_PAGE_ALIGNED(struct gdt_page, gdt_page) = { .gdt = {
 92 #ifdef CONFIG_X86_64
 93         /*
 94          * We need valid kernel segments for data and code in long mode too
 95          * IRET will check the segment types  kkeil 2000/10/28
 96          * Also sysret mandates a special GDT layout
 97          *
 98          * TLS descriptors are currently at a different place compared to i386.
 99          * Hopefully nobody expects them at a fixed place (Wine?)
100          */
101         [GDT_ENTRY_KERNEL32_CS]         = GDT_ENTRY_INIT(0xc09b, 0, 0xfffff),
102         [GDT_ENTRY_KERNEL_CS]           = GDT_ENTRY_INIT(0xa09b, 0, 0xfffff),
103         [GDT_ENTRY_KERNEL_DS]           = GDT_ENTRY_INIT(0xc093, 0, 0xfffff),
104         [GDT_ENTRY_DEFAULT_USER32_CS]   = GDT_ENTRY_INIT(0xc0fb, 0, 0xfffff),
105         [GDT_ENTRY_DEFAULT_USER_DS]     = GDT_ENTRY_INIT(0xc0f3, 0, 0xfffff),
106         [GDT_ENTRY_DEFAULT_USER_CS]     = GDT_ENTRY_INIT(0xa0fb, 0, 0xfffff),
107 #else
108         [GDT_ENTRY_KERNEL_CS]           = GDT_ENTRY_INIT(0xc09a, 0, 0xfffff),
109         [GDT_ENTRY_KERNEL_DS]           = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
110         [GDT_ENTRY_DEFAULT_USER_CS]     = GDT_ENTRY_INIT(0xc0fa, 0, 0xfffff),
111         [GDT_ENTRY_DEFAULT_USER_DS]     = GDT_ENTRY_INIT(0xc0f2, 0, 0xfffff),
112         /*
113          * Segments used for calling PnP BIOS have byte granularity.
114          * They code segments and data segments have fixed 64k limits,
115          * the transfer segment sizes are set at run time.
116          */
117         /* 32-bit code */
118         [GDT_ENTRY_PNPBIOS_CS32]        = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
119         /* 16-bit code */
120         [GDT_ENTRY_PNPBIOS_CS16]        = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
121         /* 16-bit data */
122         [GDT_ENTRY_PNPBIOS_DS]          = GDT_ENTRY_INIT(0x0092, 0, 0xffff),
123         /* 16-bit data */
124         [GDT_ENTRY_PNPBIOS_TS1]         = GDT_ENTRY_INIT(0x0092, 0, 0),
125         /* 16-bit data */
126         [GDT_ENTRY_PNPBIOS_TS2]         = GDT_ENTRY_INIT(0x0092, 0, 0),
127         /*
128          * The APM segments have byte granularity and their bases
129          * are set at run time.  All have 64k limits.
130          */
131         /* 32-bit code */
132         [GDT_ENTRY_APMBIOS_BASE]        = GDT_ENTRY_INIT(0x409a, 0, 0xffff),
133         /* 16-bit code */
134         [GDT_ENTRY_APMBIOS_BASE+1]      = GDT_ENTRY_INIT(0x009a, 0, 0xffff),
135         /* data */
136         [GDT_ENTRY_APMBIOS_BASE+2]      = GDT_ENTRY_INIT(0x4092, 0, 0xffff),
137 
138         [GDT_ENTRY_ESPFIX_SS]           = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
139         [GDT_ENTRY_PERCPU]              = GDT_ENTRY_INIT(0xc092, 0, 0xfffff),
140         GDT_STACK_CANARY_INIT
141 #endif
142 } };
143 EXPORT_PER_CPU_SYMBOL_GPL(gdt_page);
144 
145 static int __init x86_xsave_setup(char *s)
146 {
147         setup_clear_cpu_cap(X86_FEATURE_XSAVE);
148         setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
149         setup_clear_cpu_cap(X86_FEATURE_AVX);
150         setup_clear_cpu_cap(X86_FEATURE_AVX2);
151         return 1;
152 }
153 __setup("noxsave", x86_xsave_setup);
154 
155 static int __init x86_xsaveopt_setup(char *s)
156 {
157         setup_clear_cpu_cap(X86_FEATURE_XSAVEOPT);
158         return 1;
159 }
160 __setup("noxsaveopt", x86_xsaveopt_setup);
161 
162 #ifdef CONFIG_X86_32
163 static int cachesize_override = -1;
164 static int disable_x86_serial_nr = 1;
165 
166 static int __init cachesize_setup(char *str)
167 {
168         get_option(&str, &cachesize_override);
169         return 1;
170 }
171 __setup("cachesize=", cachesize_setup);
172 
173 static int __init x86_fxsr_setup(char *s)
174 {
175         setup_clear_cpu_cap(X86_FEATURE_FXSR);
176         setup_clear_cpu_cap(X86_FEATURE_XMM);
177         return 1;
178 }
179 __setup("nofxsr", x86_fxsr_setup);
180 
181 static int __init x86_sep_setup(char *s)
182 {
183         setup_clear_cpu_cap(X86_FEATURE_SEP);
184         return 1;
185 }
186 __setup("nosep", x86_sep_setup);
187 
188 /* Standard macro to see if a specific flag is changeable */
189 static inline int flag_is_changeable_p(u32 flag)
190 {
191         u32 f1, f2;
192 
193         /*
194          * Cyrix and IDT cpus allow disabling of CPUID
195          * so the code below may return different results
196          * when it is executed before and after enabling
197          * the CPUID. Add "volatile" to not allow gcc to
198          * optimize the subsequent calls to this function.
199          */
200         asm volatile ("pushfl           \n\t"
201                       "pushfl           \n\t"
202                       "popl %0          \n\t"
203                       "movl %0, %1      \n\t"
204                       "xorl %2, %0      \n\t"
205                       "pushl %0         \n\t"
206                       "popfl            \n\t"
207                       "pushfl           \n\t"
208                       "popl %0          \n\t"
209                       "popfl            \n\t"
210 
211                       : "=&r" (f1), "=&r" (f2)
212                       : "ir" (flag));
213 
214         return ((f1^f2) & flag) != 0;
215 }
216 
217 /* Probe for the CPUID instruction */
218 int have_cpuid_p(void)
219 {
220         return flag_is_changeable_p(X86_EFLAGS_ID);
221 }
222 
223 static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
224 {
225         unsigned long lo, hi;
226 
227         if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr)
228                 return;
229 
230         /* Disable processor serial number: */
231 
232         rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
233         lo |= 0x200000;
234         wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi);
235 
236         printk(KERN_NOTICE "CPU serial number disabled.\n");
237         clear_cpu_cap(c, X86_FEATURE_PN);
238 
239         /* Disabling the serial number may affect the cpuid level */
240         c->cpuid_level = cpuid_eax(0);
241 }
242 
243 static int __init x86_serial_nr_setup(char *s)
244 {
245         disable_x86_serial_nr = 0;
246         return 1;
247 }
248 __setup("serialnumber", x86_serial_nr_setup);
249 #else
250 static inline int flag_is_changeable_p(u32 flag)
251 {
252         return 1;
253 }
254 static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
255 {
256 }
257 #endif
258 
259 static __init int setup_disable_smep(char *arg)
260 {
261         setup_clear_cpu_cap(X86_FEATURE_SMEP);
262         return 1;
263 }
264 __setup("nosmep", setup_disable_smep);
265 
266 static __always_inline void setup_smep(struct cpuinfo_x86 *c)
267 {
268         if (cpu_has(c, X86_FEATURE_SMEP))
269                 set_in_cr4(X86_CR4_SMEP);
270 }
271 
272 static __init int setup_disable_smap(char *arg)
273 {
274         setup_clear_cpu_cap(X86_FEATURE_SMAP);
275         return 1;
276 }
277 __setup("nosmap", setup_disable_smap);
278 
279 static __always_inline void setup_smap(struct cpuinfo_x86 *c)
280 {
281         unsigned long eflags;
282 
283         /* This should have been cleared long ago */
284         raw_local_save_flags(eflags);
285         BUG_ON(eflags & X86_EFLAGS_AC);
286 
287         if (cpu_has(c, X86_FEATURE_SMAP)) {
288 #ifdef CONFIG_X86_SMAP
289                 set_in_cr4(X86_CR4_SMAP);
290 #else
291                 clear_in_cr4(X86_CR4_SMAP);
292 #endif
293         }
294 }
295 
296 /*
297  * Some CPU features depend on higher CPUID levels, which may not always
298  * be available due to CPUID level capping or broken virtualization
299  * software.  Add those features to this table to auto-disable them.
300  */
301 struct cpuid_dependent_feature {
302         u32 feature;
303         u32 level;
304 };
305 
306 static const struct cpuid_dependent_feature
307 cpuid_dependent_features[] = {
308         { X86_FEATURE_MWAIT,            0x00000005 },
309         { X86_FEATURE_DCA,              0x00000009 },
310         { X86_FEATURE_XSAVE,            0x0000000d },
311         { 0, 0 }
312 };
313 
314 static void filter_cpuid_features(struct cpuinfo_x86 *c, bool warn)
315 {
316         const struct cpuid_dependent_feature *df;
317 
318         for (df = cpuid_dependent_features; df->feature; df++) {
319 
320                 if (!cpu_has(c, df->feature))
321                         continue;
322                 /*
323                  * Note: cpuid_level is set to -1 if unavailable, but
324                  * extended_extended_level is set to 0 if unavailable
325                  * and the legitimate extended levels are all negative
326                  * when signed; hence the weird messing around with
327                  * signs here...
328                  */
329                 if (!((s32)df->level < 0 ?
330                      (u32)df->level > (u32)c->extended_cpuid_level :
331                      (s32)df->level > (s32)c->cpuid_level))
332                         continue;
333 
334                 clear_cpu_cap(c, df->feature);
335                 if (!warn)
336                         continue;
337 
338                 printk(KERN_WARNING
339                        "CPU: CPU feature %s disabled, no CPUID level 0x%x\n",
340                                 x86_cap_flags[df->feature], df->level);
341         }
342 }
343 
344 /*
345  * Naming convention should be: <Name> [(<Codename>)]
346  * This table only is used unless init_<vendor>() below doesn't set it;
347  * in particular, if CPUID levels 0x80000002..4 are supported, this
348  * isn't used
349  */
350 
351 /* Look up CPU names by table lookup. */
352 static const char *table_lookup_model(struct cpuinfo_x86 *c)
353 {
354 #ifdef CONFIG_X86_32
355         const struct legacy_cpu_model_info *info;
356 
357         if (c->x86_model >= 16)
358                 return NULL;    /* Range check */
359 
360         if (!this_cpu)
361                 return NULL;
362 
363         info = this_cpu->legacy_models;
364 
365         while (info->family) {
366                 if (info->family == c->x86)
367                         return info->model_names[c->x86_model];
368                 info++;
369         }
370 #endif
371         return NULL;            /* Not found */
372 }
373 
374 __u32 cpu_caps_cleared[NCAPINTS];
375 __u32 cpu_caps_set[NCAPINTS];
376 
377 void load_percpu_segment(int cpu)
378 {
379 #ifdef CONFIG_X86_32
380         loadsegment(fs, __KERNEL_PERCPU);
381 #else
382         loadsegment(gs, 0);
383         wrmsrl(MSR_GS_BASE, (unsigned long)per_cpu(irq_stack_union.gs_base, cpu));
384 #endif
385         load_stack_canary_segment();
386 }
387 
388 /*
389  * Current gdt points %fs at the "master" per-cpu area: after this,
390  * it's on the real one.
391  */
392 void switch_to_new_gdt(int cpu)
393 {
394         struct desc_ptr gdt_descr;
395 
396         gdt_descr.address = (long)get_cpu_gdt_table(cpu);
397         gdt_descr.size = GDT_SIZE - 1;
398         load_gdt(&gdt_descr);
399         /* Reload the per-cpu base */
400 
401         load_percpu_segment(cpu);
402 }
403 
404 static const struct cpu_dev *cpu_devs[X86_VENDOR_NUM] = {};
405 
406 static void get_model_name(struct cpuinfo_x86 *c)
407 {
408         unsigned int *v;
409         char *p, *q;
410 
411         if (c->extended_cpuid_level < 0x80000004)
412                 return;
413 
414         v = (unsigned int *)c->x86_model_id;
415         cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
416         cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
417         cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
418         c->x86_model_id[48] = 0;
419 
420         /*
421          * Intel chips right-justify this string for some dumb reason;
422          * undo that brain damage:
423          */
424         p = q = &c->x86_model_id[0];
425         while (*p == ' ')
426                 p++;
427         if (p != q) {
428                 while (*p)
429                         *q++ = *p++;
430                 while (q <= &c->x86_model_id[48])
431                         *q++ = '\0';    /* Zero-pad the rest */
432         }
433 }
434 
435 void cpu_detect_cache_sizes(struct cpuinfo_x86 *c)
436 {
437         unsigned int n, dummy, ebx, ecx, edx, l2size;
438 
439         n = c->extended_cpuid_level;
440 
441         if (n >= 0x80000005) {
442                 cpuid(0x80000005, &dummy, &ebx, &ecx, &edx);
443                 c->x86_cache_size = (ecx>>24) + (edx>>24);
444 #ifdef CONFIG_X86_64
445                 /* On K8 L1 TLB is inclusive, so don't count it */
446                 c->x86_tlbsize = 0;
447 #endif
448         }
449 
450         if (n < 0x80000006)     /* Some chips just has a large L1. */
451                 return;
452 
453         cpuid(0x80000006, &dummy, &ebx, &ecx, &edx);
454         l2size = ecx >> 16;
455 
456 #ifdef CONFIG_X86_64
457         c->x86_tlbsize += ((ebx >> 16) & 0xfff) + (ebx & 0xfff);
458 #else
459         /* do processor-specific cache resizing */
460         if (this_cpu->legacy_cache_size)
461                 l2size = this_cpu->legacy_cache_size(c, l2size);
462 
463         /* Allow user to override all this if necessary. */
464         if (cachesize_override != -1)
465                 l2size = cachesize_override;
466 
467         if (l2size == 0)
468                 return;         /* Again, no L2 cache is possible */
469 #endif
470 
471         c->x86_cache_size = l2size;
472 }
473 
474 u16 __read_mostly tlb_lli_4k[NR_INFO];
475 u16 __read_mostly tlb_lli_2m[NR_INFO];
476 u16 __read_mostly tlb_lli_4m[NR_INFO];
477 u16 __read_mostly tlb_lld_4k[NR_INFO];
478 u16 __read_mostly tlb_lld_2m[NR_INFO];
479 u16 __read_mostly tlb_lld_4m[NR_INFO];
480 u16 __read_mostly tlb_lld_1g[NR_INFO];
481 
482 /*
483  * tlb_flushall_shift shows the balance point in replacing cr3 write
484  * with multiple 'invlpg'. It will do this replacement when
485  *   flush_tlb_lines <= active_lines/2^tlb_flushall_shift.
486  * If tlb_flushall_shift is -1, means the replacement will be disabled.
487  */
488 s8  __read_mostly tlb_flushall_shift = -1;
489 
490 void cpu_detect_tlb(struct cpuinfo_x86 *c)
491 {
492         if (this_cpu->c_detect_tlb)
493                 this_cpu->c_detect_tlb(c);
494 
495         printk(KERN_INFO "Last level iTLB entries: 4KB %d, 2MB %d, 4MB %d\n"
496                 "Last level dTLB entries: 4KB %d, 2MB %d, 4MB %d, 1GB %d\n"
497                 "tlb_flushall_shift: %d\n",
498                 tlb_lli_4k[ENTRIES], tlb_lli_2m[ENTRIES],
499                 tlb_lli_4m[ENTRIES], tlb_lld_4k[ENTRIES],
500                 tlb_lld_2m[ENTRIES], tlb_lld_4m[ENTRIES],
501                 tlb_lld_1g[ENTRIES], tlb_flushall_shift);
502 }
503 
504 void detect_ht(struct cpuinfo_x86 *c)
505 {
506 #ifdef CONFIG_X86_HT
507         u32 eax, ebx, ecx, edx;
508         int index_msb, core_bits;
509         static bool printed;
510 
511         if (!cpu_has(c, X86_FEATURE_HT))
512                 return;
513 
514         if (cpu_has(c, X86_FEATURE_CMP_LEGACY))
515                 goto out;
516 
517         if (cpu_has(c, X86_FEATURE_XTOPOLOGY))
518                 return;
519 
520         cpuid(1, &eax, &ebx, &ecx, &edx);
521 
522         smp_num_siblings = (ebx & 0xff0000) >> 16;
523 
524         if (smp_num_siblings == 1) {
525                 printk_once(KERN_INFO "CPU0: Hyper-Threading is disabled\n");
526                 goto out;
527         }
528 
529         if (smp_num_siblings <= 1)
530                 goto out;
531 
532         index_msb = get_count_order(smp_num_siblings);
533         c->phys_proc_id = apic->phys_pkg_id(c->initial_apicid, index_msb);
534 
535         smp_num_siblings = smp_num_siblings / c->x86_max_cores;
536 
537         index_msb = get_count_order(smp_num_siblings);
538 
539         core_bits = get_count_order(c->x86_max_cores);
540 
541         c->cpu_core_id = apic->phys_pkg_id(c->initial_apicid, index_msb) &
542                                        ((1 << core_bits) - 1);
543 
544 out:
545         if (!printed && (c->x86_max_cores * smp_num_siblings) > 1) {
546                 printk(KERN_INFO  "CPU: Physical Processor ID: %d\n",
547                        c->phys_proc_id);
548                 printk(KERN_INFO  "CPU: Processor Core ID: %d\n",
549                        c->cpu_core_id);
550                 printed = 1;
551         }
552 #endif
553 }
554 
555 static void get_cpu_vendor(struct cpuinfo_x86 *c)
556 {
557         char *v = c->x86_vendor_id;
558         int i;
559 
560         for (i = 0; i < X86_VENDOR_NUM; i++) {
561                 if (!cpu_devs[i])
562                         break;
563 
564                 if (!strcmp(v, cpu_devs[i]->c_ident[0]) ||
565                     (cpu_devs[i]->c_ident[1] &&
566                      !strcmp(v, cpu_devs[i]->c_ident[1]))) {
567 
568                         this_cpu = cpu_devs[i];
569                         c->x86_vendor = this_cpu->c_x86_vendor;
570                         return;
571                 }
572         }
573 
574         printk_once(KERN_ERR
575                         "CPU: vendor_id '%s' unknown, using generic init.\n" \
576                         "CPU: Your system may be unstable.\n", v);
577 
578         c->x86_vendor = X86_VENDOR_UNKNOWN;
579         this_cpu = &default_cpu;
580 }
581 
582 void cpu_detect(struct cpuinfo_x86 *c)
583 {
584         /* Get vendor name */
585         cpuid(0x00000000, (unsigned int *)&c->cpuid_level,
586               (unsigned int *)&c->x86_vendor_id[0],
587               (unsigned int *)&c->x86_vendor_id[8],
588               (unsigned int *)&c->x86_vendor_id[4]);
589 
590         c->x86 = 4;
591         /* Intel-defined flags: level 0x00000001 */
592         if (c->cpuid_level >= 0x00000001) {
593                 u32 junk, tfms, cap0, misc;
594 
595                 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
596                 c->x86 = (tfms >> 8) & 0xf;
597                 c->x86_model = (tfms >> 4) & 0xf;
598                 c->x86_mask = tfms & 0xf;
599 
600                 if (c->x86 == 0xf)
601                         c->x86 += (tfms >> 20) & 0xff;
602                 if (c->x86 >= 0x6)
603                         c->x86_model += ((tfms >> 16) & 0xf) << 4;
604 
605                 if (cap0 & (1<<19)) {
606                         c->x86_clflush_size = ((misc >> 8) & 0xff) * 8;
607                         c->x86_cache_alignment = c->x86_clflush_size;
608                 }
609         }
610 }
611 
612 void get_cpu_cap(struct cpuinfo_x86 *c)
613 {
614         u32 tfms, xlvl;
615         u32 ebx;
616 
617         /* Intel-defined flags: level 0x00000001 */
618         if (c->cpuid_level >= 0x00000001) {
619                 u32 capability, excap;
620 
621                 cpuid(0x00000001, &tfms, &ebx, &excap, &capability);
622                 c->x86_capability[0] = capability;
623                 c->x86_capability[4] = excap;
624         }
625 
626         /* Additional Intel-defined flags: level 0x00000007 */
627         if (c->cpuid_level >= 0x00000007) {
628                 u32 eax, ebx, ecx, edx;
629 
630                 cpuid_count(0x00000007, 0, &eax, &ebx, &ecx, &edx);
631 
632                 c->x86_capability[9] = ebx;
633         }
634 
635         /* AMD-defined flags: level 0x80000001 */
636         xlvl = cpuid_eax(0x80000000);
637         c->extended_cpuid_level = xlvl;
638 
639         if ((xlvl & 0xffff0000) == 0x80000000) {
640                 if (xlvl >= 0x80000001) {
641                         c->x86_capability[1] = cpuid_edx(0x80000001);
642                         c->x86_capability[6] = cpuid_ecx(0x80000001);
643                 }
644         }
645 
646         if (c->extended_cpuid_level >= 0x80000008) {
647                 u32 eax = cpuid_eax(0x80000008);
648 
649                 c->x86_virt_bits = (eax >> 8) & 0xff;
650                 c->x86_phys_bits = eax & 0xff;
651         }
652 #ifdef CONFIG_X86_32
653         else if (cpu_has(c, X86_FEATURE_PAE) || cpu_has(c, X86_FEATURE_PSE36))
654                 c->x86_phys_bits = 36;
655 #endif
656 
657         if (c->extended_cpuid_level >= 0x80000007)
658                 c->x86_power = cpuid_edx(0x80000007);
659 
660         init_scattered_cpuid_features(c);
661 }
662 
663 static void identify_cpu_without_cpuid(struct cpuinfo_x86 *c)
664 {
665 #ifdef CONFIG_X86_32
666         int i;
667 
668         /*
669          * First of all, decide if this is a 486 or higher
670          * It's a 486 if we can modify the AC flag
671          */
672         if (flag_is_changeable_p(X86_EFLAGS_AC))
673                 c->x86 = 4;
674         else
675                 c->x86 = 3;
676 
677         for (i = 0; i < X86_VENDOR_NUM; i++)
678                 if (cpu_devs[i] && cpu_devs[i]->c_identify) {
679                         c->x86_vendor_id[0] = 0;
680                         cpu_devs[i]->c_identify(c);
681                         if (c->x86_vendor_id[0]) {
682                                 get_cpu_vendor(c);
683                                 break;
684                         }
685                 }
686 #endif
687 }
688 
689 /*
690  * Do minimum CPU detection early.
691  * Fields really needed: vendor, cpuid_level, family, model, mask,
692  * cache alignment.
693  * The others are not touched to avoid unwanted side effects.
694  *
695  * WARNING: this function is only called on the BP.  Don't add code here
696  * that is supposed to run on all CPUs.
697  */
698 static void __init early_identify_cpu(struct cpuinfo_x86 *c)
699 {
700 #ifdef CONFIG_X86_64
701         c->x86_clflush_size = 64;
702         c->x86_phys_bits = 36;
703         c->x86_virt_bits = 48;
704 #else
705         c->x86_clflush_size = 32;
706         c->x86_phys_bits = 32;
707         c->x86_virt_bits = 32;
708 #endif
709         c->x86_cache_alignment = c->x86_clflush_size;
710 
711         memset(&c->x86_capability, 0, sizeof c->x86_capability);
712         c->extended_cpuid_level = 0;
713 
714         if (!have_cpuid_p())
715                 identify_cpu_without_cpuid(c);
716 
717         /* cyrix could have cpuid enabled via c_identify()*/
718         if (!have_cpuid_p())
719                 return;
720 
721         cpu_detect(c);
722         get_cpu_vendor(c);
723         get_cpu_cap(c);
724         fpu_detect(c);
725 
726         if (this_cpu->c_early_init)
727                 this_cpu->c_early_init(c);
728 
729         c->cpu_index = 0;
730         filter_cpuid_features(c, false);
731 
732         if (this_cpu->c_bsp_init)
733                 this_cpu->c_bsp_init(c);
734 
735         setup_force_cpu_cap(X86_FEATURE_ALWAYS);
736 }
737 
738 void __init early_cpu_init(void)
739 {
740         const struct cpu_dev *const *cdev;
741         int count = 0;
742 
743 #ifdef CONFIG_PROCESSOR_SELECT
744         printk(KERN_INFO "KERNEL supported cpus:\n");
745 #endif
746 
747         for (cdev = __x86_cpu_dev_start; cdev < __x86_cpu_dev_end; cdev++) {
748                 const struct cpu_dev *cpudev = *cdev;
749 
750                 if (count >= X86_VENDOR_NUM)
751                         break;
752                 cpu_devs[count] = cpudev;
753                 count++;
754 
755 #ifdef CONFIG_PROCESSOR_SELECT
756                 {
757                         unsigned int j;
758 
759                         for (j = 0; j < 2; j++) {
760                                 if (!cpudev->c_ident[j])
761                                         continue;
762                                 printk(KERN_INFO "  %s %s\n", cpudev->c_vendor,
763                                         cpudev->c_ident[j]);
764                         }
765                 }
766 #endif
767         }
768         early_identify_cpu(&boot_cpu_data);
769 }
770 
771 /*
772  * The NOPL instruction is supposed to exist on all CPUs of family >= 6;
773  * unfortunately, that's not true in practice because of early VIA
774  * chips and (more importantly) broken virtualizers that are not easy
775  * to detect. In the latter case it doesn't even *fail* reliably, so
776  * probing for it doesn't even work. Disable it completely on 32-bit
777  * unless we can find a reliable way to detect all the broken cases.
778  * Enable it explicitly on 64-bit for non-constant inputs of cpu_has().
779  */
780 static void detect_nopl(struct cpuinfo_x86 *c)
781 {
782 #ifdef CONFIG_X86_32
783         clear_cpu_cap(c, X86_FEATURE_NOPL);
784 #else
785         set_cpu_cap(c, X86_FEATURE_NOPL);
786 #endif
787 }
788 
789 static void generic_identify(struct cpuinfo_x86 *c)
790 {
791         c->extended_cpuid_level = 0;
792 
793         if (!have_cpuid_p())
794                 identify_cpu_without_cpuid(c);
795 
796         /* cyrix could have cpuid enabled via c_identify()*/
797         if (!have_cpuid_p())
798                 return;
799 
800         cpu_detect(c);
801 
802         get_cpu_vendor(c);
803 
804         get_cpu_cap(c);
805 
806         if (c->cpuid_level >= 0x00000001) {
807                 c->initial_apicid = (cpuid_ebx(1) >> 24) & 0xFF;
808 #ifdef CONFIG_X86_32
809 # ifdef CONFIG_X86_HT
810                 c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
811 # else
812                 c->apicid = c->initial_apicid;
813 # endif
814 #endif
815                 c->phys_proc_id = c->initial_apicid;
816         }
817 
818         get_model_name(c); /* Default name */
819 
820         detect_nopl(c);
821 }
822 
823 /*
824  * This does the hard work of actually picking apart the CPU stuff...
825  */
826 static void identify_cpu(struct cpuinfo_x86 *c)
827 {
828         int i;
829 
830         c->loops_per_jiffy = loops_per_jiffy;
831         c->x86_cache_size = -1;
832         c->x86_vendor = X86_VENDOR_UNKNOWN;
833         c->x86_model = c->x86_mask = 0; /* So far unknown... */
834         c->x86_vendor_id[0] = '\0'; /* Unset */
835         c->x86_model_id[0] = '\0';  /* Unset */
836         c->x86_max_cores = 1;
837         c->x86_coreid_bits = 0;
838 #ifdef CONFIG_X86_64
839         c->x86_clflush_size = 64;
840         c->x86_phys_bits = 36;
841         c->x86_virt_bits = 48;
842 #else
843         c->cpuid_level = -1;    /* CPUID not detected */
844         c->x86_clflush_size = 32;
845         c->x86_phys_bits = 32;
846         c->x86_virt_bits = 32;
847 #endif
848         c->x86_cache_alignment = c->x86_clflush_size;
849         memset(&c->x86_capability, 0, sizeof c->x86_capability);
850 
851         generic_identify(c);
852 
853         if (this_cpu->c_identify)
854                 this_cpu->c_identify(c);
855 
856         /* Clear/Set all flags overriden by options, after probe */
857         for (i = 0; i < NCAPINTS; i++) {
858                 c->x86_capability[i] &= ~cpu_caps_cleared[i];
859                 c->x86_capability[i] |= cpu_caps_set[i];
860         }
861 
862 #ifdef CONFIG_X86_64
863         c->apicid = apic->phys_pkg_id(c->initial_apicid, 0);
864 #endif
865 
866         /*
867          * Vendor-specific initialization.  In this section we
868          * canonicalize the feature flags, meaning if there are
869          * features a certain CPU supports which CPUID doesn't
870          * tell us, CPUID claiming incorrect flags, or other bugs,
871          * we handle them here.
872          *
873          * At the end of this section, c->x86_capability better
874          * indicate the features this CPU genuinely supports!
875          */
876         if (this_cpu->c_init)
877                 this_cpu->c_init(c);
878 
879         /* Disable the PN if appropriate */
880         squash_the_stupid_serial_number(c);
881 
882         /* Set up SMEP/SMAP */
883         setup_smep(c);
884         setup_smap(c);
885 
886         /*
887          * The vendor-specific functions might have changed features.
888          * Now we do "generic changes."
889          */
890 
891         /* Filter out anything that depends on CPUID levels we don't have */
892         filter_cpuid_features(c, true);
893 
894         /* If the model name is still unset, do table lookup. */
895         if (!c->x86_model_id[0]) {
896                 const char *p;
897                 p = table_lookup_model(c);
898                 if (p)
899                         strcpy(c->x86_model_id, p);
900                 else
901                         /* Last resort... */
902                         sprintf(c->x86_model_id, "%02x/%02x",
903                                 c->x86, c->x86_model);
904         }
905 
906 #ifdef CONFIG_X86_64
907         detect_ht(c);
908 #endif
909 
910         init_hypervisor(c);
911         x86_init_rdrand(c);
912 
913         /*
914          * Clear/Set all flags overriden by options, need do it
915          * before following smp all cpus cap AND.
916          */
917         for (i = 0; i < NCAPINTS; i++) {
918                 c->x86_capability[i] &= ~cpu_caps_cleared[i];
919                 c->x86_capability[i] |= cpu_caps_set[i];
920         }
921 
922         /*
923          * On SMP, boot_cpu_data holds the common feature set between
924          * all CPUs; so make sure that we indicate which features are
925          * common between the CPUs.  The first time this routine gets
926          * executed, c == &boot_cpu_data.
927          */
928         if (c != &boot_cpu_data) {
929                 /* AND the already accumulated flags with these */
930                 for (i = 0; i < NCAPINTS; i++)
931                         boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
932 
933                 /* OR, i.e. replicate the bug flags */
934                 for (i = NCAPINTS; i < NCAPINTS + NBUGINTS; i++)
935                         c->x86_capability[i] |= boot_cpu_data.x86_capability[i];
936         }
937 
938         /* Init Machine Check Exception if available. */
939         mcheck_cpu_init(c);
940 
941         select_idle_routine(c);
942 
943 #ifdef CONFIG_NUMA
944         numa_add_cpu(smp_processor_id());
945 #endif
946 }
947 
948 #ifdef CONFIG_X86_64
949 static void vgetcpu_set_mode(void)
950 {
951         if (cpu_has(&boot_cpu_data, X86_FEATURE_RDTSCP))
952                 vgetcpu_mode = VGETCPU_RDTSCP;
953         else
954                 vgetcpu_mode = VGETCPU_LSL;
955 }
956 #endif
957 
958 void __init identify_boot_cpu(void)
959 {
960         identify_cpu(&boot_cpu_data);
961         init_amd_e400_c1e_mask();
962 #ifdef CONFIG_X86_32
963         sysenter_setup();
964         enable_sep_cpu();
965 #else
966         vgetcpu_set_mode();
967 #endif
968         cpu_detect_tlb(&boot_cpu_data);
969 }
970 
971 void identify_secondary_cpu(struct cpuinfo_x86 *c)
972 {
973         BUG_ON(c == &boot_cpu_data);
974         identify_cpu(c);
975 #ifdef CONFIG_X86_32
976         enable_sep_cpu();
977 #endif
978         mtrr_ap_init();
979 }
980 
981 struct msr_range {
982         unsigned        min;
983         unsigned        max;
984 };
985 
986 static const struct msr_range msr_range_array[] = {
987         { 0x00000000, 0x00000418},
988         { 0xc0000000, 0xc000040b},
989         { 0xc0010000, 0xc0010142},
990         { 0xc0011000, 0xc001103b},
991 };
992 
993 static void __print_cpu_msr(void)
994 {
995         unsigned index_min, index_max;
996         unsigned index;
997         u64 val;
998         int i;
999 
1000         for (i = 0; i < ARRAY_SIZE(msr_range_array); i++) {
1001                 index_min = msr_range_array[i].min;
1002                 index_max = msr_range_array[i].max;
1003 
1004                 for (index = index_min; index < index_max; index++) {
1005                         if (rdmsrl_safe(index, &val))
1006                                 continue;
1007                         printk(KERN_INFO " MSR%08x: %016llx\n", index, val);
1008                 }
1009         }
1010 }
1011 
1012 static int show_msr;
1013 
1014 static __init int setup_show_msr(char *arg)
1015 {
1016         int num;
1017 
1018         get_option(&arg, &num);
1019 
1020         if (num > 0)
1021                 show_msr = num;
1022         return 1;
1023 }
1024 __setup("show_msr=", setup_show_msr);
1025 
1026 static __init int setup_noclflush(char *arg)
1027 {
1028         setup_clear_cpu_cap(X86_FEATURE_CLFLSH);
1029         return 1;
1030 }
1031 __setup("noclflush", setup_noclflush);
1032 
1033 void print_cpu_info(struct cpuinfo_x86 *c)
1034 {
1035         const char *vendor = NULL;
1036 
1037         if (c->x86_vendor < X86_VENDOR_NUM) {
1038                 vendor = this_cpu->c_vendor;
1039         } else {
1040                 if (c->cpuid_level >= 0)
1041                         vendor = c->x86_vendor_id;
1042         }
1043 
1044         if (vendor && !strstr(c->x86_model_id, vendor))
1045                 printk(KERN_CONT "%s ", vendor);
1046 
1047         if (c->x86_model_id[0])
1048                 printk(KERN_CONT "%s", strim(c->x86_model_id));
1049         else
1050                 printk(KERN_CONT "%d86", c->x86);
1051 
1052         printk(KERN_CONT " (fam: %02x, model: %02x", c->x86, c->x86_model);
1053 
1054         if (c->x86_mask || c->cpuid_level >= 0)
1055                 printk(KERN_CONT ", stepping: %02x)\n", c->x86_mask);
1056         else
1057                 printk(KERN_CONT ")\n");
1058 
1059         print_cpu_msr(c);
1060 }
1061 
1062 void print_cpu_msr(struct cpuinfo_x86 *c)
1063 {
1064         if (c->cpu_index < show_msr)
1065                 __print_cpu_msr();
1066 }
1067 
1068 static __init int setup_disablecpuid(char *arg)
1069 {
1070         int bit;
1071 
1072         if (get_option(&arg, &bit) && bit < NCAPINTS*32)
1073                 setup_clear_cpu_cap(bit);
1074         else
1075                 return 0;
1076 
1077         return 1;
1078 }
1079 __setup("clearcpuid=", setup_disablecpuid);
1080 
1081 #ifdef CONFIG_X86_64
1082 struct desc_ptr idt_descr = { NR_VECTORS * 16 - 1, (unsigned long) idt_table };
1083 struct desc_ptr debug_idt_descr = { NR_VECTORS * 16 - 1,
1084                                     (unsigned long) debug_idt_table };
1085 
1086 DEFINE_PER_CPU_FIRST(union irq_stack_union,
1087                      irq_stack_union) __aligned(PAGE_SIZE) __visible;
1088 
1089 /*
1090  * The following four percpu variables are hot.  Align current_task to
1091  * cacheline size such that all four fall in the same cacheline.
1092  */
1093 DEFINE_PER_CPU(struct task_struct *, current_task) ____cacheline_aligned =
1094         &init_task;
1095 EXPORT_PER_CPU_SYMBOL(current_task);
1096 
1097 DEFINE_PER_CPU(unsigned long, kernel_stack) =
1098         (unsigned long)&init_thread_union - KERNEL_STACK_OFFSET + THREAD_SIZE;
1099 EXPORT_PER_CPU_SYMBOL(kernel_stack);
1100 
1101 DEFINE_PER_CPU(char *, irq_stack_ptr) =
1102         init_per_cpu_var(irq_stack_union.irq_stack) + IRQ_STACK_SIZE - 64;
1103 
1104 DEFINE_PER_CPU(unsigned int, irq_count) __visible = -1;
1105 
1106 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1107 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1108 
1109 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
1110 
1111 /*
1112  * Special IST stacks which the CPU switches to when it calls
1113  * an IST-marked descriptor entry. Up to 7 stacks (hardware
1114  * limit), all of them are 4K, except the debug stack which
1115  * is 8K.
1116  */
1117 static const unsigned int exception_stack_sizes[N_EXCEPTION_STACKS] = {
1118           [0 ... N_EXCEPTION_STACKS - 1]        = EXCEPTION_STKSZ,
1119           [DEBUG_STACK - 1]                     = DEBUG_STKSZ
1120 };
1121 
1122 static DEFINE_PER_CPU_PAGE_ALIGNED(char, exception_stacks
1123         [(N_EXCEPTION_STACKS - 1) * EXCEPTION_STKSZ + DEBUG_STKSZ]);
1124 
1125 /* May not be marked __init: used by software suspend */
1126 void syscall_init(void)
1127 {
1128         /*
1129          * LSTAR and STAR live in a bit strange symbiosis.
1130          * They both write to the same internal register. STAR allows to
1131          * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
1132          */
1133         wrmsrl(MSR_STAR,  ((u64)__USER32_CS)<<48  | ((u64)__KERNEL_CS)<<32);
1134         wrmsrl(MSR_LSTAR, system_call);
1135         wrmsrl(MSR_CSTAR, ignore_sysret);
1136 
1137 #ifdef CONFIG_IA32_EMULATION
1138         syscall32_cpu_init();
1139 #endif
1140 
1141         /* Flags to clear on syscall */
1142         wrmsrl(MSR_SYSCALL_MASK,
1143                X86_EFLAGS_TF|X86_EFLAGS_DF|X86_EFLAGS_IF|
1144                X86_EFLAGS_IOPL|X86_EFLAGS_AC);
1145 }
1146 
1147 /*
1148  * Copies of the original ist values from the tss are only accessed during
1149  * debugging, no special alignment required.
1150  */
1151 DEFINE_PER_CPU(struct orig_ist, orig_ist);
1152 
1153 static DEFINE_PER_CPU(unsigned long, debug_stack_addr);
1154 DEFINE_PER_CPU(int, debug_stack_usage);
1155 
1156 int is_debug_stack(unsigned long addr)
1157 {
1158         return __get_cpu_var(debug_stack_usage) ||
1159                 (addr <= __get_cpu_var(debug_stack_addr) &&
1160                  addr > (__get_cpu_var(debug_stack_addr) - DEBUG_STKSZ));
1161 }
1162 
1163 DEFINE_PER_CPU(u32, debug_idt_ctr);
1164 
1165 void debug_stack_set_zero(void)
1166 {
1167         this_cpu_inc(debug_idt_ctr);
1168         load_current_idt();
1169 }
1170 
1171 void debug_stack_reset(void)
1172 {
1173         if (WARN_ON(!this_cpu_read(debug_idt_ctr)))
1174                 return;
1175         if (this_cpu_dec_return(debug_idt_ctr) == 0)
1176                 load_current_idt();
1177 }
1178 
1179 #else   /* CONFIG_X86_64 */
1180 
1181 DEFINE_PER_CPU(struct task_struct *, current_task) = &init_task;
1182 EXPORT_PER_CPU_SYMBOL(current_task);
1183 DEFINE_PER_CPU(int, __preempt_count) = INIT_PREEMPT_COUNT;
1184 EXPORT_PER_CPU_SYMBOL(__preempt_count);
1185 DEFINE_PER_CPU(struct task_struct *, fpu_owner_task);
1186 
1187 #ifdef CONFIG_CC_STACKPROTECTOR
1188 DEFINE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
1189 #endif
1190 
1191 #endif  /* CONFIG_X86_64 */
1192 
1193 /*
1194  * Clear all 6 debug registers:
1195  */
1196 static void clear_all_debug_regs(void)
1197 {
1198         int i;
1199 
1200         for (i = 0; i < 8; i++) {
1201                 /* Ignore db4, db5 */
1202                 if ((i == 4) || (i == 5))
1203                         continue;
1204 
1205                 set_debugreg(0, i);
1206         }
1207 }
1208 
1209 #ifdef CONFIG_KGDB
1210 /*
1211  * Restore debug regs if using kgdbwait and you have a kernel debugger
1212  * connection established.
1213  */
1214 static void dbg_restore_debug_regs(void)
1215 {
1216         if (unlikely(kgdb_connected && arch_kgdb_ops.correct_hw_break))
1217                 arch_kgdb_ops.correct_hw_break();
1218 }
1219 #else /* ! CONFIG_KGDB */
1220 #define dbg_restore_debug_regs()
1221 #endif /* ! CONFIG_KGDB */
1222 
1223 /*
1224  * cpu_init() initializes state that is per-CPU. Some data is already
1225  * initialized (naturally) in the bootstrap process, such as the GDT
1226  * and IDT. We reload them nevertheless, this function acts as a
1227  * 'CPU state barrier', nothing should get across.
1228  * A lot of state is already set up in PDA init for 64 bit
1229  */
1230 #ifdef CONFIG_X86_64
1231 
1232 void cpu_init(void)
1233 {
1234         struct orig_ist *oist;
1235         struct task_struct *me;
1236         struct tss_struct *t;
1237         unsigned long v;
1238         int cpu;
1239         int i;
1240 
1241         /*
1242          * Load microcode on this cpu if a valid microcode is available.
1243          * This is early microcode loading procedure.
1244          */
1245         load_ucode_ap();
1246 
1247         cpu = stack_smp_processor_id();
1248         t = &per_cpu(init_tss, cpu);
1249         oist = &per_cpu(orig_ist, cpu);
1250 
1251 #ifdef CONFIG_NUMA
1252         if (this_cpu_read(numa_node) == 0 &&
1253             early_cpu_to_node(cpu) != NUMA_NO_NODE)
1254                 set_numa_node(early_cpu_to_node(cpu));
1255 #endif
1256 
1257         me = current;
1258 
1259         if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask))
1260                 panic("CPU#%d already initialized!\n", cpu);
1261 
1262         pr_debug("Initializing CPU#%d\n", cpu);
1263 
1264         clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1265 
1266         /*
1267          * Initialize the per-CPU GDT with the boot GDT,
1268          * and set up the GDT descriptor:
1269          */
1270 
1271         switch_to_new_gdt(cpu);
1272         loadsegment(fs, 0);
1273 
1274         load_current_idt();
1275 
1276         memset(me->thread.tls_array, 0, GDT_ENTRY_TLS_ENTRIES * 8);
1277         syscall_init();
1278 
1279         wrmsrl(MSR_FS_BASE, 0);
1280         wrmsrl(MSR_KERNEL_GS_BASE, 0);
1281         barrier();
1282 
1283         x86_configure_nx();
1284         enable_x2apic();
1285 
1286         /*
1287          * set up and load the per-CPU TSS
1288          */
1289         if (!oist->ist[0]) {
1290                 char *estacks = per_cpu(exception_stacks, cpu);
1291 
1292                 for (v = 0; v < N_EXCEPTION_STACKS; v++) {
1293                         estacks += exception_stack_sizes[v];
1294                         oist->ist[v] = t->x86_tss.ist[v] =
1295                                         (unsigned long)estacks;
1296                         if (v == DEBUG_STACK-1)
1297                                 per_cpu(debug_stack_addr, cpu) = (unsigned long)estacks;
1298                 }
1299         }
1300 
1301         t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1302 
1303         /*
1304          * <= is required because the CPU will access up to
1305          * 8 bits beyond the end of the IO permission bitmap.
1306          */
1307         for (i = 0; i <= IO_BITMAP_LONGS; i++)
1308                 t->io_bitmap[i] = ~0UL;
1309 
1310         atomic_inc(&init_mm.mm_count);
1311         me->active_mm = &init_mm;
1312         BUG_ON(me->mm);
1313         enter_lazy_tlb(&init_mm, me);
1314 
1315         load_sp0(t, &current->thread);
1316         set_tss_desc(cpu, t);
1317         load_TR_desc();
1318         load_LDT(&init_mm.context);
1319 
1320         clear_all_debug_regs();
1321         dbg_restore_debug_regs();
1322 
1323         fpu_init();
1324 
1325         if (is_uv_system())
1326                 uv_cpu_init();
1327 }
1328 
1329 #else
1330 
1331 void cpu_init(void)
1332 {
1333         int cpu = smp_processor_id();
1334         struct task_struct *curr = current;
1335         struct tss_struct *t = &per_cpu(init_tss, cpu);
1336         struct thread_struct *thread = &curr->thread;
1337 
1338         show_ucode_info_early();
1339 
1340         if (cpumask_test_and_set_cpu(cpu, cpu_initialized_mask)) {
1341                 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
1342                 for (;;)
1343                         local_irq_enable();
1344         }
1345 
1346         printk(KERN_INFO "Initializing CPU#%d\n", cpu);
1347 
1348         if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
1349                 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
1350 
1351         load_current_idt();
1352         switch_to_new_gdt(cpu);
1353 
1354         /*
1355          * Set up and load the per-CPU TSS and LDT
1356          */
1357         atomic_inc(&init_mm.mm_count);
1358         curr->active_mm = &init_mm;
1359         BUG_ON(curr->mm);
1360         enter_lazy_tlb(&init_mm, curr);
1361 
1362         load_sp0(t, thread);
1363         set_tss_desc(cpu, t);
1364         load_TR_desc();
1365         load_LDT(&init_mm.context);
1366 
1367         t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
1368 
1369 #ifdef CONFIG_DOUBLEFAULT
1370         /* Set up doublefault TSS pointer in the GDT */
1371         __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
1372 #endif
1373 
1374         clear_all_debug_regs();
1375         dbg_restore_debug_regs();
1376 
1377         fpu_init();
1378 }
1379 #endif
1380 
1381 #ifdef CONFIG_X86_DEBUG_STATIC_CPU_HAS
1382 void warn_pre_alternatives(void)
1383 {
1384         WARN(1, "You're using static_cpu_has before alternatives have run!\n");
1385 }
1386 EXPORT_SYMBOL_GPL(warn_pre_alternatives);
1387 #endif
1388 
1389 inline bool __static_cpu_has_safe(u16 bit)
1390 {
1391         return boot_cpu_has(bit);
1392 }
1393 EXPORT_SYMBOL_GPL(__static_cpu_has_safe);
1394 

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