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Linux/arch/x86/include/asm/processor.h

  1 #ifndef _ASM_X86_PROCESSOR_H
  2 #define _ASM_X86_PROCESSOR_H
  3 
  4 #include <asm/processor-flags.h>
  5 
  6 /* Forward declaration, a strange C thing */
  7 struct task_struct;
  8 struct mm_struct;
  9 
 10 #include <asm/vm86.h>
 11 #include <asm/math_emu.h>
 12 #include <asm/segment.h>
 13 #include <asm/types.h>
 14 #include <asm/sigcontext.h>
 15 #include <asm/current.h>
 16 #include <asm/cpufeature.h>
 17 #include <asm/page.h>
 18 #include <asm/pgtable_types.h>
 19 #include <asm/percpu.h>
 20 #include <asm/msr.h>
 21 #include <asm/desc_defs.h>
 22 #include <asm/nops.h>
 23 #include <asm/special_insns.h>
 24 #include <asm/fpu/types.h>
 25 
 26 #include <linux/personality.h>
 27 #include <linux/cpumask.h>
 28 #include <linux/cache.h>
 29 #include <linux/threads.h>
 30 #include <linux/math64.h>
 31 #include <linux/err.h>
 32 #include <linux/irqflags.h>
 33 
 34 /*
 35  * We handle most unaligned accesses in hardware.  On the other hand
 36  * unaligned DMA can be quite expensive on some Nehalem processors.
 37  *
 38  * Based on this we disable the IP header alignment in network drivers.
 39  */
 40 #define NET_IP_ALIGN    0
 41 
 42 #define HBP_NUM 4
 43 /*
 44  * Default implementation of macro that returns current
 45  * instruction pointer ("program counter").
 46  */
 47 static inline void *current_text_addr(void)
 48 {
 49         void *pc;
 50 
 51         asm volatile("mov $1f, %0; 1:":"=r" (pc));
 52 
 53         return pc;
 54 }
 55 
 56 /*
 57  * These alignment constraints are for performance in the vSMP case,
 58  * but in the task_struct case we must also meet hardware imposed
 59  * alignment requirements of the FPU state:
 60  */
 61 #ifdef CONFIG_X86_VSMP
 62 # define ARCH_MIN_TASKALIGN             (1 << INTERNODE_CACHE_SHIFT)
 63 # define ARCH_MIN_MMSTRUCT_ALIGN        (1 << INTERNODE_CACHE_SHIFT)
 64 #else
 65 # define ARCH_MIN_TASKALIGN             __alignof__(union fpregs_state)
 66 # define ARCH_MIN_MMSTRUCT_ALIGN        0
 67 #endif
 68 
 69 enum tlb_infos {
 70         ENTRIES,
 71         NR_INFO
 72 };
 73 
 74 extern u16 __read_mostly tlb_lli_4k[NR_INFO];
 75 extern u16 __read_mostly tlb_lli_2m[NR_INFO];
 76 extern u16 __read_mostly tlb_lli_4m[NR_INFO];
 77 extern u16 __read_mostly tlb_lld_4k[NR_INFO];
 78 extern u16 __read_mostly tlb_lld_2m[NR_INFO];
 79 extern u16 __read_mostly tlb_lld_4m[NR_INFO];
 80 extern u16 __read_mostly tlb_lld_1g[NR_INFO];
 81 
 82 /*
 83  *  CPU type and hardware bug flags. Kept separately for each CPU.
 84  *  Members of this structure are referenced in head.S, so think twice
 85  *  before touching them. [mj]
 86  */
 87 
 88 struct cpuinfo_x86 {
 89         __u8                    x86;            /* CPU family */
 90         __u8                    x86_vendor;     /* CPU vendor */
 91         __u8                    x86_model;
 92         __u8                    x86_mask;
 93 #ifdef CONFIG_X86_32
 94         char                    wp_works_ok;    /* It doesn't on 386's */
 95 
 96         /* Problems on some 486Dx4's and old 386's: */
 97         char                    rfu;
 98         char                    pad0;
 99         char                    pad1;
100 #else
101         /* Number of 4K pages in DTLB/ITLB combined(in pages): */
102         int                     x86_tlbsize;
103 #endif
104         __u8                    x86_virt_bits;
105         __u8                    x86_phys_bits;
106         /* CPUID returned core id bits: */
107         __u8                    x86_coreid_bits;
108         /* Max extended CPUID function supported: */
109         __u32                   extended_cpuid_level;
110         /* Maximum supported CPUID level, -1=no CPUID: */
111         int                     cpuid_level;
112         __u32                   x86_capability[NCAPINTS + NBUGINTS];
113         char                    x86_vendor_id[16];
114         char                    x86_model_id[64];
115         /* in KB - valid for CPUS which support this call: */
116         int                     x86_cache_size;
117         int                     x86_cache_alignment;    /* In bytes */
118         /* Cache QoS architectural values: */
119         int                     x86_cache_max_rmid;     /* max index */
120         int                     x86_cache_occ_scale;    /* scale to bytes */
121         int                     x86_power;
122         unsigned long           loops_per_jiffy;
123         /* cpuid returned max cores value: */
124         u16                      x86_max_cores;
125         u16                     apicid;
126         u16                     initial_apicid;
127         u16                     x86_clflush_size;
128         /* number of cores as seen by the OS: */
129         u16                     booted_cores;
130         /* Physical processor id: */
131         u16                     phys_proc_id;
132         /* Core id: */
133         u16                     cpu_core_id;
134         /* Compute unit id */
135         u8                      compute_unit_id;
136         /* Index into per_cpu list: */
137         u16                     cpu_index;
138         u32                     microcode;
139 };
140 
141 #define X86_VENDOR_INTEL        0
142 #define X86_VENDOR_CYRIX        1
143 #define X86_VENDOR_AMD          2
144 #define X86_VENDOR_UMC          3
145 #define X86_VENDOR_CENTAUR      5
146 #define X86_VENDOR_TRANSMETA    7
147 #define X86_VENDOR_NSC          8
148 #define X86_VENDOR_NUM          9
149 
150 #define X86_VENDOR_UNKNOWN      0xff
151 
152 /*
153  * capabilities of CPUs
154  */
155 extern struct cpuinfo_x86       boot_cpu_data;
156 extern struct cpuinfo_x86       new_cpu_data;
157 
158 extern struct tss_struct        doublefault_tss;
159 extern __u32                    cpu_caps_cleared[NCAPINTS];
160 extern __u32                    cpu_caps_set[NCAPINTS];
161 
162 #ifdef CONFIG_SMP
163 DECLARE_PER_CPU_READ_MOSTLY(struct cpuinfo_x86, cpu_info);
164 #define cpu_data(cpu)           per_cpu(cpu_info, cpu)
165 #else
166 #define cpu_info                boot_cpu_data
167 #define cpu_data(cpu)           boot_cpu_data
168 #endif
169 
170 extern const struct seq_operations cpuinfo_op;
171 
172 #define cache_line_size()       (boot_cpu_data.x86_cache_alignment)
173 
174 extern void cpu_detect(struct cpuinfo_x86 *c);
175 
176 extern void early_cpu_init(void);
177 extern void identify_boot_cpu(void);
178 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
179 extern void print_cpu_info(struct cpuinfo_x86 *);
180 void print_cpu_msr(struct cpuinfo_x86 *);
181 extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
182 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
183 extern void init_amd_cacheinfo(struct cpuinfo_x86 *c);
184 
185 extern void detect_extended_topology(struct cpuinfo_x86 *c);
186 extern void detect_ht(struct cpuinfo_x86 *c);
187 
188 #ifdef CONFIG_X86_32
189 extern int have_cpuid_p(void);
190 #else
191 static inline int have_cpuid_p(void)
192 {
193         return 1;
194 }
195 #endif
196 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
197                                 unsigned int *ecx, unsigned int *edx)
198 {
199         /* ecx is often an input as well as an output. */
200         asm volatile("cpuid"
201             : "=a" (*eax),
202               "=b" (*ebx),
203               "=c" (*ecx),
204               "=d" (*edx)
205             : "" (*eax), "2" (*ecx)
206             : "memory");
207 }
208 
209 static inline void load_cr3(pgd_t *pgdir)
210 {
211         write_cr3(__pa(pgdir));
212 }
213 
214 #ifdef CONFIG_X86_32
215 /* This is the TSS defined by the hardware. */
216 struct x86_hw_tss {
217         unsigned short          back_link, __blh;
218         unsigned long           sp0;
219         unsigned short          ss0, __ss0h;
220         unsigned long           sp1;
221 
222         /*
223          * We don't use ring 1, so ss1 is a convenient scratch space in
224          * the same cacheline as sp0.  We use ss1 to cache the value in
225          * MSR_IA32_SYSENTER_CS.  When we context switch
226          * MSR_IA32_SYSENTER_CS, we first check if the new value being
227          * written matches ss1, and, if it's not, then we wrmsr the new
228          * value and update ss1.
229          *
230          * The only reason we context switch MSR_IA32_SYSENTER_CS is
231          * that we set it to zero in vm86 tasks to avoid corrupting the
232          * stack if we were to go through the sysenter path from vm86
233          * mode.
234          */
235         unsigned short          ss1;    /* MSR_IA32_SYSENTER_CS */
236 
237         unsigned short          __ss1h;
238         unsigned long           sp2;
239         unsigned short          ss2, __ss2h;
240         unsigned long           __cr3;
241         unsigned long           ip;
242         unsigned long           flags;
243         unsigned long           ax;
244         unsigned long           cx;
245         unsigned long           dx;
246         unsigned long           bx;
247         unsigned long           sp;
248         unsigned long           bp;
249         unsigned long           si;
250         unsigned long           di;
251         unsigned short          es, __esh;
252         unsigned short          cs, __csh;
253         unsigned short          ss, __ssh;
254         unsigned short          ds, __dsh;
255         unsigned short          fs, __fsh;
256         unsigned short          gs, __gsh;
257         unsigned short          ldt, __ldth;
258         unsigned short          trace;
259         unsigned short          io_bitmap_base;
260 
261 } __attribute__((packed));
262 #else
263 struct x86_hw_tss {
264         u32                     reserved1;
265         u64                     sp0;
266         u64                     sp1;
267         u64                     sp2;
268         u64                     reserved2;
269         u64                     ist[7];
270         u32                     reserved3;
271         u32                     reserved4;
272         u16                     reserved5;
273         u16                     io_bitmap_base;
274 
275 } __attribute__((packed)) ____cacheline_aligned;
276 #endif
277 
278 /*
279  * IO-bitmap sizes:
280  */
281 #define IO_BITMAP_BITS                  65536
282 #define IO_BITMAP_BYTES                 (IO_BITMAP_BITS/8)
283 #define IO_BITMAP_LONGS                 (IO_BITMAP_BYTES/sizeof(long))
284 #define IO_BITMAP_OFFSET                offsetof(struct tss_struct, io_bitmap)
285 #define INVALID_IO_BITMAP_OFFSET        0x8000
286 
287 struct tss_struct {
288         /*
289          * The hardware state:
290          */
291         struct x86_hw_tss       x86_tss;
292 
293         /*
294          * The extra 1 is there because the CPU will access an
295          * additional byte beyond the end of the IO permission
296          * bitmap. The extra byte must be all 1 bits, and must
297          * be within the limit.
298          */
299         unsigned long           io_bitmap[IO_BITMAP_LONGS + 1];
300 
301         /*
302          * Space for the temporary SYSENTER stack:
303          */
304         unsigned long           SYSENTER_stack[64];
305 
306 } ____cacheline_aligned;
307 
308 DECLARE_PER_CPU_SHARED_ALIGNED(struct tss_struct, cpu_tss);
309 
310 #ifdef CONFIG_X86_32
311 DECLARE_PER_CPU(unsigned long, cpu_current_top_of_stack);
312 #endif
313 
314 /*
315  * Save the original ist values for checking stack pointers during debugging
316  */
317 struct orig_ist {
318         unsigned long           ist[7];
319 };
320 
321 #ifdef CONFIG_X86_64
322 DECLARE_PER_CPU(struct orig_ist, orig_ist);
323 
324 union irq_stack_union {
325         char irq_stack[IRQ_STACK_SIZE];
326         /*
327          * GCC hardcodes the stack canary as %gs:40.  Since the
328          * irq_stack is the object at %gs:0, we reserve the bottom
329          * 48 bytes of the irq stack for the canary.
330          */
331         struct {
332                 char gs_base[40];
333                 unsigned long stack_canary;
334         };
335 };
336 
337 DECLARE_PER_CPU_FIRST(union irq_stack_union, irq_stack_union) __visible;
338 DECLARE_INIT_PER_CPU(irq_stack_union);
339 
340 DECLARE_PER_CPU(char *, irq_stack_ptr);
341 DECLARE_PER_CPU(unsigned int, irq_count);
342 extern asmlinkage void ignore_sysret(void);
343 #else   /* X86_64 */
344 #ifdef CONFIG_CC_STACKPROTECTOR
345 /*
346  * Make sure stack canary segment base is cached-aligned:
347  *   "For Intel Atom processors, avoid non zero segment base address
348  *    that is not aligned to cache line boundary at all cost."
349  * (Optim Ref Manual Assembly/Compiler Coding Rule 15.)
350  */
351 struct stack_canary {
352         char __pad[20];         /* canary at %gs:20 */
353         unsigned long canary;
354 };
355 DECLARE_PER_CPU_ALIGNED(struct stack_canary, stack_canary);
356 #endif
357 /*
358  * per-CPU IRQ handling stacks
359  */
360 struct irq_stack {
361         u32                     stack[THREAD_SIZE/sizeof(u32)];
362 } __aligned(THREAD_SIZE);
363 
364 DECLARE_PER_CPU(struct irq_stack *, hardirq_stack);
365 DECLARE_PER_CPU(struct irq_stack *, softirq_stack);
366 #endif  /* X86_64 */
367 
368 extern unsigned int xstate_size;
369 
370 struct perf_event;
371 
372 struct thread_struct {
373         /* Cached TLS descriptors: */
374         struct desc_struct      tls_array[GDT_ENTRY_TLS_ENTRIES];
375         unsigned long           sp0;
376         unsigned long           sp;
377 #ifdef CONFIG_X86_32
378         unsigned long           sysenter_cs;
379 #else
380         unsigned short          es;
381         unsigned short          ds;
382         unsigned short          fsindex;
383         unsigned short          gsindex;
384 #endif
385 #ifdef CONFIG_X86_32
386         unsigned long           ip;
387 #endif
388 #ifdef CONFIG_X86_64
389         unsigned long           fs;
390 #endif
391         unsigned long           gs;
392 
393         /* Save middle states of ptrace breakpoints */
394         struct perf_event       *ptrace_bps[HBP_NUM];
395         /* Debug status used for traps, single steps, etc... */
396         unsigned long           debugreg6;
397         /* Keep track of the exact dr7 value set by the user */
398         unsigned long           ptrace_dr7;
399         /* Fault info: */
400         unsigned long           cr2;
401         unsigned long           trap_nr;
402         unsigned long           error_code;
403 #ifdef CONFIG_X86_32
404         /* Virtual 86 mode info */
405         struct vm86_struct __user *vm86_info;
406         unsigned long           screen_bitmap;
407         unsigned long           v86flags;
408         unsigned long           v86mask;
409         unsigned long           saved_sp0;
410         unsigned int            saved_fs;
411         unsigned int            saved_gs;
412 #endif
413         /* IO permissions: */
414         unsigned long           *io_bitmap_ptr;
415         unsigned long           iopl;
416         /* Max allowed port in the bitmap, in bytes: */
417         unsigned                io_bitmap_max;
418 
419         /* Floating point and extended processor state */
420         struct fpu              fpu;
421         /*
422          * WARNING: 'fpu' is dynamically-sized.  It *MUST* be at
423          * the end.
424          */
425 };
426 
427 /*
428  * Set IOPL bits in EFLAGS from given mask
429  */
430 static inline void native_set_iopl_mask(unsigned mask)
431 {
432 #ifdef CONFIG_X86_32
433         unsigned int reg;
434 
435         asm volatile ("pushfl;"
436                       "popl %0;"
437                       "andl %1, %0;"
438                       "orl %2, %0;"
439                       "pushl %0;"
440                       "popfl"
441                       : "=&r" (reg)
442                       : "i" (~X86_EFLAGS_IOPL), "r" (mask));
443 #endif
444 }
445 
446 static inline void
447 native_load_sp0(struct tss_struct *tss, struct thread_struct *thread)
448 {
449         tss->x86_tss.sp0 = thread->sp0;
450 #ifdef CONFIG_X86_32
451         /* Only happens when SEP is enabled, no need to test "SEP"arately: */
452         if (unlikely(tss->x86_tss.ss1 != thread->sysenter_cs)) {
453                 tss->x86_tss.ss1 = thread->sysenter_cs;
454                 wrmsr(MSR_IA32_SYSENTER_CS, thread->sysenter_cs, 0);
455         }
456 #endif
457 }
458 
459 static inline void native_swapgs(void)
460 {
461 #ifdef CONFIG_X86_64
462         asm volatile("swapgs" ::: "memory");
463 #endif
464 }
465 
466 static inline unsigned long current_top_of_stack(void)
467 {
468 #ifdef CONFIG_X86_64
469         return this_cpu_read_stable(cpu_tss.x86_tss.sp0);
470 #else
471         /* sp0 on x86_32 is special in and around vm86 mode. */
472         return this_cpu_read_stable(cpu_current_top_of_stack);
473 #endif
474 }
475 
476 #ifdef CONFIG_PARAVIRT
477 #include <asm/paravirt.h>
478 #else
479 #define __cpuid                 native_cpuid
480 #define paravirt_enabled()      0
481 
482 static inline void load_sp0(struct tss_struct *tss,
483                             struct thread_struct *thread)
484 {
485         native_load_sp0(tss, thread);
486 }
487 
488 #define set_iopl_mask native_set_iopl_mask
489 #endif /* CONFIG_PARAVIRT */
490 
491 typedef struct {
492         unsigned long           seg;
493 } mm_segment_t;
494 
495 
496 /* Free all resources held by a thread. */
497 extern void release_thread(struct task_struct *);
498 
499 unsigned long get_wchan(struct task_struct *p);
500 
501 /*
502  * Generic CPUID function
503  * clear %ecx since some cpus (Cyrix MII) do not set or clear %ecx
504  * resulting in stale register contents being returned.
505  */
506 static inline void cpuid(unsigned int op,
507                          unsigned int *eax, unsigned int *ebx,
508                          unsigned int *ecx, unsigned int *edx)
509 {
510         *eax = op;
511         *ecx = 0;
512         __cpuid(eax, ebx, ecx, edx);
513 }
514 
515 /* Some CPUID calls want 'count' to be placed in ecx */
516 static inline void cpuid_count(unsigned int op, int count,
517                                unsigned int *eax, unsigned int *ebx,
518                                unsigned int *ecx, unsigned int *edx)
519 {
520         *eax = op;
521         *ecx = count;
522         __cpuid(eax, ebx, ecx, edx);
523 }
524 
525 /*
526  * CPUID functions returning a single datum
527  */
528 static inline unsigned int cpuid_eax(unsigned int op)
529 {
530         unsigned int eax, ebx, ecx, edx;
531 
532         cpuid(op, &eax, &ebx, &ecx, &edx);
533 
534         return eax;
535 }
536 
537 static inline unsigned int cpuid_ebx(unsigned int op)
538 {
539         unsigned int eax, ebx, ecx, edx;
540 
541         cpuid(op, &eax, &ebx, &ecx, &edx);
542 
543         return ebx;
544 }
545 
546 static inline unsigned int cpuid_ecx(unsigned int op)
547 {
548         unsigned int eax, ebx, ecx, edx;
549 
550         cpuid(op, &eax, &ebx, &ecx, &edx);
551 
552         return ecx;
553 }
554 
555 static inline unsigned int cpuid_edx(unsigned int op)
556 {
557         unsigned int eax, ebx, ecx, edx;
558 
559         cpuid(op, &eax, &ebx, &ecx, &edx);
560 
561         return edx;
562 }
563 
564 /* REP NOP (PAUSE) is a good thing to insert into busy-wait loops. */
565 static inline void rep_nop(void)
566 {
567         asm volatile("rep; nop" ::: "memory");
568 }
569 
570 static inline void cpu_relax(void)
571 {
572         rep_nop();
573 }
574 
575 #define cpu_relax_lowlatency() cpu_relax()
576 
577 /* Stop speculative execution and prefetching of modified code. */
578 static inline void sync_core(void)
579 {
580         int tmp;
581 
582 #ifdef CONFIG_M486
583         /*
584          * Do a CPUID if available, otherwise do a jump.  The jump
585          * can conveniently enough be the jump around CPUID.
586          */
587         asm volatile("cmpl %2,%1\n\t"
588                      "jl 1f\n\t"
589                      "cpuid\n"
590                      "1:"
591                      : "=a" (tmp)
592                      : "rm" (boot_cpu_data.cpuid_level), "ri" (0), "" (1)
593                      : "ebx", "ecx", "edx", "memory");
594 #else
595         /*
596          * CPUID is a barrier to speculative execution.
597          * Prefetched instructions are automatically
598          * invalidated when modified.
599          */
600         asm volatile("cpuid"
601                      : "=a" (tmp)
602                      : "" (1)
603                      : "ebx", "ecx", "edx", "memory");
604 #endif
605 }
606 
607 extern void select_idle_routine(const struct cpuinfo_x86 *c);
608 extern void init_amd_e400_c1e_mask(void);
609 
610 extern unsigned long            boot_option_idle_override;
611 extern bool                     amd_e400_c1e_detected;
612 
613 enum idle_boot_override {IDLE_NO_OVERRIDE=0, IDLE_HALT, IDLE_NOMWAIT,
614                          IDLE_POLL};
615 
616 extern void enable_sep_cpu(void);
617 extern int sysenter_setup(void);
618 
619 extern void early_trap_init(void);
620 void early_trap_pf_init(void);
621 
622 /* Defined in head.S */
623 extern struct desc_ptr          early_gdt_descr;
624 
625 extern void cpu_set_gdt(int);
626 extern void switch_to_new_gdt(int);
627 extern void load_percpu_segment(int);
628 extern void cpu_init(void);
629 
630 static inline unsigned long get_debugctlmsr(void)
631 {
632         unsigned long debugctlmsr = 0;
633 
634 #ifndef CONFIG_X86_DEBUGCTLMSR
635         if (boot_cpu_data.x86 < 6)
636                 return 0;
637 #endif
638         rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
639 
640         return debugctlmsr;
641 }
642 
643 static inline void update_debugctlmsr(unsigned long debugctlmsr)
644 {
645 #ifndef CONFIG_X86_DEBUGCTLMSR
646         if (boot_cpu_data.x86 < 6)
647                 return;
648 #endif
649         wrmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr);
650 }
651 
652 extern void set_task_blockstep(struct task_struct *task, bool on);
653 
654 /*
655  * from system description table in BIOS. Mostly for MCA use, but
656  * others may find it useful:
657  */
658 extern unsigned int             machine_id;
659 extern unsigned int             machine_submodel_id;
660 extern unsigned int             BIOS_revision;
661 
662 /* Boot loader type from the setup header: */
663 extern int                      bootloader_type;
664 extern int                      bootloader_version;
665 
666 extern char                     ignore_fpu_irq;
667 
668 #define HAVE_ARCH_PICK_MMAP_LAYOUT 1
669 #define ARCH_HAS_PREFETCHW
670 #define ARCH_HAS_SPINLOCK_PREFETCH
671 
672 #ifdef CONFIG_X86_32
673 # define BASE_PREFETCH          ""
674 # define ARCH_HAS_PREFETCH
675 #else
676 # define BASE_PREFETCH          "prefetcht0 %P1"
677 #endif
678 
679 /*
680  * Prefetch instructions for Pentium III (+) and AMD Athlon (+)
681  *
682  * It's not worth to care about 3dnow prefetches for the K6
683  * because they are microcoded there and very slow.
684  */
685 static inline void prefetch(const void *x)
686 {
687         alternative_input(BASE_PREFETCH, "prefetchnta %P1",
688                           X86_FEATURE_XMM,
689                           "m" (*(const char *)x));
690 }
691 
692 /*
693  * 3dnow prefetch to get an exclusive cache line.
694  * Useful for spinlocks to avoid one state transition in the
695  * cache coherency protocol:
696  */
697 static inline void prefetchw(const void *x)
698 {
699         alternative_input(BASE_PREFETCH, "prefetchw %P1",
700                           X86_FEATURE_3DNOWPREFETCH,
701                           "m" (*(const char *)x));
702 }
703 
704 static inline void spin_lock_prefetch(const void *x)
705 {
706         prefetchw(x);
707 }
708 
709 #define TOP_OF_INIT_STACK ((unsigned long)&init_stack + sizeof(init_stack) - \
710                            TOP_OF_KERNEL_STACK_PADDING)
711 
712 #ifdef CONFIG_X86_32
713 /*
714  * User space process size: 3GB (default).
715  */
716 #define TASK_SIZE               PAGE_OFFSET
717 #define TASK_SIZE_MAX           TASK_SIZE
718 #define STACK_TOP               TASK_SIZE
719 #define STACK_TOP_MAX           STACK_TOP
720 
721 #define INIT_THREAD  {                                                    \
722         .sp0                    = TOP_OF_INIT_STACK,                      \
723         .vm86_info              = NULL,                                   \
724         .sysenter_cs            = __KERNEL_CS,                            \
725         .io_bitmap_ptr          = NULL,                                   \
726 }
727 
728 extern unsigned long thread_saved_pc(struct task_struct *tsk);
729 
730 /*
731  * TOP_OF_KERNEL_STACK_PADDING reserves 8 bytes on top of the ring0 stack.
732  * This is necessary to guarantee that the entire "struct pt_regs"
733  * is accessible even if the CPU haven't stored the SS/ESP registers
734  * on the stack (interrupt gate does not save these registers
735  * when switching to the same priv ring).
736  * Therefore beware: accessing the ss/esp fields of the
737  * "struct pt_regs" is possible, but they may contain the
738  * completely wrong values.
739  */
740 #define task_pt_regs(task) \
741 ({                                                                      \
742         unsigned long __ptr = (unsigned long)task_stack_page(task);     \
743         __ptr += THREAD_SIZE - TOP_OF_KERNEL_STACK_PADDING;             \
744         ((struct pt_regs *)__ptr) - 1;                                  \
745 })
746 
747 #define KSTK_ESP(task)          (task_pt_regs(task)->sp)
748 
749 #else
750 /*
751  * User space process size. 47bits minus one guard page.  The guard
752  * page is necessary on Intel CPUs: if a SYSCALL instruction is at
753  * the highest possible canonical userspace address, then that
754  * syscall will enter the kernel with a non-canonical return
755  * address, and SYSRET will explode dangerously.  We avoid this
756  * particular problem by preventing anything from being mapped
757  * at the maximum canonical address.
758  */
759 #define TASK_SIZE_MAX   ((1UL << 47) - PAGE_SIZE)
760 
761 /* This decides where the kernel will search for a free chunk of vm
762  * space during mmap's.
763  */
764 #define IA32_PAGE_OFFSET        ((current->personality & ADDR_LIMIT_3GB) ? \
765                                         0xc0000000 : 0xFFFFe000)
766 
767 #define TASK_SIZE               (test_thread_flag(TIF_ADDR32) ? \
768                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
769 #define TASK_SIZE_OF(child)     ((test_tsk_thread_flag(child, TIF_ADDR32)) ? \
770                                         IA32_PAGE_OFFSET : TASK_SIZE_MAX)
771 
772 #define STACK_TOP               TASK_SIZE
773 #define STACK_TOP_MAX           TASK_SIZE_MAX
774 
775 #define INIT_THREAD  { \
776         .sp0 = TOP_OF_INIT_STACK \
777 }
778 
779 /*
780  * Return saved PC of a blocked thread.
781  * What is this good for? it will be always the scheduler or ret_from_fork.
782  */
783 #define thread_saved_pc(t)      (*(unsigned long *)((t)->thread.sp - 8))
784 
785 #define task_pt_regs(tsk)       ((struct pt_regs *)(tsk)->thread.sp0 - 1)
786 extern unsigned long KSTK_ESP(struct task_struct *task);
787 
788 #endif /* CONFIG_X86_64 */
789 
790 extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
791                                                unsigned long new_sp);
792 
793 /*
794  * This decides where the kernel will search for a free chunk of vm
795  * space during mmap's.
796  */
797 #define TASK_UNMAPPED_BASE      (PAGE_ALIGN(TASK_SIZE / 3))
798 
799 #define KSTK_EIP(task)          (task_pt_regs(task)->ip)
800 
801 /* Get/set a process' ability to use the timestamp counter instruction */
802 #define GET_TSC_CTL(adr)        get_tsc_mode((adr))
803 #define SET_TSC_CTL(val)        set_tsc_mode((val))
804 
805 extern int get_tsc_mode(unsigned long adr);
806 extern int set_tsc_mode(unsigned int val);
807 
808 /* Register/unregister a process' MPX related resource */
809 #define MPX_ENABLE_MANAGEMENT() mpx_enable_management()
810 #define MPX_DISABLE_MANAGEMENT()        mpx_disable_management()
811 
812 #ifdef CONFIG_X86_INTEL_MPX
813 extern int mpx_enable_management(void);
814 extern int mpx_disable_management(void);
815 #else
816 static inline int mpx_enable_management(void)
817 {
818         return -EINVAL;
819 }
820 static inline int mpx_disable_management(void)
821 {
822         return -EINVAL;
823 }
824 #endif /* CONFIG_X86_INTEL_MPX */
825 
826 extern u16 amd_get_nb_id(int cpu);
827 extern u32 amd_get_nodes_per_socket(void);
828 
829 static inline uint32_t hypervisor_cpuid_base(const char *sig, uint32_t leaves)
830 {
831         uint32_t base, eax, signature[3];
832 
833         for (base = 0x40000000; base < 0x40010000; base += 0x100) {
834                 cpuid(base, &eax, &signature[0], &signature[1], &signature[2]);
835 
836                 if (!memcmp(sig, signature, 12) &&
837                     (leaves == 0 || ((eax - base) >= leaves)))
838                         return base;
839         }
840 
841         return 0;
842 }
843 
844 extern unsigned long arch_align_stack(unsigned long sp);
845 extern void free_init_pages(char *what, unsigned long begin, unsigned long end);
846 
847 void default_idle(void);
848 #ifdef  CONFIG_XEN
849 bool xen_set_default_idle(void);
850 #else
851 #define xen_set_default_idle 0
852 #endif
853 
854 void stop_this_cpu(void *dummy);
855 void df_debug(struct pt_regs *regs, long error_code);
856 #endif /* _ASM_X86_PROCESSOR_H */
857 

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