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Linux/arch/powerpc/sysdev/mpic.c

  1 /*
  2  *  arch/powerpc/kernel/mpic.c
  3  *
  4  *  Driver for interrupt controllers following the OpenPIC standard, the
  5  *  common implementation beeing IBM's MPIC. This driver also can deal
  6  *  with various broken implementations of this HW.
  7  *
  8  *  Copyright (C) 2004 Benjamin Herrenschmidt, IBM Corp.
  9  *  Copyright 2010-2012 Freescale Semiconductor, Inc.
 10  *
 11  *  This file is subject to the terms and conditions of the GNU General Public
 12  *  License.  See the file COPYING in the main directory of this archive
 13  *  for more details.
 14  */
 15 
 16 #undef DEBUG
 17 #undef DEBUG_IPI
 18 #undef DEBUG_IRQ
 19 #undef DEBUG_LOW
 20 
 21 #include <linux/types.h>
 22 #include <linux/kernel.h>
 23 #include <linux/init.h>
 24 #include <linux/irq.h>
 25 #include <linux/smp.h>
 26 #include <linux/interrupt.h>
 27 #include <linux/bootmem.h>
 28 #include <linux/spinlock.h>
 29 #include <linux/pci.h>
 30 #include <linux/slab.h>
 31 #include <linux/syscore_ops.h>
 32 #include <linux/ratelimit.h>
 33 
 34 #include <asm/ptrace.h>
 35 #include <asm/signal.h>
 36 #include <asm/io.h>
 37 #include <asm/pgtable.h>
 38 #include <asm/irq.h>
 39 #include <asm/machdep.h>
 40 #include <asm/mpic.h>
 41 #include <asm/smp.h>
 42 
 43 #include "mpic.h"
 44 
 45 #ifdef DEBUG
 46 #define DBG(fmt...) printk(fmt)
 47 #else
 48 #define DBG(fmt...)
 49 #endif
 50 
 51 struct bus_type mpic_subsys = {
 52         .name = "mpic",
 53         .dev_name = "mpic",
 54 };
 55 EXPORT_SYMBOL_GPL(mpic_subsys);
 56 
 57 static struct mpic *mpics;
 58 static struct mpic *mpic_primary;
 59 static DEFINE_RAW_SPINLOCK(mpic_lock);
 60 
 61 #ifdef CONFIG_PPC32     /* XXX for now */
 62 #ifdef CONFIG_IRQ_ALL_CPUS
 63 #define distribute_irqs (1)
 64 #else
 65 #define distribute_irqs (0)
 66 #endif
 67 #endif
 68 
 69 #ifdef CONFIG_MPIC_WEIRD
 70 static u32 mpic_infos[][MPIC_IDX_END] = {
 71         [0] = { /* Original OpenPIC compatible MPIC */
 72                 MPIC_GREG_BASE,
 73                 MPIC_GREG_FEATURE_0,
 74                 MPIC_GREG_GLOBAL_CONF_0,
 75                 MPIC_GREG_VENDOR_ID,
 76                 MPIC_GREG_IPI_VECTOR_PRI_0,
 77                 MPIC_GREG_IPI_STRIDE,
 78                 MPIC_GREG_SPURIOUS,
 79                 MPIC_GREG_TIMER_FREQ,
 80 
 81                 MPIC_TIMER_BASE,
 82                 MPIC_TIMER_STRIDE,
 83                 MPIC_TIMER_CURRENT_CNT,
 84                 MPIC_TIMER_BASE_CNT,
 85                 MPIC_TIMER_VECTOR_PRI,
 86                 MPIC_TIMER_DESTINATION,
 87 
 88                 MPIC_CPU_BASE,
 89                 MPIC_CPU_STRIDE,
 90                 MPIC_CPU_IPI_DISPATCH_0,
 91                 MPIC_CPU_IPI_DISPATCH_STRIDE,
 92                 MPIC_CPU_CURRENT_TASK_PRI,
 93                 MPIC_CPU_WHOAMI,
 94                 MPIC_CPU_INTACK,
 95                 MPIC_CPU_EOI,
 96                 MPIC_CPU_MCACK,
 97 
 98                 MPIC_IRQ_BASE,
 99                 MPIC_IRQ_STRIDE,
100                 MPIC_IRQ_VECTOR_PRI,
101                 MPIC_VECPRI_VECTOR_MASK,
102                 MPIC_VECPRI_POLARITY_POSITIVE,
103                 MPIC_VECPRI_POLARITY_NEGATIVE,
104                 MPIC_VECPRI_SENSE_LEVEL,
105                 MPIC_VECPRI_SENSE_EDGE,
106                 MPIC_VECPRI_POLARITY_MASK,
107                 MPIC_VECPRI_SENSE_MASK,
108                 MPIC_IRQ_DESTINATION
109         },
110         [1] = { /* Tsi108/109 PIC */
111                 TSI108_GREG_BASE,
112                 TSI108_GREG_FEATURE_0,
113                 TSI108_GREG_GLOBAL_CONF_0,
114                 TSI108_GREG_VENDOR_ID,
115                 TSI108_GREG_IPI_VECTOR_PRI_0,
116                 TSI108_GREG_IPI_STRIDE,
117                 TSI108_GREG_SPURIOUS,
118                 TSI108_GREG_TIMER_FREQ,
119 
120                 TSI108_TIMER_BASE,
121                 TSI108_TIMER_STRIDE,
122                 TSI108_TIMER_CURRENT_CNT,
123                 TSI108_TIMER_BASE_CNT,
124                 TSI108_TIMER_VECTOR_PRI,
125                 TSI108_TIMER_DESTINATION,
126 
127                 TSI108_CPU_BASE,
128                 TSI108_CPU_STRIDE,
129                 TSI108_CPU_IPI_DISPATCH_0,
130                 TSI108_CPU_IPI_DISPATCH_STRIDE,
131                 TSI108_CPU_CURRENT_TASK_PRI,
132                 TSI108_CPU_WHOAMI,
133                 TSI108_CPU_INTACK,
134                 TSI108_CPU_EOI,
135                 TSI108_CPU_MCACK,
136 
137                 TSI108_IRQ_BASE,
138                 TSI108_IRQ_STRIDE,
139                 TSI108_IRQ_VECTOR_PRI,
140                 TSI108_VECPRI_VECTOR_MASK,
141                 TSI108_VECPRI_POLARITY_POSITIVE,
142                 TSI108_VECPRI_POLARITY_NEGATIVE,
143                 TSI108_VECPRI_SENSE_LEVEL,
144                 TSI108_VECPRI_SENSE_EDGE,
145                 TSI108_VECPRI_POLARITY_MASK,
146                 TSI108_VECPRI_SENSE_MASK,
147                 TSI108_IRQ_DESTINATION
148         },
149 };
150 
151 #define MPIC_INFO(name) mpic->hw_set[MPIC_IDX_##name]
152 
153 #else /* CONFIG_MPIC_WEIRD */
154 
155 #define MPIC_INFO(name) MPIC_##name
156 
157 #endif /* CONFIG_MPIC_WEIRD */
158 
159 static inline unsigned int mpic_processor_id(struct mpic *mpic)
160 {
161         unsigned int cpu = 0;
162 
163         if (!(mpic->flags & MPIC_SECONDARY))
164                 cpu = hard_smp_processor_id();
165 
166         return cpu;
167 }
168 
169 /*
170  * Register accessor functions
171  */
172 
173 
174 static inline u32 _mpic_read(enum mpic_reg_type type,
175                              struct mpic_reg_bank *rb,
176                              unsigned int reg)
177 {
178         switch(type) {
179 #ifdef CONFIG_PPC_DCR
180         case mpic_access_dcr:
181                 return dcr_read(rb->dhost, reg);
182 #endif
183         case mpic_access_mmio_be:
184                 return in_be32(rb->base + (reg >> 2));
185         case mpic_access_mmio_le:
186         default:
187                 return in_le32(rb->base + (reg >> 2));
188         }
189 }
190 
191 static inline void _mpic_write(enum mpic_reg_type type,
192                                struct mpic_reg_bank *rb,
193                                unsigned int reg, u32 value)
194 {
195         switch(type) {
196 #ifdef CONFIG_PPC_DCR
197         case mpic_access_dcr:
198                 dcr_write(rb->dhost, reg, value);
199                 break;
200 #endif
201         case mpic_access_mmio_be:
202                 out_be32(rb->base + (reg >> 2), value);
203                 break;
204         case mpic_access_mmio_le:
205         default:
206                 out_le32(rb->base + (reg >> 2), value);
207                 break;
208         }
209 }
210 
211 static inline u32 _mpic_ipi_read(struct mpic *mpic, unsigned int ipi)
212 {
213         enum mpic_reg_type type = mpic->reg_type;
214         unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
215                               (ipi * MPIC_INFO(GREG_IPI_STRIDE));
216 
217         if ((mpic->flags & MPIC_BROKEN_IPI) && type == mpic_access_mmio_le)
218                 type = mpic_access_mmio_be;
219         return _mpic_read(type, &mpic->gregs, offset);
220 }
221 
222 static inline void _mpic_ipi_write(struct mpic *mpic, unsigned int ipi, u32 value)
223 {
224         unsigned int offset = MPIC_INFO(GREG_IPI_VECTOR_PRI_0) +
225                               (ipi * MPIC_INFO(GREG_IPI_STRIDE));
226 
227         _mpic_write(mpic->reg_type, &mpic->gregs, offset, value);
228 }
229 
230 static inline unsigned int mpic_tm_offset(struct mpic *mpic, unsigned int tm)
231 {
232         return (tm >> 2) * MPIC_TIMER_GROUP_STRIDE +
233                (tm & 3) * MPIC_INFO(TIMER_STRIDE);
234 }
235 
236 static inline u32 _mpic_tm_read(struct mpic *mpic, unsigned int tm)
237 {
238         unsigned int offset = mpic_tm_offset(mpic, tm) +
239                               MPIC_INFO(TIMER_VECTOR_PRI);
240 
241         return _mpic_read(mpic->reg_type, &mpic->tmregs, offset);
242 }
243 
244 static inline void _mpic_tm_write(struct mpic *mpic, unsigned int tm, u32 value)
245 {
246         unsigned int offset = mpic_tm_offset(mpic, tm) +
247                               MPIC_INFO(TIMER_VECTOR_PRI);
248 
249         _mpic_write(mpic->reg_type, &mpic->tmregs, offset, value);
250 }
251 
252 static inline u32 _mpic_cpu_read(struct mpic *mpic, unsigned int reg)
253 {
254         unsigned int cpu = mpic_processor_id(mpic);
255 
256         return _mpic_read(mpic->reg_type, &mpic->cpuregs[cpu], reg);
257 }
258 
259 static inline void _mpic_cpu_write(struct mpic *mpic, unsigned int reg, u32 value)
260 {
261         unsigned int cpu = mpic_processor_id(mpic);
262 
263         _mpic_write(mpic->reg_type, &mpic->cpuregs[cpu], reg, value);
264 }
265 
266 static inline u32 _mpic_irq_read(struct mpic *mpic, unsigned int src_no, unsigned int reg)
267 {
268         unsigned int    isu = src_no >> mpic->isu_shift;
269         unsigned int    idx = src_no & mpic->isu_mask;
270         unsigned int    val;
271 
272         val = _mpic_read(mpic->reg_type, &mpic->isus[isu],
273                          reg + (idx * MPIC_INFO(IRQ_STRIDE)));
274 #ifdef CONFIG_MPIC_BROKEN_REGREAD
275         if (reg == 0)
276                 val = (val & (MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY)) |
277                         mpic->isu_reg0_shadow[src_no];
278 #endif
279         return val;
280 }
281 
282 static inline void _mpic_irq_write(struct mpic *mpic, unsigned int src_no,
283                                    unsigned int reg, u32 value)
284 {
285         unsigned int    isu = src_no >> mpic->isu_shift;
286         unsigned int    idx = src_no & mpic->isu_mask;
287 
288         _mpic_write(mpic->reg_type, &mpic->isus[isu],
289                     reg + (idx * MPIC_INFO(IRQ_STRIDE)), value);
290 
291 #ifdef CONFIG_MPIC_BROKEN_REGREAD
292         if (reg == 0)
293                 mpic->isu_reg0_shadow[src_no] =
294                         value & ~(MPIC_VECPRI_MASK | MPIC_VECPRI_ACTIVITY);
295 #endif
296 }
297 
298 #define mpic_read(b,r)          _mpic_read(mpic->reg_type,&(b),(r))
299 #define mpic_write(b,r,v)       _mpic_write(mpic->reg_type,&(b),(r),(v))
300 #define mpic_ipi_read(i)        _mpic_ipi_read(mpic,(i))
301 #define mpic_ipi_write(i,v)     _mpic_ipi_write(mpic,(i),(v))
302 #define mpic_tm_read(i)         _mpic_tm_read(mpic,(i))
303 #define mpic_tm_write(i,v)      _mpic_tm_write(mpic,(i),(v))
304 #define mpic_cpu_read(i)        _mpic_cpu_read(mpic,(i))
305 #define mpic_cpu_write(i,v)     _mpic_cpu_write(mpic,(i),(v))
306 #define mpic_irq_read(s,r)      _mpic_irq_read(mpic,(s),(r))
307 #define mpic_irq_write(s,r,v)   _mpic_irq_write(mpic,(s),(r),(v))
308 
309 
310 /*
311  * Low level utility functions
312  */
313 
314 
315 static void _mpic_map_mmio(struct mpic *mpic, phys_addr_t phys_addr,
316                            struct mpic_reg_bank *rb, unsigned int offset,
317                            unsigned int size)
318 {
319         rb->base = ioremap(phys_addr + offset, size);
320         BUG_ON(rb->base == NULL);
321 }
322 
323 #ifdef CONFIG_PPC_DCR
324 static void _mpic_map_dcr(struct mpic *mpic, struct mpic_reg_bank *rb,
325                           unsigned int offset, unsigned int size)
326 {
327         phys_addr_t phys_addr = dcr_resource_start(mpic->node, 0);
328         rb->dhost = dcr_map(mpic->node, phys_addr + offset, size);
329         BUG_ON(!DCR_MAP_OK(rb->dhost));
330 }
331 
332 static inline void mpic_map(struct mpic *mpic,
333                             phys_addr_t phys_addr, struct mpic_reg_bank *rb,
334                             unsigned int offset, unsigned int size)
335 {
336         if (mpic->flags & MPIC_USES_DCR)
337                 _mpic_map_dcr(mpic, rb, offset, size);
338         else
339                 _mpic_map_mmio(mpic, phys_addr, rb, offset, size);
340 }
341 #else /* CONFIG_PPC_DCR */
342 #define mpic_map(m,p,b,o,s)     _mpic_map_mmio(m,p,b,o,s)
343 #endif /* !CONFIG_PPC_DCR */
344 
345 
346 
347 /* Check if we have one of those nice broken MPICs with a flipped endian on
348  * reads from IPI registers
349  */
350 static void __init mpic_test_broken_ipi(struct mpic *mpic)
351 {
352         u32 r;
353 
354         mpic_write(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0), MPIC_VECPRI_MASK);
355         r = mpic_read(mpic->gregs, MPIC_INFO(GREG_IPI_VECTOR_PRI_0));
356 
357         if (r == le32_to_cpu(MPIC_VECPRI_MASK)) {
358                 printk(KERN_INFO "mpic: Detected reversed IPI registers\n");
359                 mpic->flags |= MPIC_BROKEN_IPI;
360         }
361 }
362 
363 #ifdef CONFIG_MPIC_U3_HT_IRQS
364 
365 /* Test if an interrupt is sourced from HyperTransport (used on broken U3s)
366  * to force the edge setting on the MPIC and do the ack workaround.
367  */
368 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
369 {
370         if (source >= 128 || !mpic->fixups)
371                 return 0;
372         return mpic->fixups[source].base != NULL;
373 }
374 
375 
376 static inline void mpic_ht_end_irq(struct mpic *mpic, unsigned int source)
377 {
378         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
379 
380         if (fixup->applebase) {
381                 unsigned int soff = (fixup->index >> 3) & ~3;
382                 unsigned int mask = 1U << (fixup->index & 0x1f);
383                 writel(mask, fixup->applebase + soff);
384         } else {
385                 raw_spin_lock(&mpic->fixup_lock);
386                 writeb(0x11 + 2 * fixup->index, fixup->base + 2);
387                 writel(fixup->data, fixup->base + 4);
388                 raw_spin_unlock(&mpic->fixup_lock);
389         }
390 }
391 
392 static void mpic_startup_ht_interrupt(struct mpic *mpic, unsigned int source,
393                                       bool level)
394 {
395         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
396         unsigned long flags;
397         u32 tmp;
398 
399         if (fixup->base == NULL)
400                 return;
401 
402         DBG("startup_ht_interrupt(0x%x) index: %d\n",
403             source, fixup->index);
404         raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
405         /* Enable and configure */
406         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
407         tmp = readl(fixup->base + 4);
408         tmp &= ~(0x23U);
409         if (level)
410                 tmp |= 0x22;
411         writel(tmp, fixup->base + 4);
412         raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
413 
414 #ifdef CONFIG_PM
415         /* use the lowest bit inverted to the actual HW,
416          * set if this fixup was enabled, clear otherwise */
417         mpic->save_data[source].fixup_data = tmp | 1;
418 #endif
419 }
420 
421 static void mpic_shutdown_ht_interrupt(struct mpic *mpic, unsigned int source)
422 {
423         struct mpic_irq_fixup *fixup = &mpic->fixups[source];
424         unsigned long flags;
425         u32 tmp;
426 
427         if (fixup->base == NULL)
428                 return;
429 
430         DBG("shutdown_ht_interrupt(0x%x)\n", source);
431 
432         /* Disable */
433         raw_spin_lock_irqsave(&mpic->fixup_lock, flags);
434         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
435         tmp = readl(fixup->base + 4);
436         tmp |= 1;
437         writel(tmp, fixup->base + 4);
438         raw_spin_unlock_irqrestore(&mpic->fixup_lock, flags);
439 
440 #ifdef CONFIG_PM
441         /* use the lowest bit inverted to the actual HW,
442          * set if this fixup was enabled, clear otherwise */
443         mpic->save_data[source].fixup_data = tmp & ~1;
444 #endif
445 }
446 
447 #ifdef CONFIG_PCI_MSI
448 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
449                                     unsigned int devfn)
450 {
451         u8 __iomem *base;
452         u8 pos, flags;
453         u64 addr = 0;
454 
455         for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
456              pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
457                 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
458                 if (id == PCI_CAP_ID_HT) {
459                         id = readb(devbase + pos + 3);
460                         if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_MSI_MAPPING)
461                                 break;
462                 }
463         }
464 
465         if (pos == 0)
466                 return;
467 
468         base = devbase + pos;
469 
470         flags = readb(base + HT_MSI_FLAGS);
471         if (!(flags & HT_MSI_FLAGS_FIXED)) {
472                 addr = readl(base + HT_MSI_ADDR_LO) & HT_MSI_ADDR_LO_MASK;
473                 addr = addr | ((u64)readl(base + HT_MSI_ADDR_HI) << 32);
474         }
475 
476         printk(KERN_DEBUG "mpic:   - HT:%02x.%x %s MSI mapping found @ 0x%llx\n",
477                 PCI_SLOT(devfn), PCI_FUNC(devfn),
478                 flags & HT_MSI_FLAGS_ENABLE ? "enabled" : "disabled", addr);
479 
480         if (!(flags & HT_MSI_FLAGS_ENABLE))
481                 writeb(flags | HT_MSI_FLAGS_ENABLE, base + HT_MSI_FLAGS);
482 }
483 #else
484 static void __init mpic_scan_ht_msi(struct mpic *mpic, u8 __iomem *devbase,
485                                     unsigned int devfn)
486 {
487         return;
488 }
489 #endif
490 
491 static void __init mpic_scan_ht_pic(struct mpic *mpic, u8 __iomem *devbase,
492                                     unsigned int devfn, u32 vdid)
493 {
494         int i, irq, n;
495         u8 __iomem *base;
496         u32 tmp;
497         u8 pos;
498 
499         for (pos = readb(devbase + PCI_CAPABILITY_LIST); pos != 0;
500              pos = readb(devbase + pos + PCI_CAP_LIST_NEXT)) {
501                 u8 id = readb(devbase + pos + PCI_CAP_LIST_ID);
502                 if (id == PCI_CAP_ID_HT) {
503                         id = readb(devbase + pos + 3);
504                         if ((id & HT_5BIT_CAP_MASK) == HT_CAPTYPE_IRQ)
505                                 break;
506                 }
507         }
508         if (pos == 0)
509                 return;
510 
511         base = devbase + pos;
512         writeb(0x01, base + 2);
513         n = (readl(base + 4) >> 16) & 0xff;
514 
515         printk(KERN_INFO "mpic:   - HT:%02x.%x [0x%02x] vendor %04x device %04x"
516                " has %d irqs\n",
517                devfn >> 3, devfn & 0x7, pos, vdid & 0xffff, vdid >> 16, n + 1);
518 
519         for (i = 0; i <= n; i++) {
520                 writeb(0x10 + 2 * i, base + 2);
521                 tmp = readl(base + 4);
522                 irq = (tmp >> 16) & 0xff;
523                 DBG("HT PIC index 0x%x, irq 0x%x, tmp: %08x\n", i, irq, tmp);
524                 /* mask it , will be unmasked later */
525                 tmp |= 0x1;
526                 writel(tmp, base + 4);
527                 mpic->fixups[irq].index = i;
528                 mpic->fixups[irq].base = base;
529                 /* Apple HT PIC has a non-standard way of doing EOIs */
530                 if ((vdid & 0xffff) == 0x106b)
531                         mpic->fixups[irq].applebase = devbase + 0x60;
532                 else
533                         mpic->fixups[irq].applebase = NULL;
534                 writeb(0x11 + 2 * i, base + 2);
535                 mpic->fixups[irq].data = readl(base + 4) | 0x80000000;
536         }
537 }
538 
539 
540 static void __init mpic_scan_ht_pics(struct mpic *mpic)
541 {
542         unsigned int devfn;
543         u8 __iomem *cfgspace;
544 
545         printk(KERN_INFO "mpic: Setting up HT PICs workarounds for U3/U4\n");
546 
547         /* Allocate fixups array */
548         mpic->fixups = kzalloc(128 * sizeof(*mpic->fixups), GFP_KERNEL);
549         BUG_ON(mpic->fixups == NULL);
550 
551         /* Init spinlock */
552         raw_spin_lock_init(&mpic->fixup_lock);
553 
554         /* Map U3 config space. We assume all IO-APICs are on the primary bus
555          * so we only need to map 64kB.
556          */
557         cfgspace = ioremap(0xf2000000, 0x10000);
558         BUG_ON(cfgspace == NULL);
559 
560         /* Now we scan all slots. We do a very quick scan, we read the header
561          * type, vendor ID and device ID only, that's plenty enough
562          */
563         for (devfn = 0; devfn < 0x100; devfn++) {
564                 u8 __iomem *devbase = cfgspace + (devfn << 8);
565                 u8 hdr_type = readb(devbase + PCI_HEADER_TYPE);
566                 u32 l = readl(devbase + PCI_VENDOR_ID);
567                 u16 s;
568 
569                 DBG("devfn %x, l: %x\n", devfn, l);
570 
571                 /* If no device, skip */
572                 if (l == 0xffffffff || l == 0x00000000 ||
573                     l == 0x0000ffff || l == 0xffff0000)
574                         goto next;
575                 /* Check if is supports capability lists */
576                 s = readw(devbase + PCI_STATUS);
577                 if (!(s & PCI_STATUS_CAP_LIST))
578                         goto next;
579 
580                 mpic_scan_ht_pic(mpic, devbase, devfn, l);
581                 mpic_scan_ht_msi(mpic, devbase, devfn);
582 
583         next:
584                 /* next device, if function 0 */
585                 if (PCI_FUNC(devfn) == 0 && (hdr_type & 0x80) == 0)
586                         devfn += 7;
587         }
588 }
589 
590 #else /* CONFIG_MPIC_U3_HT_IRQS */
591 
592 static inline int mpic_is_ht_interrupt(struct mpic *mpic, unsigned int source)
593 {
594         return 0;
595 }
596 
597 static void __init mpic_scan_ht_pics(struct mpic *mpic)
598 {
599 }
600 
601 #endif /* CONFIG_MPIC_U3_HT_IRQS */
602 
603 /* Find an mpic associated with a given linux interrupt */
604 static struct mpic *mpic_find(unsigned int irq)
605 {
606         if (irq < NUM_ISA_INTERRUPTS)
607                 return NULL;
608 
609         return irq_get_chip_data(irq);
610 }
611 
612 /* Determine if the linux irq is an IPI */
613 static unsigned int mpic_is_ipi(struct mpic *mpic, unsigned int src)
614 {
615         return (src >= mpic->ipi_vecs[0] && src <= mpic->ipi_vecs[3]);
616 }
617 
618 /* Determine if the linux irq is a timer */
619 static unsigned int mpic_is_tm(struct mpic *mpic, unsigned int src)
620 {
621         return (src >= mpic->timer_vecs[0] && src <= mpic->timer_vecs[7]);
622 }
623 
624 /* Convert a cpu mask from logical to physical cpu numbers. */
625 static inline u32 mpic_physmask(u32 cpumask)
626 {
627         int i;
628         u32 mask = 0;
629 
630         for (i = 0; i < min(32, NR_CPUS); ++i, cpumask >>= 1)
631                 mask |= (cpumask & 1) << get_hard_smp_processor_id(i);
632         return mask;
633 }
634 
635 #ifdef CONFIG_SMP
636 /* Get the mpic structure from the IPI number */
637 static inline struct mpic * mpic_from_ipi(struct irq_data *d)
638 {
639         return irq_data_get_irq_chip_data(d);
640 }
641 #endif
642 
643 /* Get the mpic structure from the irq number */
644 static inline struct mpic * mpic_from_irq(unsigned int irq)
645 {
646         return irq_get_chip_data(irq);
647 }
648 
649 /* Get the mpic structure from the irq data */
650 static inline struct mpic * mpic_from_irq_data(struct irq_data *d)
651 {
652         return irq_data_get_irq_chip_data(d);
653 }
654 
655 /* Send an EOI */
656 static inline void mpic_eoi(struct mpic *mpic)
657 {
658         mpic_cpu_write(MPIC_INFO(CPU_EOI), 0);
659         (void)mpic_cpu_read(MPIC_INFO(CPU_WHOAMI));
660 }
661 
662 /*
663  * Linux descriptor level callbacks
664  */
665 
666 
667 void mpic_unmask_irq(struct irq_data *d)
668 {
669         unsigned int loops = 100000;
670         struct mpic *mpic = mpic_from_irq_data(d);
671         unsigned int src = irqd_to_hwirq(d);
672 
673         DBG("%p: %s: enable_irq: %d (src %d)\n", mpic, mpic->name, d->irq, src);
674 
675         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
676                        mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) &
677                        ~MPIC_VECPRI_MASK);
678         /* make sure mask gets to controller before we return to user */
679         do {
680                 if (!loops--) {
681                         printk(KERN_ERR "%s: timeout on hwirq %u\n",
682                                __func__, src);
683                         break;
684                 }
685         } while(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK);
686 }
687 
688 void mpic_mask_irq(struct irq_data *d)
689 {
690         unsigned int loops = 100000;
691         struct mpic *mpic = mpic_from_irq_data(d);
692         unsigned int src = irqd_to_hwirq(d);
693 
694         DBG("%s: disable_irq: %d (src %d)\n", mpic->name, d->irq, src);
695 
696         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
697                        mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) |
698                        MPIC_VECPRI_MASK);
699 
700         /* make sure mask gets to controller before we return to user */
701         do {
702                 if (!loops--) {
703                         printk(KERN_ERR "%s: timeout on hwirq %u\n",
704                                __func__, src);
705                         break;
706                 }
707         } while(!(mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI)) & MPIC_VECPRI_MASK));
708 }
709 
710 void mpic_end_irq(struct irq_data *d)
711 {
712         struct mpic *mpic = mpic_from_irq_data(d);
713 
714 #ifdef DEBUG_IRQ
715         DBG("%s: end_irq: %d\n", mpic->name, d->irq);
716 #endif
717         /* We always EOI on end_irq() even for edge interrupts since that
718          * should only lower the priority, the MPIC should have properly
719          * latched another edge interrupt coming in anyway
720          */
721 
722         mpic_eoi(mpic);
723 }
724 
725 #ifdef CONFIG_MPIC_U3_HT_IRQS
726 
727 static void mpic_unmask_ht_irq(struct irq_data *d)
728 {
729         struct mpic *mpic = mpic_from_irq_data(d);
730         unsigned int src = irqd_to_hwirq(d);
731 
732         mpic_unmask_irq(d);
733 
734         if (irqd_is_level_type(d))
735                 mpic_ht_end_irq(mpic, src);
736 }
737 
738 static unsigned int mpic_startup_ht_irq(struct irq_data *d)
739 {
740         struct mpic *mpic = mpic_from_irq_data(d);
741         unsigned int src = irqd_to_hwirq(d);
742 
743         mpic_unmask_irq(d);
744         mpic_startup_ht_interrupt(mpic, src, irqd_is_level_type(d));
745 
746         return 0;
747 }
748 
749 static void mpic_shutdown_ht_irq(struct irq_data *d)
750 {
751         struct mpic *mpic = mpic_from_irq_data(d);
752         unsigned int src = irqd_to_hwirq(d);
753 
754         mpic_shutdown_ht_interrupt(mpic, src);
755         mpic_mask_irq(d);
756 }
757 
758 static void mpic_end_ht_irq(struct irq_data *d)
759 {
760         struct mpic *mpic = mpic_from_irq_data(d);
761         unsigned int src = irqd_to_hwirq(d);
762 
763 #ifdef DEBUG_IRQ
764         DBG("%s: end_irq: %d\n", mpic->name, d->irq);
765 #endif
766         /* We always EOI on end_irq() even for edge interrupts since that
767          * should only lower the priority, the MPIC should have properly
768          * latched another edge interrupt coming in anyway
769          */
770 
771         if (irqd_is_level_type(d))
772                 mpic_ht_end_irq(mpic, src);
773         mpic_eoi(mpic);
774 }
775 #endif /* !CONFIG_MPIC_U3_HT_IRQS */
776 
777 #ifdef CONFIG_SMP
778 
779 static void mpic_unmask_ipi(struct irq_data *d)
780 {
781         struct mpic *mpic = mpic_from_ipi(d);
782         unsigned int src = virq_to_hw(d->irq) - mpic->ipi_vecs[0];
783 
784         DBG("%s: enable_ipi: %d (ipi %d)\n", mpic->name, d->irq, src);
785         mpic_ipi_write(src, mpic_ipi_read(src) & ~MPIC_VECPRI_MASK);
786 }
787 
788 static void mpic_mask_ipi(struct irq_data *d)
789 {
790         /* NEVER disable an IPI... that's just plain wrong! */
791 }
792 
793 static void mpic_end_ipi(struct irq_data *d)
794 {
795         struct mpic *mpic = mpic_from_ipi(d);
796 
797         /*
798          * IPIs are marked IRQ_PER_CPU. This has the side effect of
799          * preventing the IRQ_PENDING/IRQ_INPROGRESS logic from
800          * applying to them. We EOI them late to avoid re-entering.
801          */
802         mpic_eoi(mpic);
803 }
804 
805 #endif /* CONFIG_SMP */
806 
807 static void mpic_unmask_tm(struct irq_data *d)
808 {
809         struct mpic *mpic = mpic_from_irq_data(d);
810         unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
811 
812         DBG("%s: enable_tm: %d (tm %d)\n", mpic->name, d->irq, src);
813         mpic_tm_write(src, mpic_tm_read(src) & ~MPIC_VECPRI_MASK);
814         mpic_tm_read(src);
815 }
816 
817 static void mpic_mask_tm(struct irq_data *d)
818 {
819         struct mpic *mpic = mpic_from_irq_data(d);
820         unsigned int src = virq_to_hw(d->irq) - mpic->timer_vecs[0];
821 
822         mpic_tm_write(src, mpic_tm_read(src) | MPIC_VECPRI_MASK);
823         mpic_tm_read(src);
824 }
825 
826 int mpic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
827                       bool force)
828 {
829         struct mpic *mpic = mpic_from_irq_data(d);
830         unsigned int src = irqd_to_hwirq(d);
831 
832         if (mpic->flags & MPIC_SINGLE_DEST_CPU) {
833                 int cpuid = irq_choose_cpu(cpumask);
834 
835                 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
836         } else {
837                 u32 mask = cpumask_bits(cpumask)[0];
838 
839                 mask &= cpumask_bits(cpu_online_mask)[0];
840 
841                 mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION),
842                                mpic_physmask(mask));
843         }
844 
845         return IRQ_SET_MASK_OK;
846 }
847 
848 static unsigned int mpic_type_to_vecpri(struct mpic *mpic, unsigned int type)
849 {
850         /* Now convert sense value */
851         switch(type & IRQ_TYPE_SENSE_MASK) {
852         case IRQ_TYPE_EDGE_RISING:
853                 return MPIC_INFO(VECPRI_SENSE_EDGE) |
854                        MPIC_INFO(VECPRI_POLARITY_POSITIVE);
855         case IRQ_TYPE_EDGE_FALLING:
856         case IRQ_TYPE_EDGE_BOTH:
857                 return MPIC_INFO(VECPRI_SENSE_EDGE) |
858                        MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
859         case IRQ_TYPE_LEVEL_HIGH:
860                 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
861                        MPIC_INFO(VECPRI_POLARITY_POSITIVE);
862         case IRQ_TYPE_LEVEL_LOW:
863         default:
864                 return MPIC_INFO(VECPRI_SENSE_LEVEL) |
865                        MPIC_INFO(VECPRI_POLARITY_NEGATIVE);
866         }
867 }
868 
869 int mpic_set_irq_type(struct irq_data *d, unsigned int flow_type)
870 {
871         struct mpic *mpic = mpic_from_irq_data(d);
872         unsigned int src = irqd_to_hwirq(d);
873         unsigned int vecpri, vold, vnew;
874 
875         DBG("mpic: set_irq_type(mpic:@%p,virq:%d,src:0x%x,type:0x%x)\n",
876             mpic, d->irq, src, flow_type);
877 
878         if (src >= mpic->num_sources)
879                 return -EINVAL;
880 
881         vold = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
882 
883         /* We don't support "none" type */
884         if (flow_type == IRQ_TYPE_NONE)
885                 flow_type = IRQ_TYPE_DEFAULT;
886 
887         /* Default: read HW settings */
888         if (flow_type == IRQ_TYPE_DEFAULT) {
889                 int vold_ps;
890 
891                 vold_ps = vold & (MPIC_INFO(VECPRI_POLARITY_MASK) |
892                                   MPIC_INFO(VECPRI_SENSE_MASK));
893 
894                 if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
895                                 MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
896                         flow_type = IRQ_TYPE_EDGE_RISING;
897                 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_EDGE) |
898                                      MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
899                         flow_type = IRQ_TYPE_EDGE_FALLING;
900                 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
901                                      MPIC_INFO(VECPRI_POLARITY_POSITIVE)))
902                         flow_type = IRQ_TYPE_LEVEL_HIGH;
903                 else if (vold_ps == (MPIC_INFO(VECPRI_SENSE_LEVEL) |
904                                      MPIC_INFO(VECPRI_POLARITY_NEGATIVE)))
905                         flow_type = IRQ_TYPE_LEVEL_LOW;
906                 else
907                         WARN_ONCE(1, "mpic: unknown IRQ type %d\n", vold);
908         }
909 
910         /* Apply to irq desc */
911         irqd_set_trigger_type(d, flow_type);
912 
913         /* Apply to HW */
914         if (mpic_is_ht_interrupt(mpic, src))
915                 vecpri = MPIC_VECPRI_POLARITY_POSITIVE |
916                         MPIC_VECPRI_SENSE_EDGE;
917         else
918                 vecpri = mpic_type_to_vecpri(mpic, flow_type);
919 
920         vnew = vold & ~(MPIC_INFO(VECPRI_POLARITY_MASK) |
921                         MPIC_INFO(VECPRI_SENSE_MASK));
922         vnew |= vecpri;
923         if (vold != vnew)
924                 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vnew);
925 
926         return IRQ_SET_MASK_OK_NOCOPY;
927 }
928 
929 static int mpic_irq_set_wake(struct irq_data *d, unsigned int on)
930 {
931         struct irq_desc *desc = container_of(d, struct irq_desc, irq_data);
932         struct mpic *mpic = mpic_from_irq_data(d);
933 
934         if (!(mpic->flags & MPIC_FSL))
935                 return -ENXIO;
936 
937         if (on)
938                 desc->action->flags |= IRQF_NO_SUSPEND;
939         else
940                 desc->action->flags &= ~IRQF_NO_SUSPEND;
941 
942         return 0;
943 }
944 
945 void mpic_set_vector(unsigned int virq, unsigned int vector)
946 {
947         struct mpic *mpic = mpic_from_irq(virq);
948         unsigned int src = virq_to_hw(virq);
949         unsigned int vecpri;
950 
951         DBG("mpic: set_vector(mpic:@%p,virq:%d,src:%d,vector:0x%x)\n",
952             mpic, virq, src, vector);
953 
954         if (src >= mpic->num_sources)
955                 return;
956 
957         vecpri = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI));
958         vecpri = vecpri & ~MPIC_INFO(VECPRI_VECTOR_MASK);
959         vecpri |= vector;
960         mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
961 }
962 
963 void mpic_set_destination(unsigned int virq, unsigned int cpuid)
964 {
965         struct mpic *mpic = mpic_from_irq(virq);
966         unsigned int src = virq_to_hw(virq);
967 
968         DBG("mpic: set_destination(mpic:@%p,virq:%d,src:%d,cpuid:0x%x)\n",
969             mpic, virq, src, cpuid);
970 
971         if (src >= mpic->num_sources)
972                 return;
973 
974         mpic_irq_write(src, MPIC_INFO(IRQ_DESTINATION), 1 << cpuid);
975 }
976 
977 static struct irq_chip mpic_irq_chip = {
978         .irq_mask       = mpic_mask_irq,
979         .irq_unmask     = mpic_unmask_irq,
980         .irq_eoi        = mpic_end_irq,
981         .irq_set_type   = mpic_set_irq_type,
982         .irq_set_wake   = mpic_irq_set_wake,
983 };
984 
985 #ifdef CONFIG_SMP
986 static struct irq_chip mpic_ipi_chip = {
987         .irq_mask       = mpic_mask_ipi,
988         .irq_unmask     = mpic_unmask_ipi,
989         .irq_eoi        = mpic_end_ipi,
990 };
991 #endif /* CONFIG_SMP */
992 
993 static struct irq_chip mpic_tm_chip = {
994         .irq_mask       = mpic_mask_tm,
995         .irq_unmask     = mpic_unmask_tm,
996         .irq_eoi        = mpic_end_irq,
997         .irq_set_wake   = mpic_irq_set_wake,
998 };
999 
1000 #ifdef CONFIG_MPIC_U3_HT_IRQS
1001 static struct irq_chip mpic_irq_ht_chip = {
1002         .irq_startup    = mpic_startup_ht_irq,
1003         .irq_shutdown   = mpic_shutdown_ht_irq,
1004         .irq_mask       = mpic_mask_irq,
1005         .irq_unmask     = mpic_unmask_ht_irq,
1006         .irq_eoi        = mpic_end_ht_irq,
1007         .irq_set_type   = mpic_set_irq_type,
1008 };
1009 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1010 
1011 
1012 static int mpic_host_match(struct irq_domain *h, struct device_node *node)
1013 {
1014         /* Exact match, unless mpic node is NULL */
1015         return h->of_node == NULL || h->of_node == node;
1016 }
1017 
1018 static int mpic_host_map(struct irq_domain *h, unsigned int virq,
1019                          irq_hw_number_t hw)
1020 {
1021         struct mpic *mpic = h->host_data;
1022         struct irq_chip *chip;
1023 
1024         DBG("mpic: map virq %d, hwirq 0x%lx\n", virq, hw);
1025 
1026         if (hw == mpic->spurious_vec)
1027                 return -EINVAL;
1028         if (mpic->protected && test_bit(hw, mpic->protected)) {
1029                 pr_warning("mpic: Mapping of source 0x%x failed, "
1030                            "source protected by firmware !\n",\
1031                            (unsigned int)hw);
1032                 return -EPERM;
1033         }
1034 
1035 #ifdef CONFIG_SMP
1036         else if (hw >= mpic->ipi_vecs[0]) {
1037                 WARN_ON(mpic->flags & MPIC_SECONDARY);
1038 
1039                 DBG("mpic: mapping as IPI\n");
1040                 irq_set_chip_data(virq, mpic);
1041                 irq_set_chip_and_handler(virq, &mpic->hc_ipi,
1042                                          handle_percpu_irq);
1043                 return 0;
1044         }
1045 #endif /* CONFIG_SMP */
1046 
1047         if (hw >= mpic->timer_vecs[0] && hw <= mpic->timer_vecs[7]) {
1048                 WARN_ON(mpic->flags & MPIC_SECONDARY);
1049 
1050                 DBG("mpic: mapping as timer\n");
1051                 irq_set_chip_data(virq, mpic);
1052                 irq_set_chip_and_handler(virq, &mpic->hc_tm,
1053                                          handle_fasteoi_irq);
1054                 return 0;
1055         }
1056 
1057         if (mpic_map_error_int(mpic, virq, hw))
1058                 return 0;
1059 
1060         if (hw >= mpic->num_sources) {
1061                 pr_warning("mpic: Mapping of source 0x%x failed, "
1062                            "source out of range !\n",\
1063                            (unsigned int)hw);
1064                 return -EINVAL;
1065         }
1066 
1067         mpic_msi_reserve_hwirq(mpic, hw);
1068 
1069         /* Default chip */
1070         chip = &mpic->hc_irq;
1071 
1072 #ifdef CONFIG_MPIC_U3_HT_IRQS
1073         /* Check for HT interrupts, override vecpri */
1074         if (mpic_is_ht_interrupt(mpic, hw))
1075                 chip = &mpic->hc_ht_irq;
1076 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1077 
1078         DBG("mpic: mapping to irq chip @%p\n", chip);
1079 
1080         irq_set_chip_data(virq, mpic);
1081         irq_set_chip_and_handler(virq, chip, handle_fasteoi_irq);
1082 
1083         /* Set default irq type */
1084         irq_set_irq_type(virq, IRQ_TYPE_DEFAULT);
1085 
1086         /* If the MPIC was reset, then all vectors have already been
1087          * initialized.  Otherwise, a per source lazy initialization
1088          * is done here.
1089          */
1090         if (!mpic_is_ipi(mpic, hw) && (mpic->flags & MPIC_NO_RESET)) {
1091                 int cpu;
1092 
1093                 preempt_disable();
1094                 cpu = mpic_processor_id(mpic);
1095                 preempt_enable();
1096 
1097                 mpic_set_vector(virq, hw);
1098                 mpic_set_destination(virq, cpu);
1099                 mpic_irq_set_priority(virq, 8);
1100         }
1101 
1102         return 0;
1103 }
1104 
1105 static int mpic_host_xlate(struct irq_domain *h, struct device_node *ct,
1106                            const u32 *intspec, unsigned int intsize,
1107                            irq_hw_number_t *out_hwirq, unsigned int *out_flags)
1108 
1109 {
1110         struct mpic *mpic = h->host_data;
1111         static unsigned char map_mpic_senses[4] = {
1112                 IRQ_TYPE_EDGE_RISING,
1113                 IRQ_TYPE_LEVEL_LOW,
1114                 IRQ_TYPE_LEVEL_HIGH,
1115                 IRQ_TYPE_EDGE_FALLING,
1116         };
1117 
1118         *out_hwirq = intspec[0];
1119         if (intsize >= 4 && (mpic->flags & MPIC_FSL)) {
1120                 /*
1121                  * Freescale MPIC with extended intspec:
1122                  * First two cells are as usual.  Third specifies
1123                  * an "interrupt type".  Fourth is type-specific data.
1124                  *
1125                  * See Documentation/devicetree/bindings/powerpc/fsl/mpic.txt
1126                  */
1127                 switch (intspec[2]) {
1128                 case 0:
1129                         break;
1130                 case 1:
1131                         if (!(mpic->flags & MPIC_FSL_HAS_EIMR))
1132                                 break;
1133 
1134                         if (intspec[3] >= ARRAY_SIZE(mpic->err_int_vecs))
1135                                 return -EINVAL;
1136 
1137                         *out_hwirq = mpic->err_int_vecs[intspec[3]];
1138 
1139                         break;
1140                 case 2:
1141                         if (intspec[0] >= ARRAY_SIZE(mpic->ipi_vecs))
1142                                 return -EINVAL;
1143 
1144                         *out_hwirq = mpic->ipi_vecs[intspec[0]];
1145                         break;
1146                 case 3:
1147                         if (intspec[0] >= ARRAY_SIZE(mpic->timer_vecs))
1148                                 return -EINVAL;
1149 
1150                         *out_hwirq = mpic->timer_vecs[intspec[0]];
1151                         break;
1152                 default:
1153                         pr_debug("%s: unknown irq type %u\n",
1154                                  __func__, intspec[2]);
1155                         return -EINVAL;
1156                 }
1157 
1158                 *out_flags = map_mpic_senses[intspec[1] & 3];
1159         } else if (intsize > 1) {
1160                 u32 mask = 0x3;
1161 
1162                 /* Apple invented a new race of encoding on machines with
1163                  * an HT APIC. They encode, among others, the index within
1164                  * the HT APIC. We don't care about it here since thankfully,
1165                  * it appears that they have the APIC already properly
1166                  * configured, and thus our current fixup code that reads the
1167                  * APIC config works fine. However, we still need to mask out
1168                  * bits in the specifier to make sure we only get bit 0 which
1169                  * is the level/edge bit (the only sense bit exposed by Apple),
1170                  * as their bit 1 means something else.
1171                  */
1172                 if (machine_is(powermac))
1173                         mask = 0x1;
1174                 *out_flags = map_mpic_senses[intspec[1] & mask];
1175         } else
1176                 *out_flags = IRQ_TYPE_NONE;
1177 
1178         DBG("mpic: xlate (%d cells: 0x%08x 0x%08x) to line 0x%lx sense 0x%x\n",
1179             intsize, intspec[0], intspec[1], *out_hwirq, *out_flags);
1180 
1181         return 0;
1182 }
1183 
1184 /* IRQ handler for a secondary MPIC cascaded from another IRQ controller */
1185 static void mpic_cascade(unsigned int irq, struct irq_desc *desc)
1186 {
1187         struct irq_chip *chip = irq_desc_get_chip(desc);
1188         struct mpic *mpic = irq_desc_get_handler_data(desc);
1189         unsigned int virq;
1190 
1191         BUG_ON(!(mpic->flags & MPIC_SECONDARY));
1192 
1193         virq = mpic_get_one_irq(mpic);
1194         if (virq)
1195                 generic_handle_irq(virq);
1196 
1197         chip->irq_eoi(&desc->irq_data);
1198 }
1199 
1200 static struct irq_domain_ops mpic_host_ops = {
1201         .match = mpic_host_match,
1202         .map = mpic_host_map,
1203         .xlate = mpic_host_xlate,
1204 };
1205 
1206 static u32 fsl_mpic_get_version(struct mpic *mpic)
1207 {
1208         u32 brr1;
1209 
1210         if (!(mpic->flags & MPIC_FSL))
1211                 return 0;
1212 
1213         brr1 = _mpic_read(mpic->reg_type, &mpic->thiscpuregs,
1214                         MPIC_FSL_BRR1);
1215 
1216         return brr1 & MPIC_FSL_BRR1_VER;
1217 }
1218 
1219 /*
1220  * Exported functions
1221  */
1222 
1223 u32 fsl_mpic_primary_get_version(void)
1224 {
1225         struct mpic *mpic = mpic_primary;
1226 
1227         if (mpic)
1228                 return fsl_mpic_get_version(mpic);
1229 
1230         return 0;
1231 }
1232 
1233 struct mpic * __init mpic_alloc(struct device_node *node,
1234                                 phys_addr_t phys_addr,
1235                                 unsigned int flags,
1236                                 unsigned int isu_size,
1237                                 unsigned int irq_count,
1238                                 const char *name)
1239 {
1240         int i, psize, intvec_top;
1241         struct mpic *mpic;
1242         u32 greg_feature;
1243         const char *vers;
1244         const u32 *psrc;
1245         u32 last_irq;
1246         u32 fsl_version = 0;
1247 
1248         /* Default MPIC search parameters */
1249         static const struct of_device_id __initconst mpic_device_id[] = {
1250                 { .type       = "open-pic", },
1251                 { .compatible = "open-pic", },
1252                 {},
1253         };
1254 
1255         /*
1256          * If we were not passed a device-tree node, then perform the default
1257          * search for standardized a standardized OpenPIC.
1258          */
1259         if (node) {
1260                 node = of_node_get(node);
1261         } else {
1262                 node = of_find_matching_node(NULL, mpic_device_id);
1263                 if (!node)
1264                         return NULL;
1265         }
1266 
1267         /* Pick the physical address from the device tree if unspecified */
1268         if (!phys_addr) {
1269                 /* Check if it is DCR-based */
1270                 if (of_get_property(node, "dcr-reg", NULL)) {
1271                         flags |= MPIC_USES_DCR;
1272                 } else {
1273                         struct resource r;
1274                         if (of_address_to_resource(node, 0, &r))
1275                                 goto err_of_node_put;
1276                         phys_addr = r.start;
1277                 }
1278         }
1279 
1280         /* Read extra device-tree properties into the flags variable */
1281         if (of_get_property(node, "big-endian", NULL))
1282                 flags |= MPIC_BIG_ENDIAN;
1283         if (of_get_property(node, "pic-no-reset", NULL))
1284                 flags |= MPIC_NO_RESET;
1285         if (of_get_property(node, "single-cpu-affinity", NULL))
1286                 flags |= MPIC_SINGLE_DEST_CPU;
1287         if (of_device_is_compatible(node, "fsl,mpic"))
1288                 flags |= MPIC_FSL | MPIC_LARGE_VECTORS;
1289 
1290         mpic = kzalloc(sizeof(struct mpic), GFP_KERNEL);
1291         if (mpic == NULL)
1292                 goto err_of_node_put;
1293 
1294         mpic->name = name;
1295         mpic->node = node;
1296         mpic->paddr = phys_addr;
1297         mpic->flags = flags;
1298 
1299         mpic->hc_irq = mpic_irq_chip;
1300         mpic->hc_irq.name = name;
1301         if (!(mpic->flags & MPIC_SECONDARY))
1302                 mpic->hc_irq.irq_set_affinity = mpic_set_affinity;
1303 #ifdef CONFIG_MPIC_U3_HT_IRQS
1304         mpic->hc_ht_irq = mpic_irq_ht_chip;
1305         mpic->hc_ht_irq.name = name;
1306         if (!(mpic->flags & MPIC_SECONDARY))
1307                 mpic->hc_ht_irq.irq_set_affinity = mpic_set_affinity;
1308 #endif /* CONFIG_MPIC_U3_HT_IRQS */
1309 
1310 #ifdef CONFIG_SMP
1311         mpic->hc_ipi = mpic_ipi_chip;
1312         mpic->hc_ipi.name = name;
1313 #endif /* CONFIG_SMP */
1314 
1315         mpic->hc_tm = mpic_tm_chip;
1316         mpic->hc_tm.name = name;
1317 
1318         mpic->num_sources = 0; /* so far */
1319 
1320         if (mpic->flags & MPIC_LARGE_VECTORS)
1321                 intvec_top = 2047;
1322         else
1323                 intvec_top = 255;
1324 
1325         mpic->timer_vecs[0] = intvec_top - 12;
1326         mpic->timer_vecs[1] = intvec_top - 11;
1327         mpic->timer_vecs[2] = intvec_top - 10;
1328         mpic->timer_vecs[3] = intvec_top - 9;
1329         mpic->timer_vecs[4] = intvec_top - 8;
1330         mpic->timer_vecs[5] = intvec_top - 7;
1331         mpic->timer_vecs[6] = intvec_top - 6;
1332         mpic->timer_vecs[7] = intvec_top - 5;
1333         mpic->ipi_vecs[0]   = intvec_top - 4;
1334         mpic->ipi_vecs[1]   = intvec_top - 3;
1335         mpic->ipi_vecs[2]   = intvec_top - 2;
1336         mpic->ipi_vecs[3]   = intvec_top - 1;
1337         mpic->spurious_vec  = intvec_top;
1338 
1339         /* Look for protected sources */
1340         psrc = of_get_property(mpic->node, "protected-sources", &psize);
1341         if (psrc) {
1342                 /* Allocate a bitmap with one bit per interrupt */
1343                 unsigned int mapsize = BITS_TO_LONGS(intvec_top + 1);
1344                 mpic->protected = kzalloc(mapsize*sizeof(long), GFP_KERNEL);
1345                 BUG_ON(mpic->protected == NULL);
1346                 for (i = 0; i < psize/sizeof(u32); i++) {
1347                         if (psrc[i] > intvec_top)
1348                                 continue;
1349                         __set_bit(psrc[i], mpic->protected);
1350                 }
1351         }
1352 
1353 #ifdef CONFIG_MPIC_WEIRD
1354         mpic->hw_set = mpic_infos[MPIC_GET_REGSET(mpic->flags)];
1355 #endif
1356 
1357         /* default register type */
1358         if (mpic->flags & MPIC_BIG_ENDIAN)
1359                 mpic->reg_type = mpic_access_mmio_be;
1360         else
1361                 mpic->reg_type = mpic_access_mmio_le;
1362 
1363         /*
1364          * An MPIC with a "dcr-reg" property must be accessed that way, but
1365          * only if the kernel includes DCR support.
1366          */
1367 #ifdef CONFIG_PPC_DCR
1368         if (mpic->flags & MPIC_USES_DCR)
1369                 mpic->reg_type = mpic_access_dcr;
1370 #else
1371         BUG_ON(mpic->flags & MPIC_USES_DCR);
1372 #endif
1373 
1374         /* Map the global registers */
1375         mpic_map(mpic, mpic->paddr, &mpic->gregs, MPIC_INFO(GREG_BASE), 0x1000);
1376         mpic_map(mpic, mpic->paddr, &mpic->tmregs, MPIC_INFO(TIMER_BASE), 0x1000);
1377 
1378         if (mpic->flags & MPIC_FSL) {
1379                 int ret;
1380 
1381                 /*
1382                  * Yes, Freescale really did put global registers in the
1383                  * magic per-cpu area -- and they don't even show up in the
1384                  * non-magic per-cpu copies that this driver normally uses.
1385                  */
1386                 mpic_map(mpic, mpic->paddr, &mpic->thiscpuregs,
1387                          MPIC_CPU_THISBASE, 0x1000);
1388 
1389                 fsl_version = fsl_mpic_get_version(mpic);
1390 
1391                 /* Error interrupt mask register (EIMR) is required for
1392                  * handling individual device error interrupts. EIMR
1393                  * was added in MPIC version 4.1.
1394                  *
1395                  * Over here we reserve vector number space for error
1396                  * interrupt vectors. This space is stolen from the
1397                  * global vector number space, as in case of ipis
1398                  * and timer interrupts.
1399                  *
1400                  * Available vector space = intvec_top - 12, where 12
1401                  * is the number of vectors which have been consumed by
1402                  * ipis and timer interrupts.
1403                  */
1404                 if (fsl_version >= 0x401) {
1405                         ret = mpic_setup_error_int(mpic, intvec_top - 12);
1406                         if (ret)
1407                                 return NULL;
1408                 }
1409 
1410         }
1411 
1412         /*
1413          * EPR is only available starting with v4.0.  To support
1414          * platforms that don't know the MPIC version at compile-time,
1415          * such as qemu-e500, turn off coreint if this MPIC doesn't
1416          * support it.  Note that we never enable it if it wasn't
1417          * requested in the first place.
1418          *
1419          * This is done outside the MPIC_FSL check, so that we
1420          * also disable coreint if the MPIC node doesn't have
1421          * an "fsl,mpic" compatible at all.  This will be the case
1422          * with device trees generated by older versions of QEMU.
1423          * fsl_version will be zero if MPIC_FSL is not set.
1424          */
1425         if (fsl_version < 0x400 && (flags & MPIC_ENABLE_COREINT)) {
1426                 WARN_ON(ppc_md.get_irq != mpic_get_coreint_irq);
1427                 ppc_md.get_irq = mpic_get_irq;
1428         }
1429 
1430         /* Reset */
1431 
1432         /* When using a device-node, reset requests are only honored if the MPIC
1433          * is allowed to reset.
1434          */
1435         if (!(mpic->flags & MPIC_NO_RESET)) {
1436                 printk(KERN_DEBUG "mpic: Resetting\n");
1437                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1438                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1439                            | MPIC_GREG_GCONF_RESET);
1440                 while( mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1441                        & MPIC_GREG_GCONF_RESET)
1442                         mb();
1443         }
1444 
1445         /* CoreInt */
1446         if (mpic->flags & MPIC_ENABLE_COREINT)
1447                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1448                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1449                            | MPIC_GREG_GCONF_COREINT);
1450 
1451         if (mpic->flags & MPIC_ENABLE_MCK)
1452                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1453                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1454                            | MPIC_GREG_GCONF_MCK);
1455 
1456         /*
1457          * The MPIC driver will crash if there are more cores than we
1458          * can initialize, so we may as well catch that problem here.
1459          */
1460         BUG_ON(num_possible_cpus() > MPIC_MAX_CPUS);
1461 
1462         /* Map the per-CPU registers */
1463         for_each_possible_cpu(i) {
1464                 unsigned int cpu = get_hard_smp_processor_id(i);
1465 
1466                 mpic_map(mpic, mpic->paddr, &mpic->cpuregs[cpu],
1467                          MPIC_INFO(CPU_BASE) + cpu * MPIC_INFO(CPU_STRIDE),
1468                          0x1000);
1469         }
1470 
1471         /*
1472          * Read feature register.  For non-ISU MPICs, num sources as well. On
1473          * ISU MPICs, sources are counted as ISUs are added
1474          */
1475         greg_feature = mpic_read(mpic->gregs, MPIC_INFO(GREG_FEATURE_0));
1476 
1477         /*
1478          * By default, the last source number comes from the MPIC, but the
1479          * device-tree and board support code can override it on buggy hw.
1480          * If we get passed an isu_size (multi-isu MPIC) then we use that
1481          * as a default instead of the value read from the HW.
1482          */
1483         last_irq = (greg_feature & MPIC_GREG_FEATURE_LAST_SRC_MASK)
1484                                 >> MPIC_GREG_FEATURE_LAST_SRC_SHIFT;
1485         if (isu_size)
1486                 last_irq = isu_size  * MPIC_MAX_ISU - 1;
1487         of_property_read_u32(mpic->node, "last-interrupt-source", &last_irq);
1488         if (irq_count)
1489                 last_irq = irq_count - 1;
1490 
1491         /* Initialize main ISU if none provided */
1492         if (!isu_size) {
1493                 isu_size = last_irq + 1;
1494                 mpic->num_sources = isu_size;
1495                 mpic_map(mpic, mpic->paddr, &mpic->isus[0],
1496                                 MPIC_INFO(IRQ_BASE),
1497                                 MPIC_INFO(IRQ_STRIDE) * isu_size);
1498         }
1499 
1500         mpic->isu_size = isu_size;
1501         mpic->isu_shift = 1 + __ilog2(mpic->isu_size - 1);
1502         mpic->isu_mask = (1 << mpic->isu_shift) - 1;
1503 
1504         mpic->irqhost = irq_domain_add_linear(mpic->node,
1505                                        intvec_top,
1506                                        &mpic_host_ops, mpic);
1507 
1508         /*
1509          * FIXME: The code leaks the MPIC object and mappings here; this
1510          * is very unlikely to fail but it ought to be fixed anyways.
1511          */
1512         if (mpic->irqhost == NULL)
1513                 return NULL;
1514 
1515         /* Display version */
1516         switch (greg_feature & MPIC_GREG_FEATURE_VERSION_MASK) {
1517         case 1:
1518                 vers = "1.0";
1519                 break;
1520         case 2:
1521                 vers = "1.2";
1522                 break;
1523         case 3:
1524                 vers = "1.3";
1525                 break;
1526         default:
1527                 vers = "<unknown>";
1528                 break;
1529         }
1530         printk(KERN_INFO "mpic: Setting up MPIC \"%s\" version %s at %llx,"
1531                " max %d CPUs\n",
1532                name, vers, (unsigned long long)mpic->paddr, num_possible_cpus());
1533         printk(KERN_INFO "mpic: ISU size: %d, shift: %d, mask: %x\n",
1534                mpic->isu_size, mpic->isu_shift, mpic->isu_mask);
1535 
1536         mpic->next = mpics;
1537         mpics = mpic;
1538 
1539         if (!(mpic->flags & MPIC_SECONDARY)) {
1540                 mpic_primary = mpic;
1541                 irq_set_default_host(mpic->irqhost);
1542         }
1543 
1544         return mpic;
1545 
1546 err_of_node_put:
1547         of_node_put(node);
1548         return NULL;
1549 }
1550 
1551 void __init mpic_assign_isu(struct mpic *mpic, unsigned int isu_num,
1552                             phys_addr_t paddr)
1553 {
1554         unsigned int isu_first = isu_num * mpic->isu_size;
1555 
1556         BUG_ON(isu_num >= MPIC_MAX_ISU);
1557 
1558         mpic_map(mpic,
1559                  paddr, &mpic->isus[isu_num], 0,
1560                  MPIC_INFO(IRQ_STRIDE) * mpic->isu_size);
1561 
1562         if ((isu_first + mpic->isu_size) > mpic->num_sources)
1563                 mpic->num_sources = isu_first + mpic->isu_size;
1564 }
1565 
1566 void __init mpic_init(struct mpic *mpic)
1567 {
1568         int i, cpu;
1569         int num_timers = 4;
1570 
1571         BUG_ON(mpic->num_sources == 0);
1572 
1573         printk(KERN_INFO "mpic: Initializing for %d sources\n", mpic->num_sources);
1574 
1575         /* Set current processor priority to max */
1576         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1577 
1578         if (mpic->flags & MPIC_FSL) {
1579                 u32 version = fsl_mpic_get_version(mpic);
1580 
1581                 /*
1582                  * Timer group B is present at the latest in MPIC 3.1 (e.g.
1583                  * mpc8536).  It is not present in MPIC 2.0 (e.g. mpc8544).
1584                  * I don't know about the status of intermediate versions (or
1585                  * whether they even exist).
1586                  */
1587                 if (version >= 0x0301)
1588                         num_timers = 8;
1589         }
1590 
1591         /* Initialize timers to our reserved vectors and mask them for now */
1592         for (i = 0; i < num_timers; i++) {
1593                 unsigned int offset = mpic_tm_offset(mpic, i);
1594 
1595                 mpic_write(mpic->tmregs,
1596                            offset + MPIC_INFO(TIMER_DESTINATION),
1597                            1 << hard_smp_processor_id());
1598                 mpic_write(mpic->tmregs,
1599                            offset + MPIC_INFO(TIMER_VECTOR_PRI),
1600                            MPIC_VECPRI_MASK |
1601                            (9 << MPIC_VECPRI_PRIORITY_SHIFT) |
1602                            (mpic->timer_vecs[0] + i));
1603         }
1604 
1605         /* Initialize IPIs to our reserved vectors and mark them disabled for now */
1606         mpic_test_broken_ipi(mpic);
1607         for (i = 0; i < 4; i++) {
1608                 mpic_ipi_write(i,
1609                                MPIC_VECPRI_MASK |
1610                                (10 << MPIC_VECPRI_PRIORITY_SHIFT) |
1611                                (mpic->ipi_vecs[0] + i));
1612         }
1613 
1614         /* Do the HT PIC fixups on U3 broken mpic */
1615         DBG("MPIC flags: %x\n", mpic->flags);
1616         if ((mpic->flags & MPIC_U3_HT_IRQS) && !(mpic->flags & MPIC_SECONDARY)) {
1617                 mpic_scan_ht_pics(mpic);
1618                 mpic_u3msi_init(mpic);
1619         }
1620 
1621         mpic_pasemi_msi_init(mpic);
1622 
1623         cpu = mpic_processor_id(mpic);
1624 
1625         if (!(mpic->flags & MPIC_NO_RESET)) {
1626                 for (i = 0; i < mpic->num_sources; i++) {
1627                         /* start with vector = source number, and masked */
1628                         u32 vecpri = MPIC_VECPRI_MASK | i |
1629                                 (8 << MPIC_VECPRI_PRIORITY_SHIFT);
1630 
1631                         /* check if protected */
1632                         if (mpic->protected && test_bit(i, mpic->protected))
1633                                 continue;
1634                         /* init hw */
1635                         mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI), vecpri);
1636                         mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION), 1 << cpu);
1637                 }
1638         }
1639 
1640         /* Init spurious vector */
1641         mpic_write(mpic->gregs, MPIC_INFO(GREG_SPURIOUS), mpic->spurious_vec);
1642 
1643         /* Disable 8259 passthrough, if supported */
1644         if (!(mpic->flags & MPIC_NO_PTHROU_DIS))
1645                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1646                            mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1647                            | MPIC_GREG_GCONF_8259_PTHROU_DIS);
1648 
1649         if (mpic->flags & MPIC_NO_BIAS)
1650                 mpic_write(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0),
1651                         mpic_read(mpic->gregs, MPIC_INFO(GREG_GLOBAL_CONF_0))
1652                         | MPIC_GREG_GCONF_NO_BIAS);
1653 
1654         /* Set current processor priority to 0 */
1655         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1656 
1657 #ifdef CONFIG_PM
1658         /* allocate memory to save mpic state */
1659         mpic->save_data = kmalloc(mpic->num_sources * sizeof(*mpic->save_data),
1660                                   GFP_KERNEL);
1661         BUG_ON(mpic->save_data == NULL);
1662 #endif
1663 
1664         /* Check if this MPIC is chained from a parent interrupt controller */
1665         if (mpic->flags & MPIC_SECONDARY) {
1666                 int virq = irq_of_parse_and_map(mpic->node, 0);
1667                 if (virq != NO_IRQ) {
1668                         printk(KERN_INFO "%s: hooking up to IRQ %d\n",
1669                                         mpic->node->full_name, virq);
1670                         irq_set_handler_data(virq, mpic);
1671                         irq_set_chained_handler(virq, &mpic_cascade);
1672                 }
1673         }
1674 
1675         /* FSL mpic error interrupt intialization */
1676         if (mpic->flags & MPIC_FSL_HAS_EIMR)
1677                 mpic_err_int_init(mpic, MPIC_FSL_ERR_INT);
1678 }
1679 
1680 void __init mpic_set_clk_ratio(struct mpic *mpic, u32 clock_ratio)
1681 {
1682         u32 v;
1683 
1684         v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1685         v &= ~MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO_MASK;
1686         v |= MPIC_GREG_GLOBAL_CONF_1_CLK_RATIO(clock_ratio);
1687         mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1688 }
1689 
1690 void __init mpic_set_serial_int(struct mpic *mpic, int enable)
1691 {
1692         unsigned long flags;
1693         u32 v;
1694 
1695         raw_spin_lock_irqsave(&mpic_lock, flags);
1696         v = mpic_read(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1);
1697         if (enable)
1698                 v |= MPIC_GREG_GLOBAL_CONF_1_SIE;
1699         else
1700                 v &= ~MPIC_GREG_GLOBAL_CONF_1_SIE;
1701         mpic_write(mpic->gregs, MPIC_GREG_GLOBAL_CONF_1, v);
1702         raw_spin_unlock_irqrestore(&mpic_lock, flags);
1703 }
1704 
1705 void mpic_irq_set_priority(unsigned int irq, unsigned int pri)
1706 {
1707         struct mpic *mpic = mpic_find(irq);
1708         unsigned int src = virq_to_hw(irq);
1709         unsigned long flags;
1710         u32 reg;
1711 
1712         if (!mpic)
1713                 return;
1714 
1715         raw_spin_lock_irqsave(&mpic_lock, flags);
1716         if (mpic_is_ipi(mpic, src)) {
1717                 reg = mpic_ipi_read(src - mpic->ipi_vecs[0]) &
1718                         ~MPIC_VECPRI_PRIORITY_MASK;
1719                 mpic_ipi_write(src - mpic->ipi_vecs[0],
1720                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1721         } else if (mpic_is_tm(mpic, src)) {
1722                 reg = mpic_tm_read(src - mpic->timer_vecs[0]) &
1723                         ~MPIC_VECPRI_PRIORITY_MASK;
1724                 mpic_tm_write(src - mpic->timer_vecs[0],
1725                               reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1726         } else {
1727                 reg = mpic_irq_read(src, MPIC_INFO(IRQ_VECTOR_PRI))
1728                         & ~MPIC_VECPRI_PRIORITY_MASK;
1729                 mpic_irq_write(src, MPIC_INFO(IRQ_VECTOR_PRI),
1730                                reg | (pri << MPIC_VECPRI_PRIORITY_SHIFT));
1731         }
1732         raw_spin_unlock_irqrestore(&mpic_lock, flags);
1733 }
1734 
1735 void mpic_setup_this_cpu(void)
1736 {
1737 #ifdef CONFIG_SMP
1738         struct mpic *mpic = mpic_primary;
1739         unsigned long flags;
1740         u32 msk = 1 << hard_smp_processor_id();
1741         unsigned int i;
1742 
1743         BUG_ON(mpic == NULL);
1744 
1745         DBG("%s: setup_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1746 
1747         raw_spin_lock_irqsave(&mpic_lock, flags);
1748 
1749         /* let the mpic know we want intrs. default affinity is 0xffffffff
1750          * until changed via /proc. That's how it's done on x86. If we want
1751          * it differently, then we should make sure we also change the default
1752          * values of irq_desc[].affinity in irq.c.
1753          */
1754         if (distribute_irqs && !(mpic->flags & MPIC_SINGLE_DEST_CPU)) {
1755                 for (i = 0; i < mpic->num_sources ; i++)
1756                         mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1757                                 mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) | msk);
1758         }
1759 
1760         /* Set current processor priority to 0 */
1761         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0);
1762 
1763         raw_spin_unlock_irqrestore(&mpic_lock, flags);
1764 #endif /* CONFIG_SMP */
1765 }
1766 
1767 int mpic_cpu_get_priority(void)
1768 {
1769         struct mpic *mpic = mpic_primary;
1770 
1771         return mpic_cpu_read(MPIC_INFO(CPU_CURRENT_TASK_PRI));
1772 }
1773 
1774 void mpic_cpu_set_priority(int prio)
1775 {
1776         struct mpic *mpic = mpic_primary;
1777 
1778         prio &= MPIC_CPU_TASKPRI_MASK;
1779         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), prio);
1780 }
1781 
1782 void mpic_teardown_this_cpu(int secondary)
1783 {
1784         struct mpic *mpic = mpic_primary;
1785         unsigned long flags;
1786         u32 msk = 1 << hard_smp_processor_id();
1787         unsigned int i;
1788 
1789         BUG_ON(mpic == NULL);
1790 
1791         DBG("%s: teardown_this_cpu(%d)\n", mpic->name, hard_smp_processor_id());
1792         raw_spin_lock_irqsave(&mpic_lock, flags);
1793 
1794         /* let the mpic know we don't want intrs.  */
1795         for (i = 0; i < mpic->num_sources ; i++)
1796                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
1797                         mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION)) & ~msk);
1798 
1799         /* Set current processor priority to max */
1800         mpic_cpu_write(MPIC_INFO(CPU_CURRENT_TASK_PRI), 0xf);
1801         /* We need to EOI the IPI since not all platforms reset the MPIC
1802          * on boot and new interrupts wouldn't get delivered otherwise.
1803          */
1804         mpic_eoi(mpic);
1805 
1806         raw_spin_unlock_irqrestore(&mpic_lock, flags);
1807 }
1808 
1809 
1810 static unsigned int _mpic_get_one_irq(struct mpic *mpic, int reg)
1811 {
1812         u32 src;
1813 
1814         src = mpic_cpu_read(reg) & MPIC_INFO(VECPRI_VECTOR_MASK);
1815 #ifdef DEBUG_LOW
1816         DBG("%s: get_one_irq(reg 0x%x): %d\n", mpic->name, reg, src);
1817 #endif
1818         if (unlikely(src == mpic->spurious_vec)) {
1819                 if (mpic->flags & MPIC_SPV_EOI)
1820                         mpic_eoi(mpic);
1821                 return NO_IRQ;
1822         }
1823         if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1824                 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1825                                    mpic->name, (int)src);
1826                 mpic_eoi(mpic);
1827                 return NO_IRQ;
1828         }
1829 
1830         return irq_linear_revmap(mpic->irqhost, src);
1831 }
1832 
1833 unsigned int mpic_get_one_irq(struct mpic *mpic)
1834 {
1835         return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_INTACK));
1836 }
1837 
1838 unsigned int mpic_get_irq(void)
1839 {
1840         struct mpic *mpic = mpic_primary;
1841 
1842         BUG_ON(mpic == NULL);
1843 
1844         return mpic_get_one_irq(mpic);
1845 }
1846 
1847 unsigned int mpic_get_coreint_irq(void)
1848 {
1849 #ifdef CONFIG_BOOKE
1850         struct mpic *mpic = mpic_primary;
1851         u32 src;
1852 
1853         BUG_ON(mpic == NULL);
1854 
1855         src = mfspr(SPRN_EPR);
1856 
1857         if (unlikely(src == mpic->spurious_vec)) {
1858                 if (mpic->flags & MPIC_SPV_EOI)
1859                         mpic_eoi(mpic);
1860                 return NO_IRQ;
1861         }
1862         if (unlikely(mpic->protected && test_bit(src, mpic->protected))) {
1863                 printk_ratelimited(KERN_WARNING "%s: Got protected source %d !\n",
1864                                    mpic->name, (int)src);
1865                 return NO_IRQ;
1866         }
1867 
1868         return irq_linear_revmap(mpic->irqhost, src);
1869 #else
1870         return NO_IRQ;
1871 #endif
1872 }
1873 
1874 unsigned int mpic_get_mcirq(void)
1875 {
1876         struct mpic *mpic = mpic_primary;
1877 
1878         BUG_ON(mpic == NULL);
1879 
1880         return _mpic_get_one_irq(mpic, MPIC_INFO(CPU_MCACK));
1881 }
1882 
1883 #ifdef CONFIG_SMP
1884 void mpic_request_ipis(void)
1885 {
1886         struct mpic *mpic = mpic_primary;
1887         int i;
1888         BUG_ON(mpic == NULL);
1889 
1890         printk(KERN_INFO "mpic: requesting IPIs...\n");
1891 
1892         for (i = 0; i < 4; i++) {
1893                 unsigned int vipi = irq_create_mapping(mpic->irqhost,
1894                                                        mpic->ipi_vecs[0] + i);
1895                 if (vipi == NO_IRQ) {
1896                         printk(KERN_ERR "Failed to map %s\n", smp_ipi_name[i]);
1897                         continue;
1898                 }
1899                 smp_request_message_ipi(vipi, i);
1900         }
1901 }
1902 
1903 void smp_mpic_message_pass(int cpu, int msg)
1904 {
1905         struct mpic *mpic = mpic_primary;
1906         u32 physmask;
1907 
1908         BUG_ON(mpic == NULL);
1909 
1910         /* make sure we're sending something that translates to an IPI */
1911         if ((unsigned int)msg > 3) {
1912                 printk("SMP %d: smp_message_pass: unknown msg %d\n",
1913                        smp_processor_id(), msg);
1914                 return;
1915         }
1916 
1917 #ifdef DEBUG_IPI
1918         DBG("%s: send_ipi(ipi_no: %d)\n", mpic->name, msg);
1919 #endif
1920 
1921         physmask = 1 << get_hard_smp_processor_id(cpu);
1922 
1923         mpic_cpu_write(MPIC_INFO(CPU_IPI_DISPATCH_0) +
1924                        msg * MPIC_INFO(CPU_IPI_DISPATCH_STRIDE), physmask);
1925 }
1926 
1927 int __init smp_mpic_probe(void)
1928 {
1929         int nr_cpus;
1930 
1931         DBG("smp_mpic_probe()...\n");
1932 
1933         nr_cpus = cpumask_weight(cpu_possible_mask);
1934 
1935         DBG("nr_cpus: %d\n", nr_cpus);
1936 
1937         if (nr_cpus > 1)
1938                 mpic_request_ipis();
1939 
1940         return nr_cpus;
1941 }
1942 
1943 void smp_mpic_setup_cpu(int cpu)
1944 {
1945         mpic_setup_this_cpu();
1946 }
1947 
1948 void mpic_reset_core(int cpu)
1949 {
1950         struct mpic *mpic = mpic_primary;
1951         u32 pir;
1952         int cpuid = get_hard_smp_processor_id(cpu);
1953         int i;
1954 
1955         /* Set target bit for core reset */
1956         pir = mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1957         pir |= (1 << cpuid);
1958         mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1959         mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1960 
1961         /* Restore target bit after reset complete */
1962         pir &= ~(1 << cpuid);
1963         mpic_write(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT), pir);
1964         mpic_read(mpic->gregs, MPIC_INFO(GREG_PROCESSOR_INIT));
1965 
1966         /* Perform 15 EOI on each reset core to clear pending interrupts.
1967          * This is required for FSL CoreNet based devices */
1968         if (mpic->flags & MPIC_FSL) {
1969                 for (i = 0; i < 15; i++) {
1970                         _mpic_write(mpic->reg_type, &mpic->cpuregs[cpuid],
1971                                       MPIC_CPU_EOI, 0);
1972                 }
1973         }
1974 }
1975 #endif /* CONFIG_SMP */
1976 
1977 #ifdef CONFIG_PM
1978 static void mpic_suspend_one(struct mpic *mpic)
1979 {
1980         int i;
1981 
1982         for (i = 0; i < mpic->num_sources; i++) {
1983                 mpic->save_data[i].vecprio =
1984                         mpic_irq_read(i, MPIC_INFO(IRQ_VECTOR_PRI));
1985                 mpic->save_data[i].dest =
1986                         mpic_irq_read(i, MPIC_INFO(IRQ_DESTINATION));
1987         }
1988 }
1989 
1990 static int mpic_suspend(void)
1991 {
1992         struct mpic *mpic = mpics;
1993 
1994         while (mpic) {
1995                 mpic_suspend_one(mpic);
1996                 mpic = mpic->next;
1997         }
1998 
1999         return 0;
2000 }
2001 
2002 static void mpic_resume_one(struct mpic *mpic)
2003 {
2004         int i;
2005 
2006         for (i = 0; i < mpic->num_sources; i++) {
2007                 mpic_irq_write(i, MPIC_INFO(IRQ_VECTOR_PRI),
2008                                mpic->save_data[i].vecprio);
2009                 mpic_irq_write(i, MPIC_INFO(IRQ_DESTINATION),
2010                                mpic->save_data[i].dest);
2011 
2012 #ifdef CONFIG_MPIC_U3_HT_IRQS
2013         if (mpic->fixups) {
2014                 struct mpic_irq_fixup *fixup = &mpic->fixups[i];
2015 
2016                 if (fixup->base) {
2017                         /* we use the lowest bit in an inverted meaning */
2018                         if ((mpic->save_data[i].fixup_data & 1) == 0)
2019                                 continue;
2020 
2021                         /* Enable and configure */
2022                         writeb(0x10 + 2 * fixup->index, fixup->base + 2);
2023 
2024                         writel(mpic->save_data[i].fixup_data & ~1,
2025                                fixup->base + 4);
2026                 }
2027         }
2028 #endif
2029         } /* end for loop */
2030 }
2031 
2032 static void mpic_resume(void)
2033 {
2034         struct mpic *mpic = mpics;
2035 
2036         while (mpic) {
2037                 mpic_resume_one(mpic);
2038                 mpic = mpic->next;
2039         }
2040 }
2041 
2042 static struct syscore_ops mpic_syscore_ops = {
2043         .resume = mpic_resume,
2044         .suspend = mpic_suspend,
2045 };
2046 
2047 static int mpic_init_sys(void)
2048 {
2049         register_syscore_ops(&mpic_syscore_ops);
2050         subsys_system_register(&mpic_subsys, NULL);
2051 
2052         return 0;
2053 }
2054 
2055 device_initcall(mpic_init_sys);
2056 #endif
2057 

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