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Linux/arch/powerpc/platforms/85xx/p1022_ds.c

  1 /*
  2  * P1022DS board specific routines
  3  *
  4  * Authors: Travis Wheatley <travis.wheatley@freescale.com>
  5  *          Dave Liu <daveliu@freescale.com>
  6  *          Timur Tabi <timur@freescale.com>
  7  *
  8  * Copyright 2010 Freescale Semiconductor, Inc.
  9  *
 10  * This file is taken from the Freescale P1022DS BSP, with modifications:
 11  * 2) No AMP support
 12  * 3) No PCI endpoint support
 13  *
 14  * This file is licensed under the terms of the GNU General Public License
 15  * version 2.  This program is licensed "as is" without any warranty of any
 16  * kind, whether express or implied.
 17  */
 18 
 19 #include <linux/pci.h>
 20 #include <linux/of_platform.h>
 21 #include <asm/div64.h>
 22 #include <asm/mpic.h>
 23 #include <asm/swiotlb.h>
 24 
 25 #include <sysdev/fsl_soc.h>
 26 #include <sysdev/fsl_pci.h>
 27 #include <asm/udbg.h>
 28 #include <asm/fsl_guts.h>
 29 #include <asm/fsl_lbc.h>
 30 #include "smp.h"
 31 
 32 #include "mpc85xx.h"
 33 
 34 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
 35 
 36 #define PMUXCR_ELBCDIU_MASK     0xc0000000
 37 #define PMUXCR_ELBCDIU_NOR16    0x80000000
 38 #define PMUXCR_ELBCDIU_DIU      0x40000000
 39 
 40 /*
 41  * Board-specific initialization of the DIU.  This code should probably be
 42  * executed when the DIU is opened, rather than in arch code, but the DIU
 43  * driver does not have a mechanism for this (yet).
 44  *
 45  * This is especially problematic on the P1022DS because the local bus (eLBC)
 46  * and the DIU video signals share the same pins, which means that enabling the
 47  * DIU will disable access to NOR flash.
 48  */
 49 
 50 /* DIU Pixel Clock bits of the CLKDVDR Global Utilities register */
 51 #define CLKDVDR_PXCKEN          0x80000000
 52 #define CLKDVDR_PXCKINV         0x10000000
 53 #define CLKDVDR_PXCKDLY         0x06000000
 54 #define CLKDVDR_PXCLK_MASK      0x00FF0000
 55 
 56 /* Some ngPIXIS register definitions */
 57 #define PX_CTL          3
 58 #define PX_BRDCFG0      8
 59 #define PX_BRDCFG1      9
 60 
 61 #define PX_BRDCFG0_ELBC_SPI_MASK        0xc0
 62 #define PX_BRDCFG0_ELBC_SPI_ELBC        0x00
 63 #define PX_BRDCFG0_ELBC_SPI_NULL        0xc0
 64 #define PX_BRDCFG0_ELBC_DIU             0x02
 65 
 66 #define PX_BRDCFG1_DVIEN        0x80
 67 #define PX_BRDCFG1_DFPEN        0x40
 68 #define PX_BRDCFG1_BACKLIGHT    0x20
 69 #define PX_BRDCFG1_DDCEN        0x10
 70 
 71 #define PX_CTL_ALTACC           0x80
 72 
 73 /*
 74  * DIU Area Descriptor
 75  *
 76  * Note that we need to byte-swap the value before it's written to the AD
 77  * register.  So even though the registers don't look like they're in the same
 78  * bit positions as they are on the MPC8610, the same value is written to the
 79  * AD register on the MPC8610 and on the P1022.
 80  */
 81 #define AD_BYTE_F               0x10000000
 82 #define AD_ALPHA_C_MASK         0x0E000000
 83 #define AD_ALPHA_C_SHIFT        25
 84 #define AD_BLUE_C_MASK          0x01800000
 85 #define AD_BLUE_C_SHIFT         23
 86 #define AD_GREEN_C_MASK         0x00600000
 87 #define AD_GREEN_C_SHIFT        21
 88 #define AD_RED_C_MASK           0x00180000
 89 #define AD_RED_C_SHIFT          19
 90 #define AD_PALETTE              0x00040000
 91 #define AD_PIXEL_S_MASK         0x00030000
 92 #define AD_PIXEL_S_SHIFT        16
 93 #define AD_COMP_3_MASK          0x0000F000
 94 #define AD_COMP_3_SHIFT         12
 95 #define AD_COMP_2_MASK          0x00000F00
 96 #define AD_COMP_2_SHIFT         8
 97 #define AD_COMP_1_MASK          0x000000F0
 98 #define AD_COMP_1_SHIFT         4
 99 #define AD_COMP_0_MASK          0x0000000F
100 #define AD_COMP_0_SHIFT         0
101 
102 #define MAKE_AD(alpha, red, blue, green, size, c0, c1, c2, c3) \
103         cpu_to_le32(AD_BYTE_F | (alpha << AD_ALPHA_C_SHIFT) | \
104         (blue << AD_BLUE_C_SHIFT) | (green << AD_GREEN_C_SHIFT) | \
105         (red << AD_RED_C_SHIFT) | (c3 << AD_COMP_3_SHIFT) | \
106         (c2 << AD_COMP_2_SHIFT) | (c1 << AD_COMP_1_SHIFT) | \
107         (c0 << AD_COMP_0_SHIFT) | (size << AD_PIXEL_S_SHIFT))
108 
109 struct fsl_law {
110         u32     lawbar;
111         u32     reserved1;
112         u32     lawar;
113         u32     reserved[5];
114 };
115 
116 #define LAWBAR_MASK     0x00F00000
117 #define LAWBAR_SHIFT    12
118 
119 #define LAWAR_EN        0x80000000
120 #define LAWAR_TGT_MASK  0x01F00000
121 #define LAW_TRGT_IF_LBC (0x04 << 20)
122 
123 #define LAWAR_MASK      (LAWAR_EN | LAWAR_TGT_MASK)
124 #define LAWAR_MATCH     (LAWAR_EN | LAW_TRGT_IF_LBC)
125 
126 #define BR_BA           0xFFFF8000
127 
128 /*
129  * Map a BRx value to a physical address
130  *
131  * The localbus BRx registers only store the lower 32 bits of the address.  To
132  * obtain the upper four bits, we need to scan the LAW table.  The entry which
133  * maps to the localbus will contain the upper four bits.
134  */
135 static phys_addr_t lbc_br_to_phys(const void *ecm, unsigned int count, u32 br)
136 {
137 #ifndef CONFIG_PHYS_64BIT
138         /*
139          * If we only have 32-bit addressing, then the BRx address *is* the
140          * physical address.
141          */
142         return br & BR_BA;
143 #else
144         const struct fsl_law *law = ecm + 0xc08;
145         unsigned int i;
146 
147         for (i = 0; i < count; i++) {
148                 u64 lawbar = in_be32(&law[i].lawbar);
149                 u32 lawar = in_be32(&law[i].lawar);
150 
151                 if ((lawar & LAWAR_MASK) == LAWAR_MATCH)
152                         /* Extract the upper four bits */
153                         return (br & BR_BA) | ((lawbar & LAWBAR_MASK) << 12);
154         }
155 
156         return 0;
157 #endif
158 }
159 
160 /**
161  * p1022ds_set_monitor_port: switch the output to a different monitor port
162  */
163 static void p1022ds_set_monitor_port(enum fsl_diu_monitor_port port)
164 {
165         struct device_node *guts_node;
166         struct device_node *lbc_node = NULL;
167         struct device_node *law_node = NULL;
168         struct ccsr_guts __iomem *guts;
169         struct fsl_lbc_regs *lbc = NULL;
170         void *ecm = NULL;
171         u8 __iomem *lbc_lcs0_ba = NULL;
172         u8 __iomem *lbc_lcs1_ba = NULL;
173         phys_addr_t cs0_addr, cs1_addr;
174         u32 br0, or0, br1, or1;
175         const __be32 *iprop;
176         unsigned int num_laws;
177         u8 b;
178 
179         /* Map the global utilities registers. */
180         guts_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
181         if (!guts_node) {
182                 pr_err("p1022ds: missing global utilities device node\n");
183                 return;
184         }
185 
186         guts = of_iomap(guts_node, 0);
187         if (!guts) {
188                 pr_err("p1022ds: could not map global utilities device\n");
189                 goto exit;
190         }
191 
192         lbc_node = of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
193         if (!lbc_node) {
194                 pr_err("p1022ds: missing localbus node\n");
195                 goto exit;
196         }
197 
198         lbc = of_iomap(lbc_node, 0);
199         if (!lbc) {
200                 pr_err("p1022ds: could not map localbus node\n");
201                 goto exit;
202         }
203 
204         law_node = of_find_compatible_node(NULL, NULL, "fsl,ecm-law");
205         if (!law_node) {
206                 pr_err("p1022ds: missing local access window node\n");
207                 goto exit;
208         }
209 
210         ecm = of_iomap(law_node, 0);
211         if (!ecm) {
212                 pr_err("p1022ds: could not map local access window node\n");
213                 goto exit;
214         }
215 
216         iprop = of_get_property(law_node, "fsl,num-laws", NULL);
217         if (!iprop) {
218                 pr_err("p1022ds: LAW node is missing fsl,num-laws property\n");
219                 goto exit;
220         }
221         num_laws = be32_to_cpup(iprop);
222 
223         /*
224          * Indirect mode requires both BR0 and BR1 to be set to "GPCM",
225          * otherwise writes to these addresses won't actually appear on the
226          * local bus, and so the PIXIS won't see them.
227          *
228          * In FCM mode, writes go to the NAND controller, which does not pass
229          * them to the localbus directly.  So we force BR0 and BR1 into GPCM
230          * mode, since we don't care about what's behind the localbus any
231          * more.
232          */
233         br0 = in_be32(&lbc->bank[0].br);
234         br1 = in_be32(&lbc->bank[1].br);
235         or0 = in_be32(&lbc->bank[0].or);
236         or1 = in_be32(&lbc->bank[1].or);
237 
238         /* Make sure CS0 and CS1 are programmed */
239         if (!(br0 & BR_V) || !(br1 & BR_V)) {
240                 pr_err("p1022ds: CS0 and/or CS1 is not programmed\n");
241                 goto exit;
242         }
243 
244         /*
245          * Use the existing BRx/ORx values if it's already GPCM. Otherwise,
246          * force the values to simple 32KB GPCM windows with the most
247          * conservative timing.
248          */
249         if ((br0 & BR_MSEL) != BR_MS_GPCM) {
250                 br0 = (br0 & BR_BA) | BR_V;
251                 or0 = 0xFFFF8000 | 0xFF7;
252                 out_be32(&lbc->bank[0].br, br0);
253                 out_be32(&lbc->bank[0].or, or0);
254         }
255         if ((br1 & BR_MSEL) != BR_MS_GPCM) {
256                 br1 = (br1 & BR_BA) | BR_V;
257                 or1 = 0xFFFF8000 | 0xFF7;
258                 out_be32(&lbc->bank[1].br, br1);
259                 out_be32(&lbc->bank[1].or, or1);
260         }
261 
262         cs0_addr = lbc_br_to_phys(ecm, num_laws, br0);
263         if (!cs0_addr) {
264                 pr_err("p1022ds: could not determine physical address for CS0"
265                        " (BR0=%08x)\n", br0);
266                 goto exit;
267         }
268         cs1_addr = lbc_br_to_phys(ecm, num_laws, br1);
269         if (!cs1_addr) {
270                 pr_err("p1022ds: could not determine physical address for CS1"
271                        " (BR1=%08x)\n", br1);
272                 goto exit;
273         }
274 
275         lbc_lcs0_ba = ioremap(cs0_addr, 1);
276         if (!lbc_lcs0_ba) {
277                 pr_err("p1022ds: could not ioremap CS0 address %llx\n",
278                        (unsigned long long)cs0_addr);
279                 goto exit;
280         }
281         lbc_lcs1_ba = ioremap(cs1_addr, 1);
282         if (!lbc_lcs1_ba) {
283                 pr_err("p1022ds: could not ioremap CS1 address %llx\n",
284                        (unsigned long long)cs1_addr);
285                 goto exit;
286         }
287 
288         /* Make sure we're in indirect mode first. */
289         if ((in_be32(&guts->pmuxcr) & PMUXCR_ELBCDIU_MASK) !=
290             PMUXCR_ELBCDIU_DIU) {
291                 struct device_node *pixis_node;
292                 void __iomem *pixis;
293 
294                 pixis_node =
295                         of_find_compatible_node(NULL, NULL, "fsl,p1022ds-fpga");
296                 if (!pixis_node) {
297                         pr_err("p1022ds: missing pixis node\n");
298                         goto exit;
299                 }
300 
301                 pixis = of_iomap(pixis_node, 0);
302                 of_node_put(pixis_node);
303                 if (!pixis) {
304                         pr_err("p1022ds: could not map pixis registers\n");
305                         goto exit;
306                 }
307 
308                 /* Enable indirect PIXIS mode.  */
309                 setbits8(pixis + PX_CTL, PX_CTL_ALTACC);
310                 iounmap(pixis);
311 
312                 /* Switch the board mux to the DIU */
313                 out_8(lbc_lcs0_ba, PX_BRDCFG0); /* BRDCFG0 */
314                 b = in_8(lbc_lcs1_ba);
315                 b |= PX_BRDCFG0_ELBC_DIU;
316                 out_8(lbc_lcs1_ba, b);
317 
318                 /* Set the chip mux to DIU mode. */
319                 clrsetbits_be32(&guts->pmuxcr, PMUXCR_ELBCDIU_MASK,
320                                 PMUXCR_ELBCDIU_DIU);
321                 in_be32(&guts->pmuxcr);
322         }
323 
324 
325         switch (port) {
326         case FSL_DIU_PORT_DVI:
327                 /* Enable the DVI port, disable the DFP and the backlight */
328                 out_8(lbc_lcs0_ba, PX_BRDCFG1);
329                 b = in_8(lbc_lcs1_ba);
330                 b &= ~(PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT);
331                 b |= PX_BRDCFG1_DVIEN;
332                 out_8(lbc_lcs1_ba, b);
333                 break;
334         case FSL_DIU_PORT_LVDS:
335                 /*
336                  * LVDS also needs backlight enabled, otherwise the display
337                  * will be blank.
338                  */
339                 /* Enable the DFP port, disable the DVI and the backlight */
340                 out_8(lbc_lcs0_ba, PX_BRDCFG1);
341                 b = in_8(lbc_lcs1_ba);
342                 b &= ~PX_BRDCFG1_DVIEN;
343                 b |= PX_BRDCFG1_DFPEN | PX_BRDCFG1_BACKLIGHT;
344                 out_8(lbc_lcs1_ba, b);
345                 break;
346         default:
347                 pr_err("p1022ds: unsupported monitor port %i\n", port);
348         }
349 
350 exit:
351         if (lbc_lcs1_ba)
352                 iounmap(lbc_lcs1_ba);
353         if (lbc_lcs0_ba)
354                 iounmap(lbc_lcs0_ba);
355         if (lbc)
356                 iounmap(lbc);
357         if (ecm)
358                 iounmap(ecm);
359         if (guts)
360                 iounmap(guts);
361 
362         of_node_put(law_node);
363         of_node_put(lbc_node);
364         of_node_put(guts_node);
365 }
366 
367 /**
368  * p1022ds_set_pixel_clock: program the DIU's clock
369  *
370  * @pixclock: the wavelength, in picoseconds, of the clock
371  */
372 void p1022ds_set_pixel_clock(unsigned int pixclock)
373 {
374         struct device_node *guts_np = NULL;
375         struct ccsr_guts __iomem *guts;
376         unsigned long freq;
377         u64 temp;
378         u32 pxclk;
379 
380         /* Map the global utilities registers. */
381         guts_np = of_find_compatible_node(NULL, NULL, "fsl,p1022-guts");
382         if (!guts_np) {
383                 pr_err("p1022ds: missing global utilities device node\n");
384                 return;
385         }
386 
387         guts = of_iomap(guts_np, 0);
388         of_node_put(guts_np);
389         if (!guts) {
390                 pr_err("p1022ds: could not map global utilities device\n");
391                 return;
392         }
393 
394         /* Convert pixclock from a wavelength to a frequency */
395         temp = 1000000000000ULL;
396         do_div(temp, pixclock);
397         freq = temp;
398 
399         /*
400          * 'pxclk' is the ratio of the platform clock to the pixel clock.
401          * This number is programmed into the CLKDVDR register, and the valid
402          * range of values is 2-255.
403          */
404         pxclk = DIV_ROUND_CLOSEST(fsl_get_sys_freq(), freq);
405         pxclk = clamp_t(u32, pxclk, 2, 255);
406 
407         /* Disable the pixel clock, and set it to non-inverted and no delay */
408         clrbits32(&guts->clkdvdr,
409                   CLKDVDR_PXCKEN | CLKDVDR_PXCKDLY | CLKDVDR_PXCLK_MASK);
410 
411         /* Enable the clock and set the pxclk */
412         setbits32(&guts->clkdvdr, CLKDVDR_PXCKEN | (pxclk << 16));
413 
414         iounmap(guts);
415 }
416 
417 /**
418  * p1022ds_valid_monitor_port: set the monitor port for sysfs
419  */
420 enum fsl_diu_monitor_port
421 p1022ds_valid_monitor_port(enum fsl_diu_monitor_port port)
422 {
423         switch (port) {
424         case FSL_DIU_PORT_DVI:
425         case FSL_DIU_PORT_LVDS:
426                 return port;
427         default:
428                 return FSL_DIU_PORT_DVI; /* Dual-link LVDS is not supported */
429         }
430 }
431 
432 #endif
433 
434 void __init p1022_ds_pic_init(void)
435 {
436         struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
437                 MPIC_SINGLE_DEST_CPU,
438                 0, 256, " OpenPIC  ");
439         BUG_ON(mpic == NULL);
440         mpic_init(mpic);
441 }
442 
443 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
444 
445 /* TRUE if there is a "video=fslfb" command-line parameter. */
446 static bool fslfb;
447 
448 /*
449  * Search for a "video=fslfb" command-line parameter, and set 'fslfb' to
450  * true if we find it.
451  *
452  * We need to use early_param() instead of __setup() because the normal
453  * __setup() gets called to late.  However, early_param() gets called very
454  * early, before the device tree is unflattened, so all we can do now is set a
455  * global variable.  Later on, p1022_ds_setup_arch() will use that variable
456  * to determine if we need to update the device tree.
457  */
458 static int __init early_video_setup(char *options)
459 {
460         fslfb = (strncmp(options, "fslfb:", 6) == 0);
461 
462         return 0;
463 }
464 early_param("video", early_video_setup);
465 
466 #endif
467 
468 /*
469  * Setup the architecture
470  */
471 static void __init p1022_ds_setup_arch(void)
472 {
473         if (ppc_md.progress)
474                 ppc_md.progress("p1022_ds_setup_arch()", 0);
475 
476 #if defined(CONFIG_FB_FSL_DIU) || defined(CONFIG_FB_FSL_DIU_MODULE)
477         diu_ops.set_monitor_port        = p1022ds_set_monitor_port;
478         diu_ops.set_pixel_clock         = p1022ds_set_pixel_clock;
479         diu_ops.valid_monitor_port      = p1022ds_valid_monitor_port;
480 
481         /*
482          * Disable the NOR and NAND flash nodes if there is video=fslfb...
483          * command-line parameter.  When the DIU is active, the localbus is
484          * unavailable, so we have to disable these nodes before the MTD
485          * driver loads.
486          */
487         if (fslfb) {
488                 struct device_node *np =
489                         of_find_compatible_node(NULL, NULL, "fsl,p1022-elbc");
490 
491                 if (np) {
492                         struct device_node *np2;
493 
494                         of_node_get(np);
495                         np2 = of_find_compatible_node(np, NULL, "cfi-flash");
496                         if (np2) {
497                                 static struct property nor_status = {
498                                         .name = "status",
499                                         .value = "disabled",
500                                         .length = sizeof("disabled"),
501                                 };
502 
503                                 /*
504                                  * of_update_property() is called before
505                                  * kmalloc() is available, so the 'new' object
506                                  * should be allocated in the global area.
507                                  * The easiest way is to do that is to
508                                  * allocate one static local variable for each
509                                  * call to this function.
510                                  */
511                                 pr_info("p1022ds: disabling %s node",
512                                         np2->full_name);
513                                 of_update_property(np2, &nor_status);
514                                 of_node_put(np2);
515                         }
516 
517                         of_node_get(np);
518                         np2 = of_find_compatible_node(np, NULL,
519                                                       "fsl,elbc-fcm-nand");
520                         if (np2) {
521                                 static struct property nand_status = {
522                                         .name = "status",
523                                         .value = "disabled",
524                                         .length = sizeof("disabled"),
525                                 };
526 
527                                 pr_info("p1022ds: disabling %s node",
528                                         np2->full_name);
529                                 of_update_property(np2, &nand_status);
530                                 of_node_put(np2);
531                         }
532 
533                         of_node_put(np);
534                 }
535 
536         }
537 
538 #endif
539 
540         mpc85xx_smp_init();
541 
542         fsl_pci_assign_primary();
543 
544         swiotlb_detect_4g();
545 
546         pr_info("Freescale P1022 DS reference board\n");
547 }
548 
549 machine_arch_initcall(p1022_ds, mpc85xx_common_publish_devices);
550 
551 machine_arch_initcall(p1022_ds, swiotlb_setup_bus_notifier);
552 
553 /*
554  * Called very early, device-tree isn't unflattened
555  */
556 static int __init p1022_ds_probe(void)
557 {
558         unsigned long root = of_get_flat_dt_root();
559 
560         return of_flat_dt_is_compatible(root, "fsl,p1022ds");
561 }
562 
563 define_machine(p1022_ds) {
564         .name                   = "P1022 DS",
565         .probe                  = p1022_ds_probe,
566         .setup_arch             = p1022_ds_setup_arch,
567         .init_IRQ               = p1022_ds_pic_init,
568 #ifdef CONFIG_PCI
569         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
570         .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
571 #endif
572         .get_irq                = mpic_get_irq,
573         .restart                = fsl_rstcr_restart,
574         .calibrate_decr         = generic_calibrate_decr,
575         .progress               = udbg_progress,
576 };
577 

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