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Linux/arch/powerpc/platforms/85xx/mpc85xx_mds.c

  1 /*
  2  * Copyright (C) 2006-2010, 2012-2013 Freescale Semiconductor, Inc.
  3  * All rights reserved.
  4  *
  5  * Author: Andy Fleming <afleming@freescale.com>
  6  *
  7  * Based on 83xx/mpc8360e_pb.c by:
  8  *         Li Yang <LeoLi@freescale.com>
  9  *         Yin Olivia <Hong-hua.Yin@freescale.com>
 10  *
 11  * Description:
 12  * MPC85xx MDS board specific routines.
 13  *
 14  * This program is free software; you can redistribute  it and/or modify it
 15  * under  the terms of  the GNU General  Public License as published by the
 16  * Free Software Foundation;  either version 2 of the  License, or (at your
 17  * option) any later version.
 18  */
 19 
 20 #include <linux/stddef.h>
 21 #include <linux/kernel.h>
 22 #include <linux/init.h>
 23 #include <linux/errno.h>
 24 #include <linux/reboot.h>
 25 #include <linux/pci.h>
 26 #include <linux/kdev_t.h>
 27 #include <linux/major.h>
 28 #include <linux/console.h>
 29 #include <linux/delay.h>
 30 #include <linux/seq_file.h>
 31 #include <linux/initrd.h>
 32 #include <linux/fsl_devices.h>
 33 #include <linux/of_platform.h>
 34 #include <linux/of_device.h>
 35 #include <linux/phy.h>
 36 #include <linux/memblock.h>
 37 
 38 #include <linux/atomic.h>
 39 #include <asm/time.h>
 40 #include <asm/io.h>
 41 #include <asm/machdep.h>
 42 #include <asm/pci-bridge.h>
 43 #include <asm/irq.h>
 44 #include <mm/mmu_decl.h>
 45 #include <asm/prom.h>
 46 #include <asm/udbg.h>
 47 #include <sysdev/fsl_soc.h>
 48 #include <sysdev/fsl_pci.h>
 49 #include <sysdev/simple_gpio.h>
 50 #include <asm/qe.h>
 51 #include <asm/qe_ic.h>
 52 #include <asm/mpic.h>
 53 #include <asm/swiotlb.h>
 54 #include <asm/fsl_guts.h>
 55 #include "smp.h"
 56 
 57 #include "mpc85xx.h"
 58 
 59 #undef DEBUG
 60 #ifdef DEBUG
 61 #define DBG(fmt...) udbg_printf(fmt)
 62 #else
 63 #define DBG(fmt...)
 64 #endif
 65 
 66 #define MV88E1111_SCR   0x10
 67 #define MV88E1111_SCR_125CLK    0x0010
 68 static int mpc8568_fixup_125_clock(struct phy_device *phydev)
 69 {
 70         int scr;
 71         int err;
 72 
 73         /* Workaround for the 125 CLK Toggle */
 74         scr = phy_read(phydev, MV88E1111_SCR);
 75 
 76         if (scr < 0)
 77                 return scr;
 78 
 79         err = phy_write(phydev, MV88E1111_SCR, scr & ~(MV88E1111_SCR_125CLK));
 80 
 81         if (err)
 82                 return err;
 83 
 84         err = phy_write(phydev, MII_BMCR, BMCR_RESET);
 85 
 86         if (err)
 87                 return err;
 88 
 89         scr = phy_read(phydev, MV88E1111_SCR);
 90 
 91         if (scr < 0)
 92                 return scr;
 93 
 94         err = phy_write(phydev, MV88E1111_SCR, scr | 0x0008);
 95 
 96         return err;
 97 }
 98 
 99 static int mpc8568_mds_phy_fixups(struct phy_device *phydev)
100 {
101         int temp;
102         int err;
103 
104         /* Errata */
105         err = phy_write(phydev,29, 0x0006);
106 
107         if (err)
108                 return err;
109 
110         temp = phy_read(phydev, 30);
111 
112         if (temp < 0)
113                 return temp;
114 
115         temp = (temp & (~0x8000)) | 0x4000;
116         err = phy_write(phydev,30, temp);
117 
118         if (err)
119                 return err;
120 
121         err = phy_write(phydev,29, 0x000a);
122 
123         if (err)
124                 return err;
125 
126         temp = phy_read(phydev, 30);
127 
128         if (temp < 0)
129                 return temp;
130 
131         temp = phy_read(phydev, 30);
132 
133         if (temp < 0)
134                 return temp;
135 
136         temp &= ~0x0020;
137 
138         err = phy_write(phydev,30,temp);
139 
140         if (err)
141                 return err;
142 
143         /* Disable automatic MDI/MDIX selection */
144         temp = phy_read(phydev, 16);
145 
146         if (temp < 0)
147                 return temp;
148 
149         temp &= ~0x0060;
150         err = phy_write(phydev,16,temp);
151 
152         return err;
153 }
154 
155 /* ************************************************************************
156  *
157  * Setup the architecture
158  *
159  */
160 #ifdef CONFIG_QUICC_ENGINE
161 static void __init mpc85xx_mds_reset_ucc_phys(void)
162 {
163         struct device_node *np;
164         static u8 __iomem *bcsr_regs;
165 
166         /* Map BCSR area */
167         np = of_find_node_by_name(NULL, "bcsr");
168         if (!np)
169                 return;
170 
171         bcsr_regs = of_iomap(np, 0);
172         of_node_put(np);
173         if (!bcsr_regs)
174                 return;
175 
176         if (machine_is(mpc8568_mds)) {
177 #define BCSR_UCC1_GETH_EN       (0x1 << 7)
178 #define BCSR_UCC2_GETH_EN       (0x1 << 7)
179 #define BCSR_UCC1_MODE_MSK      (0x3 << 4)
180 #define BCSR_UCC2_MODE_MSK      (0x3 << 0)
181 
182                 /* Turn off UCC1 & UCC2 */
183                 clrbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
184                 clrbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
185 
186                 /* Mode is RGMII, all bits clear */
187                 clrbits8(&bcsr_regs[11], BCSR_UCC1_MODE_MSK |
188                                          BCSR_UCC2_MODE_MSK);
189 
190                 /* Turn UCC1 & UCC2 on */
191                 setbits8(&bcsr_regs[8], BCSR_UCC1_GETH_EN);
192                 setbits8(&bcsr_regs[9], BCSR_UCC2_GETH_EN);
193         } else if (machine_is(mpc8569_mds)) {
194 #define BCSR7_UCC12_GETHnRST    (0x1 << 2)
195 #define BCSR8_UEM_MARVELL_RST   (0x1 << 1)
196 #define BCSR_UCC_RGMII          (0x1 << 6)
197 #define BCSR_UCC_RTBI           (0x1 << 5)
198                 /*
199                  * U-Boot mangles interrupt polarity for Marvell PHYs,
200                  * so reset built-in and UEM Marvell PHYs, this puts
201                  * the PHYs into their normal state.
202                  */
203                 clrbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
204                 setbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
205 
206                 setbits8(&bcsr_regs[7], BCSR7_UCC12_GETHnRST);
207                 clrbits8(&bcsr_regs[8], BCSR8_UEM_MARVELL_RST);
208 
209                 for_each_compatible_node(np, "network", "ucc_geth") {
210                         const unsigned int *prop;
211                         int ucc_num;
212 
213                         prop = of_get_property(np, "cell-index", NULL);
214                         if (prop == NULL)
215                                 continue;
216 
217                         ucc_num = *prop - 1;
218 
219                         prop = of_get_property(np, "phy-connection-type", NULL);
220                         if (prop == NULL)
221                                 continue;
222 
223                         if (strcmp("rtbi", (const char *)prop) == 0)
224                                 clrsetbits_8(&bcsr_regs[7 + ucc_num],
225                                         BCSR_UCC_RGMII, BCSR_UCC_RTBI);
226                 }
227         } else if (machine_is(p1021_mds)) {
228 #define BCSR11_ENET_MICRST     (0x1 << 5)
229                 /* Reset Micrel PHY */
230                 clrbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
231                 setbits8(&bcsr_regs[11], BCSR11_ENET_MICRST);
232         }
233 
234         iounmap(bcsr_regs);
235 }
236 
237 static void __init mpc85xx_mds_qe_init(void)
238 {
239         struct device_node *np;
240 
241         mpc85xx_qe_init();
242         mpc85xx_mds_reset_ucc_phys();
243 
244         if (machine_is(p1021_mds)) {
245 
246                 struct ccsr_guts __iomem *guts;
247 
248                 np = of_find_node_by_name(NULL, "global-utilities");
249                 if (np) {
250                         guts = of_iomap(np, 0);
251                         if (!guts)
252                                 pr_err("mpc85xx-rdb: could not map global utilities register\n");
253                         else{
254                         /* P1021 has pins muxed for QE and other functions. To
255                          * enable QE UEC mode, we need to set bit QE0 for UCC1
256                          * in Eth mode, QE0 and QE3 for UCC5 in Eth mode, QE9
257                          * and QE12 for QE MII management signals in PMUXCR
258                          * register.
259                          */
260                                 setbits32(&guts->pmuxcr, MPC85xx_PMUXCR_QE(0) |
261                                                   MPC85xx_PMUXCR_QE(3) |
262                                                   MPC85xx_PMUXCR_QE(9) |
263                                                   MPC85xx_PMUXCR_QE(12));
264                                 iounmap(guts);
265                         }
266                         of_node_put(np);
267                 }
268 
269         }
270 }
271 
272 static void __init mpc85xx_mds_qeic_init(void)
273 {
274         struct device_node *np;
275 
276         np = of_find_compatible_node(NULL, NULL, "fsl,qe");
277         if (!of_device_is_available(np)) {
278                 of_node_put(np);
279                 return;
280         }
281 
282         np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
283         if (!np) {
284                 np = of_find_node_by_type(NULL, "qeic");
285                 if (!np)
286                         return;
287         }
288 
289         if (machine_is(p1021_mds))
290                 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
291                                 qe_ic_cascade_high_mpic);
292         else
293                 qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
294         of_node_put(np);
295 }
296 #else
297 static void __init mpc85xx_mds_qe_init(void) { }
298 static void __init mpc85xx_mds_qeic_init(void) { }
299 #endif  /* CONFIG_QUICC_ENGINE */
300 
301 static void __init mpc85xx_mds_setup_arch(void)
302 {
303         if (ppc_md.progress)
304                 ppc_md.progress("mpc85xx_mds_setup_arch()", 0);
305 
306         mpc85xx_smp_init();
307 
308         mpc85xx_mds_qe_init();
309 
310         fsl_pci_assign_primary();
311 
312         swiotlb_detect_4g();
313 }
314 
315 
316 static int __init board_fixups(void)
317 {
318         char phy_id[20];
319         char *compstrs[2] = {"fsl,gianfar-mdio", "fsl,ucc-mdio"};
320         struct device_node *mdio;
321         struct resource res;
322         int i;
323 
324         for (i = 0; i < ARRAY_SIZE(compstrs); i++) {
325                 mdio = of_find_compatible_node(NULL, NULL, compstrs[i]);
326 
327                 of_address_to_resource(mdio, 0, &res);
328                 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
329                         (unsigned long long)res.start, 1);
330 
331                 phy_register_fixup_for_id(phy_id, mpc8568_fixup_125_clock);
332                 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
333 
334                 /* Register a workaround for errata */
335                 snprintf(phy_id, sizeof(phy_id), "%llx:%02x",
336                         (unsigned long long)res.start, 7);
337                 phy_register_fixup_for_id(phy_id, mpc8568_mds_phy_fixups);
338 
339                 of_node_put(mdio);
340         }
341 
342         return 0;
343 }
344 machine_arch_initcall(mpc8568_mds, board_fixups);
345 machine_arch_initcall(mpc8569_mds, board_fixups);
346 
347 static int __init mpc85xx_publish_devices(void)
348 {
349         if (machine_is(mpc8568_mds))
350                 simple_gpiochip_init("fsl,mpc8568mds-bcsr-gpio");
351         if (machine_is(mpc8569_mds))
352                 simple_gpiochip_init("fsl,mpc8569mds-bcsr-gpio");
353 
354         return mpc85xx_common_publish_devices();
355 }
356 
357 machine_arch_initcall(mpc8568_mds, mpc85xx_publish_devices);
358 machine_arch_initcall(mpc8569_mds, mpc85xx_publish_devices);
359 machine_arch_initcall(p1021_mds, mpc85xx_common_publish_devices);
360 
361 machine_arch_initcall(mpc8568_mds, swiotlb_setup_bus_notifier);
362 machine_arch_initcall(mpc8569_mds, swiotlb_setup_bus_notifier);
363 machine_arch_initcall(p1021_mds, swiotlb_setup_bus_notifier);
364 
365 static void __init mpc85xx_mds_pic_init(void)
366 {
367         struct mpic *mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
368                         MPIC_SINGLE_DEST_CPU,
369                         0, 256, " OpenPIC  ");
370         BUG_ON(mpic == NULL);
371 
372         mpic_init(mpic);
373         mpc85xx_mds_qeic_init();
374 }
375 
376 static int __init mpc85xx_mds_probe(void)
377 {
378         unsigned long root = of_get_flat_dt_root();
379 
380         return of_flat_dt_is_compatible(root, "MPC85xxMDS");
381 }
382 
383 define_machine(mpc8568_mds) {
384         .name           = "MPC8568 MDS",
385         .probe          = mpc85xx_mds_probe,
386         .setup_arch     = mpc85xx_mds_setup_arch,
387         .init_IRQ       = mpc85xx_mds_pic_init,
388         .get_irq        = mpic_get_irq,
389         .restart        = fsl_rstcr_restart,
390         .calibrate_decr = generic_calibrate_decr,
391         .progress       = udbg_progress,
392 #ifdef CONFIG_PCI
393         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
394 #endif
395 };
396 
397 static int __init mpc8569_mds_probe(void)
398 {
399         unsigned long root = of_get_flat_dt_root();
400 
401         return of_flat_dt_is_compatible(root, "fsl,MPC8569EMDS");
402 }
403 
404 define_machine(mpc8569_mds) {
405         .name           = "MPC8569 MDS",
406         .probe          = mpc8569_mds_probe,
407         .setup_arch     = mpc85xx_mds_setup_arch,
408         .init_IRQ       = mpc85xx_mds_pic_init,
409         .get_irq        = mpic_get_irq,
410         .restart        = fsl_rstcr_restart,
411         .calibrate_decr = generic_calibrate_decr,
412         .progress       = udbg_progress,
413 #ifdef CONFIG_PCI
414         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
415 #endif
416 };
417 
418 static int __init p1021_mds_probe(void)
419 {
420         unsigned long root = of_get_flat_dt_root();
421 
422         return of_flat_dt_is_compatible(root, "fsl,P1021MDS");
423 
424 }
425 
426 define_machine(p1021_mds) {
427         .name           = "P1021 MDS",
428         .probe          = p1021_mds_probe,
429         .setup_arch     = mpc85xx_mds_setup_arch,
430         .init_IRQ       = mpc85xx_mds_pic_init,
431         .get_irq        = mpic_get_irq,
432         .restart        = fsl_rstcr_restart,
433         .calibrate_decr = generic_calibrate_decr,
434         .progress       = udbg_progress,
435 #ifdef CONFIG_PCI
436         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
437 #endif
438 };
439 
440 

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