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Linux/arch/powerpc/platforms/85xx/mpc85xx_cds.c

  1 /*
  2  * MPC85xx setup and early boot code plus other random bits.
  3  *
  4  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
  5  *
  6  * Copyright 2005, 2011-2012 Freescale Semiconductor Inc.
  7  *
  8  * This program is free software; you can redistribute  it and/or modify it
  9  * under  the terms of  the GNU General  Public License as published by the
 10  * Free Software Foundation;  either version 2 of the  License, or (at your
 11  * option) any later version.
 12  */
 13 
 14 #include <linux/stddef.h>
 15 #include <linux/kernel.h>
 16 #include <linux/init.h>
 17 #include <linux/errno.h>
 18 #include <linux/reboot.h>
 19 #include <linux/pci.h>
 20 #include <linux/kdev_t.h>
 21 #include <linux/major.h>
 22 #include <linux/console.h>
 23 #include <linux/delay.h>
 24 #include <linux/seq_file.h>
 25 #include <linux/initrd.h>
 26 #include <linux/interrupt.h>
 27 #include <linux/fsl_devices.h>
 28 #include <linux/of_platform.h>
 29 
 30 #include <asm/pgtable.h>
 31 #include <asm/page.h>
 32 #include <linux/atomic.h>
 33 #include <asm/time.h>
 34 #include <asm/io.h>
 35 #include <asm/machdep.h>
 36 #include <asm/ipic.h>
 37 #include <asm/pci-bridge.h>
 38 #include <asm/irq.h>
 39 #include <mm/mmu_decl.h>
 40 #include <asm/prom.h>
 41 #include <asm/udbg.h>
 42 #include <asm/mpic.h>
 43 #include <asm/i8259.h>
 44 
 45 #include <sysdev/fsl_soc.h>
 46 #include <sysdev/fsl_pci.h>
 47 
 48 #include "mpc85xx.h"
 49 
 50 /*
 51  * The CDS board contains an FPGA/CPLD called "Cadmus", which collects
 52  * various logic and performs system control functions.
 53  * Here is the FPGA/CPLD register map.
 54  */
 55 struct cadmus_reg {
 56         u8 cm_ver;              /* Board version */
 57         u8 cm_csr;              /* General control/status */
 58         u8 cm_rst;              /* Reset control */
 59         u8 cm_hsclk;    /* High speed clock */
 60         u8 cm_hsxclk;   /* High speed clock extended */
 61         u8 cm_led;              /* LED data */
 62         u8 cm_pci;              /* PCI control/status */
 63         u8 cm_dma;              /* DMA control */
 64         u8 res[248];    /* Total 256 bytes */
 65 };
 66 
 67 static struct cadmus_reg *cadmus;
 68 
 69 #ifdef CONFIG_PCI
 70 
 71 #define ARCADIA_HOST_BRIDGE_IDSEL       17
 72 #define ARCADIA_2ND_BRIDGE_IDSEL        3
 73 
 74 static int mpc85xx_exclude_device(struct pci_controller *hose,
 75                                   u_char bus, u_char devfn)
 76 {
 77         /* We explicitly do not go past the Tundra 320 Bridge */
 78         if ((bus == 1) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
 79                 return PCIBIOS_DEVICE_NOT_FOUND;
 80         if ((bus == 0) && (PCI_SLOT(devfn) == ARCADIA_2ND_BRIDGE_IDSEL))
 81                 return PCIBIOS_DEVICE_NOT_FOUND;
 82         else
 83                 return PCIBIOS_SUCCESSFUL;
 84 }
 85 
 86 static int mpc85xx_cds_restart(struct notifier_block *this,
 87                                unsigned long mode, void *cmd)
 88 {
 89         struct pci_dev *dev;
 90         u_char tmp;
 91 
 92         if ((dev = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686,
 93                                         NULL))) {
 94 
 95                 /* Use the VIA Super Southbridge to force a PCI reset */
 96                 pci_read_config_byte(dev, 0x47, &tmp);
 97                 pci_write_config_byte(dev, 0x47, tmp | 1);
 98 
 99                 /* Flush the outbound PCI write queues */
100                 pci_read_config_byte(dev, 0x47, &tmp);
101 
102                 /*
103                  *  At this point, the hardware reset should have triggered.
104                  *  However, if it doesn't work for some mysterious reason,
105                  *  just fall through to the default reset below.
106                  */
107 
108                 pci_dev_put(dev);
109         }
110 
111         /*
112          *  If we can't find the VIA chip (maybe the P2P bridge is
113          *  disabled) or the VIA chip reset didn't work, just return
114          *  and let default reset sequence happen.
115          */
116         return NOTIFY_DONE;
117 }
118 
119 static int mpc85xx_cds_restart_register(void)
120 {
121         static struct notifier_block restart_handler;
122 
123         restart_handler.notifier_call = mpc85xx_cds_restart;
124         restart_handler.priority = 192;
125 
126         return register_restart_handler(&restart_handler);
127 }
128 machine_arch_initcall(mpc85xx_cds, mpc85xx_cds_restart_register);
129 
130 
131 static void __init mpc85xx_cds_pci_irq_fixup(struct pci_dev *dev)
132 {
133         u_char c;
134         if (dev->vendor == PCI_VENDOR_ID_VIA) {
135                 switch (dev->device) {
136                 case PCI_DEVICE_ID_VIA_82C586_1:
137                         /*
138                          * U-Boot does not set the enable bits
139                          * for the IDE device. Force them on here.
140                          */
141                         pci_read_config_byte(dev, 0x40, &c);
142                         c |= 0x03; /* IDE: Chip Enable Bits */
143                         pci_write_config_byte(dev, 0x40, c);
144 
145                         /*
146                          * Since only primary interface works, force the
147                          * IDE function to standard primary IDE interrupt
148                          * w/ 8259 offset
149                          */
150                         dev->irq = 14;
151                         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
152                         break;
153                 /*
154                  * Force legacy USB interrupt routing
155                  */
156                 case PCI_DEVICE_ID_VIA_82C586_2:
157                 /* There are two USB controllers.
158                  * Identify them by functon number
159                  */
160                         if (PCI_FUNC(dev->devfn) == 3)
161                                 dev->irq = 11;
162                         else
163                                 dev->irq = 10;
164                         pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
165                 default:
166                         break;
167                 }
168         }
169 }
170 
171 static void skip_fake_bridge(struct pci_dev *dev)
172 {
173         /* Make it an error to skip the fake bridge
174          * in pci_setup_device() in probe.c */
175         dev->hdr_type = 0x7f;
176 }
177 DECLARE_PCI_FIXUP_EARLY(0x1957, 0x3fff, skip_fake_bridge);
178 DECLARE_PCI_FIXUP_EARLY(0x3fff, 0x1957, skip_fake_bridge);
179 DECLARE_PCI_FIXUP_EARLY(0xff3f, 0x5719, skip_fake_bridge);
180 
181 #define PCI_DEVICE_ID_IDT_TSI310        0x01a7
182 
183 /*
184  * Fix Tsi310 PCI-X bridge resource.
185  * Force the bridge to open a window from 0x0000-0x1fff in PCI I/O space.
186  * This allows legacy I/O(i8259, etc) on the VIA southbridge to be accessed.
187  */
188 void mpc85xx_cds_fixup_bus(struct pci_bus *bus)
189 {
190         struct pci_dev *dev = bus->self;
191         struct resource *res = bus->resource[0];
192 
193         if (dev != NULL &&
194             dev->vendor == PCI_VENDOR_ID_IBM &&
195             dev->device == PCI_DEVICE_ID_IDT_TSI310) {
196                 if (res) {
197                         res->start = 0;
198                         res->end   = 0x1fff;
199                         res->flags = IORESOURCE_IO;
200                         pr_info("mpc85xx_cds: PCI bridge resource fixup applied\n");
201                         pr_info("mpc85xx_cds: %pR\n", res);
202                 }
203         }
204 
205         fsl_pcibios_fixup_bus(bus);
206 }
207 
208 #ifdef CONFIG_PPC_I8259
209 static void mpc85xx_8259_cascade_handler(struct irq_desc *desc)
210 {
211         unsigned int cascade_irq = i8259_irq();
212 
213         if (cascade_irq)
214                 /* handle an interrupt from the 8259 */
215                 generic_handle_irq(cascade_irq);
216 
217         /* check for any interrupts from the shared IRQ line */
218         handle_fasteoi_irq(desc);
219 }
220 
221 static irqreturn_t mpc85xx_8259_cascade_action(int irq, void *dev_id)
222 {
223         return IRQ_HANDLED;
224 }
225 
226 static struct irqaction mpc85xxcds_8259_irqaction = {
227         .handler = mpc85xx_8259_cascade_action,
228         .flags = IRQF_SHARED | IRQF_NO_THREAD,
229         .name = "8259 cascade",
230 };
231 #endif /* PPC_I8259 */
232 #endif /* CONFIG_PCI */
233 
234 static void __init mpc85xx_cds_pic_init(void)
235 {
236         struct mpic *mpic;
237         mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN,
238                         0, 256, " OpenPIC  ");
239         BUG_ON(mpic == NULL);
240         mpic_init(mpic);
241 }
242 
243 #if defined(CONFIG_PPC_I8259) && defined(CONFIG_PCI)
244 static int mpc85xx_cds_8259_attach(void)
245 {
246         int ret;
247         struct device_node *np = NULL;
248         struct device_node *cascade_node = NULL;
249         int cascade_irq;
250 
251         /* Initialize the i8259 controller */
252         for_each_node_by_type(np, "interrupt-controller")
253                 if (of_device_is_compatible(np, "chrp,iic")) {
254                         cascade_node = np;
255                         break;
256                 }
257 
258         if (cascade_node == NULL) {
259                 printk(KERN_DEBUG "Could not find i8259 PIC\n");
260                 return -ENODEV;
261         }
262 
263         cascade_irq = irq_of_parse_and_map(cascade_node, 0);
264         if (!cascade_irq) {
265                 printk(KERN_ERR "Failed to map cascade interrupt\n");
266                 return -ENXIO;
267         }
268 
269         i8259_init(cascade_node, 0);
270         of_node_put(cascade_node);
271 
272         /*
273          *  Hook the interrupt to make sure desc->action is never NULL.
274          *  This is required to ensure that the interrupt does not get
275          *  disabled when the last user of the shared IRQ line frees their
276          *  interrupt.
277          */
278         if ((ret = setup_irq(cascade_irq, &mpc85xxcds_8259_irqaction))) {
279                 printk(KERN_ERR "Failed to setup cascade interrupt\n");
280                 return ret;
281         }
282 
283         /* Success. Connect our low-level cascade handler. */
284         irq_set_handler(cascade_irq, mpc85xx_8259_cascade_handler);
285 
286         return 0;
287 }
288 machine_device_initcall(mpc85xx_cds, mpc85xx_cds_8259_attach);
289 
290 #endif /* CONFIG_PPC_I8259 */
291 
292 static void mpc85xx_cds_pci_assign_primary(void)
293 {
294 #ifdef CONFIG_PCI
295         struct device_node *np;
296 
297         if (fsl_pci_primary)
298                 return;
299 
300         /*
301          * MPC85xx_CDS has ISA bridge but unfortunately there is no
302          * isa node in device tree. We now looking for i8259 node as
303          * a workaround for such a broken device tree. This routine
304          * is for complying to all device trees.
305          */
306         np = of_find_node_by_name(NULL, "i8259");
307         while ((fsl_pci_primary = of_get_parent(np))) {
308                 of_node_put(np);
309                 np = fsl_pci_primary;
310 
311                 if ((of_device_is_compatible(np, "fsl,mpc8540-pci") ||
312                     of_device_is_compatible(np, "fsl,mpc8548-pcie")) &&
313                     of_device_is_available(np))
314                         return;
315         }
316 #endif
317 }
318 
319 /*
320  * Setup the architecture
321  */
322 static void __init mpc85xx_cds_setup_arch(void)
323 {
324         struct device_node *np;
325         int cds_pci_slot;
326 
327         if (ppc_md.progress)
328                 ppc_md.progress("mpc85xx_cds_setup_arch()", 0);
329 
330         np = of_find_compatible_node(NULL, NULL, "fsl,mpc8548cds-fpga");
331         if (!np) {
332                 pr_err("Could not find FPGA node.\n");
333                 return;
334         }
335 
336         cadmus = of_iomap(np, 0);
337         of_node_put(np);
338         if (!cadmus) {
339                 pr_err("Fail to map FPGA area.\n");
340                 return;
341         }
342 
343         if (ppc_md.progress) {
344                 char buf[40];
345                 cds_pci_slot = ((in_8(&cadmus->cm_csr) >> 6) & 0x3) + 1;
346                 snprintf(buf, 40, "CDS Version = 0x%x in slot %d\n",
347                                 in_8(&cadmus->cm_ver), cds_pci_slot);
348                 ppc_md.progress(buf, 0);
349         }
350 
351 #ifdef CONFIG_PCI
352         ppc_md.pci_irq_fixup = mpc85xx_cds_pci_irq_fixup;
353         ppc_md.pci_exclude_device = mpc85xx_exclude_device;
354 #endif
355 
356         mpc85xx_cds_pci_assign_primary();
357         fsl_pci_assign_primary();
358 }
359 
360 static void mpc85xx_cds_show_cpuinfo(struct seq_file *m)
361 {
362         uint pvid, svid, phid1;
363 
364         pvid = mfspr(SPRN_PVR);
365         svid = mfspr(SPRN_SVR);
366 
367         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
368         seq_printf(m, "Machine\t\t: MPC85xx CDS (0x%x)\n",
369                         in_8(&cadmus->cm_ver));
370         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
371         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
372 
373         /* Display cpu Pll setting */
374         phid1 = mfspr(SPRN_HID1);
375         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
376 }
377 
378 
379 /*
380  * Called very early, device-tree isn't unflattened
381  */
382 static int __init mpc85xx_cds_probe(void)
383 {
384         return of_machine_is_compatible("MPC85xxCDS");
385 }
386 
387 machine_arch_initcall(mpc85xx_cds, mpc85xx_common_publish_devices);
388 
389 define_machine(mpc85xx_cds) {
390         .name           = "MPC85xx CDS",
391         .probe          = mpc85xx_cds_probe,
392         .setup_arch     = mpc85xx_cds_setup_arch,
393         .init_IRQ       = mpc85xx_cds_pic_init,
394         .show_cpuinfo   = mpc85xx_cds_show_cpuinfo,
395         .get_irq        = mpic_get_irq,
396 #ifdef CONFIG_PCI
397         .pcibios_fixup_bus      = mpc85xx_cds_fixup_bus,
398         .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
399 #endif
400         .calibrate_decr = generic_calibrate_decr,
401         .progress       = udbg_progress,
402 };
403 

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