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Linux/arch/powerpc/platforms/85xx/corenet_generic.c

  1 /*
  2  * Corenet based SoC DS Setup
  3  *
  4  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
  5  *
  6  * Copyright 2009-2011 Freescale Semiconductor Inc.
  7  *
  8  * This program is free software; you can redistribute  it and/or modify it
  9  * under  the terms of  the GNU General  Public License as published by the
 10  * Free Software Foundation;  either version 2 of the  License, or (at your
 11  * option) any later version.
 12  */
 13 
 14 #include <linux/kernel.h>
 15 #include <linux/pci.h>
 16 #include <linux/kdev_t.h>
 17 #include <linux/delay.h>
 18 #include <linux/interrupt.h>
 19 
 20 #include <asm/time.h>
 21 #include <asm/machdep.h>
 22 #include <asm/pci-bridge.h>
 23 #include <asm/pgtable.h>
 24 #include <asm/ppc-pci.h>
 25 #include <mm/mmu_decl.h>
 26 #include <asm/prom.h>
 27 #include <asm/udbg.h>
 28 #include <asm/mpic.h>
 29 #include <asm/ehv_pic.h>
 30 #include <asm/qe_ic.h>
 31 
 32 #include <linux/of_platform.h>
 33 #include <sysdev/fsl_soc.h>
 34 #include <sysdev/fsl_pci.h>
 35 #include "smp.h"
 36 #include "mpc85xx.h"
 37 
 38 void __init corenet_gen_pic_init(void)
 39 {
 40         struct mpic *mpic;
 41         unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
 42                 MPIC_NO_RESET;
 43 
 44         struct device_node *np;
 45 
 46         if (ppc_md.get_irq == mpic_get_coreint_irq)
 47                 flags |= MPIC_ENABLE_COREINT;
 48 
 49         mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC  ");
 50         BUG_ON(mpic == NULL);
 51 
 52         mpic_init(mpic);
 53 
 54         np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
 55         if (np) {
 56                 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
 57                                 qe_ic_cascade_high_mpic);
 58                 of_node_put(np);
 59         }
 60 }
 61 
 62 /*
 63  * Setup the architecture
 64  */
 65 void __init corenet_gen_setup_arch(void)
 66 {
 67         mpc85xx_smp_init();
 68 
 69         swiotlb_detect_4g();
 70 
 71 #if defined(CONFIG_FSL_PCI) && defined(CONFIG_ZONE_DMA32)
 72         /*
 73          * Inbound windows don't cover the full lower 4 GiB
 74          * due to conflicts with PCICSRBAR and outbound windows,
 75          * so limit the DMA32 zone to 2 GiB, to allow consistent
 76          * allocations to succeed.
 77          */
 78         limit_zone_pfn(ZONE_DMA32, 1UL << (31 - PAGE_SHIFT));
 79 #endif
 80 
 81         pr_info("%s board\n", ppc_md.name);
 82 
 83         mpc85xx_qe_init();
 84 }
 85 
 86 static const struct of_device_id of_device_ids[] = {
 87         {
 88                 .compatible     = "simple-bus"
 89         },
 90         {
 91                 .compatible     = "fsl,srio",
 92         },
 93         {
 94                 .compatible     = "fsl,p4080-pcie",
 95         },
 96         {
 97                 .compatible     = "fsl,qoriq-pcie-v2.2",
 98         },
 99         {
100                 .compatible     = "fsl,qoriq-pcie-v2.3",
101         },
102         {
103                 .compatible     = "fsl,qoriq-pcie-v2.4",
104         },
105         {
106                 .compatible     = "fsl,qoriq-pcie-v3.0",
107         },
108         {
109                 .compatible     = "fsl,qe",
110         },
111         /* The following two are for the Freescale hypervisor */
112         {
113                 .name           = "hypervisor",
114         },
115         {
116                 .name           = "handles",
117         },
118         {}
119 };
120 
121 int __init corenet_gen_publish_devices(void)
122 {
123         return of_platform_bus_probe(NULL, of_device_ids, NULL);
124 }
125 
126 static const char * const boards[] __initconst = {
127         "fsl,P2041RDB",
128         "fsl,P3041DS",
129         "fsl,OCA4080",
130         "fsl,P4080DS",
131         "fsl,P5020DS",
132         "fsl,P5040DS",
133         "fsl,T2080QDS",
134         "fsl,T2080RDB",
135         "fsl,T2081QDS",
136         "fsl,T4240QDS",
137         "fsl,T4240RDB",
138         "fsl,B4860QDS",
139         "fsl,B4420QDS",
140         "fsl,B4220QDS",
141         "fsl,T1040QDS",
142         "fsl,T1042QDS",
143         "fsl,T1040RDB",
144         "fsl,T1042RDB",
145         "fsl,T1042RDB_PI",
146         "keymile,kmcoge4",
147         NULL
148 };
149 
150 /*
151  * Called very early, device-tree isn't unflattened
152  */
153 static int __init corenet_generic_probe(void)
154 {
155         unsigned long root = of_get_flat_dt_root();
156         char hv_compat[24];
157         int i;
158 #ifdef CONFIG_SMP
159         extern struct smp_ops_t smp_85xx_ops;
160 #endif
161 
162         if (of_flat_dt_match(root, boards))
163                 return 1;
164 
165         /* Check if we're running under the Freescale hypervisor */
166         for (i = 0; boards[i]; i++) {
167                 snprintf(hv_compat, sizeof(hv_compat), "%s-hv", boards[i]);
168                 if (of_flat_dt_is_compatible(root, hv_compat)) {
169                         ppc_md.init_IRQ = ehv_pic_init;
170 
171                         ppc_md.get_irq = ehv_pic_get_irq;
172                         ppc_md.restart = fsl_hv_restart;
173                         ppc_md.power_off = fsl_hv_halt;
174                         ppc_md.halt = fsl_hv_halt;
175 #ifdef CONFIG_SMP
176                         /*
177                          * Disable the timebase sync operations because we
178                          * can't write to the timebase registers under the
179                          * hypervisor.
180                          */
181                         smp_85xx_ops.give_timebase = NULL;
182                         smp_85xx_ops.take_timebase = NULL;
183 #endif
184                         return 1;
185                 }
186         }
187 
188         return 0;
189 }
190 
191 define_machine(corenet_generic) {
192         .name                   = "CoreNet Generic",
193         .probe                  = corenet_generic_probe,
194         .setup_arch             = corenet_gen_setup_arch,
195         .init_IRQ               = corenet_gen_pic_init,
196 #ifdef CONFIG_PCI
197         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
198         .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
199 #endif
200         .get_irq                = mpic_get_coreint_irq,
201         .restart                = fsl_rstcr_restart,
202         .calibrate_decr         = generic_calibrate_decr,
203         .progress               = udbg_progress,
204 #ifdef CONFIG_PPC64
205         .power_save             = book3e_idle,
206 #else
207         .power_save             = e500_idle,
208 #endif
209 };
210 
211 machine_arch_initcall(corenet_generic, corenet_gen_publish_devices);
212 
213 #ifdef CONFIG_SWIOTLB
214 machine_arch_initcall(corenet_generic, swiotlb_setup_bus_notifier);
215 #endif
216 

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