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Linux/arch/powerpc/platforms/85xx/corenet_generic.c

  1 /*
  2  * Corenet based SoC DS Setup
  3  *
  4  * Maintained by Kumar Gala (see MAINTAINERS for contact information)
  5  *
  6  * Copyright 2009-2011 Freescale Semiconductor Inc.
  7  *
  8  * This program is free software; you can redistribute  it and/or modify it
  9  * under  the terms of  the GNU General  Public License as published by the
 10  * Free Software Foundation;  either version 2 of the  License, or (at your
 11  * option) any later version.
 12  */
 13 
 14 #include <linux/kernel.h>
 15 #include <linux/pci.h>
 16 #include <linux/kdev_t.h>
 17 #include <linux/delay.h>
 18 #include <linux/interrupt.h>
 19 
 20 #include <asm/time.h>
 21 #include <asm/machdep.h>
 22 #include <asm/pci-bridge.h>
 23 #include <asm/ppc-pci.h>
 24 #include <mm/mmu_decl.h>
 25 #include <asm/prom.h>
 26 #include <asm/udbg.h>
 27 #include <asm/mpic.h>
 28 #include <asm/ehv_pic.h>
 29 #include <asm/qe_ic.h>
 30 
 31 #include <linux/of_platform.h>
 32 #include <sysdev/fsl_soc.h>
 33 #include <sysdev/fsl_pci.h>
 34 #include "smp.h"
 35 #include "mpc85xx.h"
 36 
 37 void __init corenet_gen_pic_init(void)
 38 {
 39         struct mpic *mpic;
 40         unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
 41                 MPIC_NO_RESET;
 42 
 43         struct device_node *np;
 44 
 45         if (ppc_md.get_irq == mpic_get_coreint_irq)
 46                 flags |= MPIC_ENABLE_COREINT;
 47 
 48         mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC  ");
 49         BUG_ON(mpic == NULL);
 50 
 51         mpic_init(mpic);
 52 
 53         np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
 54         if (np) {
 55                 qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
 56                                 qe_ic_cascade_high_mpic);
 57                 of_node_put(np);
 58         }
 59 }
 60 
 61 /*
 62  * Setup the architecture
 63  */
 64 void __init corenet_gen_setup_arch(void)
 65 {
 66         mpc85xx_smp_init();
 67 
 68         swiotlb_detect_4g();
 69 
 70         pr_info("%s board\n", ppc_md.name);
 71 
 72         mpc85xx_qe_init();
 73 }
 74 
 75 static const struct of_device_id of_device_ids[] = {
 76         {
 77                 .compatible     = "simple-bus"
 78         },
 79         {
 80                 .compatible     = "fsl,srio",
 81         },
 82         {
 83                 .compatible     = "fsl,p4080-pcie",
 84         },
 85         {
 86                 .compatible     = "fsl,qoriq-pcie-v2.2",
 87         },
 88         {
 89                 .compatible     = "fsl,qoriq-pcie-v2.3",
 90         },
 91         {
 92                 .compatible     = "fsl,qoriq-pcie-v2.4",
 93         },
 94         {
 95                 .compatible     = "fsl,qoriq-pcie-v3.0",
 96         },
 97         {
 98                 .compatible     = "fsl,qe",
 99         },
100         /* The following two are for the Freescale hypervisor */
101         {
102                 .name           = "hypervisor",
103         },
104         {
105                 .name           = "handles",
106         },
107         {}
108 };
109 
110 int __init corenet_gen_publish_devices(void)
111 {
112         return of_platform_bus_probe(NULL, of_device_ids, NULL);
113 }
114 
115 static const char * const boards[] __initconst = {
116         "fsl,P2041RDB",
117         "fsl,P3041DS",
118         "fsl,OCA4080",
119         "fsl,P4080DS",
120         "fsl,P5020DS",
121         "fsl,P5040DS",
122         "fsl,T2080QDS",
123         "fsl,T2080RDB",
124         "fsl,T2081QDS",
125         "fsl,T4240QDS",
126         "fsl,T4240RDB",
127         "fsl,B4860QDS",
128         "fsl,B4420QDS",
129         "fsl,B4220QDS",
130         "fsl,T1040QDS",
131         "fsl,T1042QDS",
132         "keymile,kmcoge4",
133         NULL
134 };
135 
136 /*
137  * Called very early, device-tree isn't unflattened
138  */
139 static int __init corenet_generic_probe(void)
140 {
141         unsigned long root = of_get_flat_dt_root();
142         char hv_compat[24];
143         int i;
144 #ifdef CONFIG_SMP
145         extern struct smp_ops_t smp_85xx_ops;
146 #endif
147 
148         if (of_flat_dt_match(root, boards))
149                 return 1;
150 
151         /* Check if we're running under the Freescale hypervisor */
152         for (i = 0; boards[i]; i++) {
153                 snprintf(hv_compat, sizeof(hv_compat), "%s-hv", boards[i]);
154                 if (of_flat_dt_is_compatible(root, hv_compat)) {
155                         ppc_md.init_IRQ = ehv_pic_init;
156 
157                         ppc_md.get_irq = ehv_pic_get_irq;
158                         ppc_md.restart = fsl_hv_restart;
159                         ppc_md.power_off = fsl_hv_halt;
160                         ppc_md.halt = fsl_hv_halt;
161 #ifdef CONFIG_SMP
162                         /*
163                          * Disable the timebase sync operations because we
164                          * can't write to the timebase registers under the
165                          * hypervisor.
166                          */
167                         smp_85xx_ops.give_timebase = NULL;
168                         smp_85xx_ops.take_timebase = NULL;
169 #endif
170                         return 1;
171                 }
172         }
173 
174         return 0;
175 }
176 
177 define_machine(corenet_generic) {
178         .name                   = "CoreNet Generic",
179         .probe                  = corenet_generic_probe,
180         .setup_arch             = corenet_gen_setup_arch,
181         .init_IRQ               = corenet_gen_pic_init,
182 #ifdef CONFIG_PCI
183         .pcibios_fixup_bus      = fsl_pcibios_fixup_bus,
184         .pcibios_fixup_phb      = fsl_pcibios_fixup_phb,
185 #endif
186         .get_irq                = mpic_get_coreint_irq,
187         .restart                = fsl_rstcr_restart,
188         .calibrate_decr         = generic_calibrate_decr,
189         .progress               = udbg_progress,
190 #ifdef CONFIG_PPC64
191         .power_save             = book3e_idle,
192 #else
193         .power_save             = e500_idle,
194 #endif
195 };
196 
197 machine_arch_initcall(corenet_generic, corenet_gen_publish_devices);
198 
199 #ifdef CONFIG_SWIOTLB
200 machine_arch_initcall(corenet_generic, swiotlb_setup_bus_notifier);
201 #endif
202 

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