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Linux/arch/powerpc/platforms/83xx/mpc836x_mds.c

  1 /*
  2  * Copyright 2006 Freescale Semiconductor, Inc. All rights reserved.
  3  *
  4  * Author: Li Yang <LeoLi@freescale.com>
  5  *         Yin Olivia <Hong-hua.Yin@freescale.com>
  6  *
  7  * Description:
  8  * MPC8360E MDS board specific routines.
  9  *
 10  * Changelog:
 11  * Jun 21, 2006 Initial version
 12  *
 13  * This program is free software; you can redistribute it and/or modify it
 14  * under  the terms of  the GNU General  Public License as published by the
 15  * Free Software Foundation;  either version 2 of the  License, or (at your
 16  * option) any later version.
 17  */
 18 
 19 #include <linux/stddef.h>
 20 #include <linux/kernel.h>
 21 #include <linux/compiler.h>
 22 #include <linux/init.h>
 23 #include <linux/errno.h>
 24 #include <linux/reboot.h>
 25 #include <linux/pci.h>
 26 #include <linux/kdev_t.h>
 27 #include <linux/major.h>
 28 #include <linux/console.h>
 29 #include <linux/delay.h>
 30 #include <linux/seq_file.h>
 31 #include <linux/root_dev.h>
 32 #include <linux/initrd.h>
 33 #include <linux/of_platform.h>
 34 #include <linux/of_device.h>
 35 
 36 #include <linux/atomic.h>
 37 #include <asm/time.h>
 38 #include <asm/io.h>
 39 #include <asm/machdep.h>
 40 #include <asm/ipic.h>
 41 #include <asm/irq.h>
 42 #include <asm/prom.h>
 43 #include <asm/udbg.h>
 44 #include <sysdev/fsl_soc.h>
 45 #include <sysdev/fsl_pci.h>
 46 #include <sysdev/simple_gpio.h>
 47 #include <asm/qe.h>
 48 #include <asm/qe_ic.h>
 49 
 50 #include "mpc83xx.h"
 51 
 52 #undef DEBUG
 53 #ifdef DEBUG
 54 #define DBG(fmt...) udbg_printf(fmt)
 55 #else
 56 #define DBG(fmt...)
 57 #endif
 58 
 59 /* ************************************************************************
 60  *
 61  * Setup the architecture
 62  *
 63  */
 64 static void __init mpc836x_mds_setup_arch(void)
 65 {
 66         struct device_node *np;
 67         u8 __iomem *bcsr_regs = NULL;
 68 
 69         if (ppc_md.progress)
 70                 ppc_md.progress("mpc836x_mds_setup_arch()", 0);
 71 
 72         /* Map BCSR area */
 73         np = of_find_node_by_name(NULL, "bcsr");
 74         if (np) {
 75                 struct resource res;
 76 
 77                 of_address_to_resource(np, 0, &res);
 78                 bcsr_regs = ioremap(res.start, resource_size(&res));
 79                 of_node_put(np);
 80         }
 81 
 82         mpc83xx_setup_pci();
 83 
 84 #ifdef CONFIG_QUICC_ENGINE
 85         qe_reset();
 86 
 87         if ((np = of_find_node_by_name(NULL, "par_io")) != NULL) {
 88                 par_io_init(np);
 89                 of_node_put(np);
 90 
 91                 for (np = NULL; (np = of_find_node_by_name(np, "ucc")) != NULL;)
 92                         par_io_of_config(np);
 93 #ifdef CONFIG_QE_USB
 94                 /* Must fixup Par IO before QE GPIO chips are registered. */
 95                 par_io_config_pin(1,  2, 1, 0, 3, 0); /* USBOE  */
 96                 par_io_config_pin(1,  3, 1, 0, 3, 0); /* USBTP  */
 97                 par_io_config_pin(1,  8, 1, 0, 1, 0); /* USBTN  */
 98                 par_io_config_pin(1, 10, 2, 0, 3, 0); /* USBRXD */
 99                 par_io_config_pin(1,  9, 2, 1, 3, 0); /* USBRP  */
100                 par_io_config_pin(1, 11, 2, 1, 3, 0); /* USBRN  */
101                 par_io_config_pin(2, 20, 2, 0, 1, 0); /* CLK21  */
102 #endif /* CONFIG_QE_USB */
103         }
104 
105         if ((np = of_find_compatible_node(NULL, "network", "ucc_geth"))
106                         != NULL){
107                 uint svid;
108 
109                 /* Reset the Ethernet PHY */
110 #define BCSR9_GETHRST 0x20
111                 clrbits8(&bcsr_regs[9], BCSR9_GETHRST);
112                 udelay(1000);
113                 setbits8(&bcsr_regs[9], BCSR9_GETHRST);
114 
115                 /* handle mpc8360ea rev.2.1 erratum 2: RGMII Timing */
116                 svid = mfspr(SPRN_SVR);
117                 if (svid == 0x80480021) {
118                         void __iomem *immap;
119 
120                         immap = ioremap(get_immrbase() + 0x14a8, 8);
121 
122                         /*
123                          * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
124                          * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
125                          */
126                         setbits32(immap, 0x0c003000);
127 
128                         /*
129                          * IMMR + 0x14AC[20:27] = 10101010
130                          * (data delay for both UCC's)
131                          */
132                         clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
133 
134                         iounmap(immap);
135                 }
136 
137                 iounmap(bcsr_regs);
138                 of_node_put(np);
139         }
140 #endif                          /* CONFIG_QUICC_ENGINE */
141 }
142 
143 machine_device_initcall(mpc836x_mds, mpc83xx_declare_of_platform_devices);
144 
145 #ifdef CONFIG_QE_USB
146 static int __init mpc836x_usb_cfg(void)
147 {
148         u8 __iomem *bcsr;
149         struct device_node *np;
150         const char *mode;
151         int ret = 0;
152 
153         np = of_find_compatible_node(NULL, NULL, "fsl,mpc8360mds-bcsr");
154         if (!np)
155                 return -ENODEV;
156 
157         bcsr = of_iomap(np, 0);
158         of_node_put(np);
159         if (!bcsr)
160                 return -ENOMEM;
161 
162         np = of_find_compatible_node(NULL, NULL, "fsl,mpc8323-qe-usb");
163         if (!np) {
164                 ret = -ENODEV;
165                 goto err;
166         }
167 
168 #define BCSR8_TSEC1M_MASK       (0x3 << 6)
169 #define BCSR8_TSEC1M_RGMII      (0x0 << 6)
170 #define BCSR8_TSEC2M_MASK       (0x3 << 4)
171 #define BCSR8_TSEC2M_RGMII      (0x0 << 4)
172         /*
173          * Default is GMII (2), but we should set it to RGMII (0) if we use
174          * USB (Eth PHY is in RGMII mode anyway).
175          */
176         clrsetbits_8(&bcsr[8], BCSR8_TSEC1M_MASK | BCSR8_TSEC2M_MASK,
177                                BCSR8_TSEC1M_RGMII | BCSR8_TSEC2M_RGMII);
178 
179 #define BCSR13_USBMASK  0x0f
180 #define BCSR13_nUSBEN   0x08 /* 1 - Disable, 0 - Enable                 */
181 #define BCSR13_USBSPEED 0x04 /* 1 - Full, 0 - Low                       */
182 #define BCSR13_USBMODE  0x02 /* 1 - Host, 0 - Function                  */
183 #define BCSR13_nUSBVCC  0x01 /* 1 - gets VBUS, 0 - supplies VBUS        */
184 
185         clrsetbits_8(&bcsr[13], BCSR13_USBMASK, BCSR13_USBSPEED);
186 
187         mode = of_get_property(np, "mode", NULL);
188         if (mode && !strcmp(mode, "peripheral")) {
189                 setbits8(&bcsr[13], BCSR13_nUSBVCC);
190                 qe_usb_clock_set(QE_CLK21, 48000000);
191         } else {
192                 setbits8(&bcsr[13], BCSR13_USBMODE);
193                 /*
194                  * The BCSR GPIOs are used to control power and
195                  * speed of the USB transceiver. This is needed for
196                  * the USB Host only.
197                  */
198                 simple_gpiochip_init("fsl,mpc8360mds-bcsr-gpio");
199         }
200 
201         of_node_put(np);
202 err:
203         iounmap(bcsr);
204         return ret;
205 }
206 machine_arch_initcall(mpc836x_mds, mpc836x_usb_cfg);
207 #endif /* CONFIG_QE_USB */
208 
209 /*
210  * Called very early, MMU is off, device-tree isn't unflattened
211  */
212 static int __init mpc836x_mds_probe(void)
213 {
214         unsigned long root = of_get_flat_dt_root();
215 
216         return of_flat_dt_is_compatible(root, "MPC836xMDS");
217 }
218 
219 define_machine(mpc836x_mds) {
220         .name           = "MPC836x MDS",
221         .probe          = mpc836x_mds_probe,
222         .setup_arch     = mpc836x_mds_setup_arch,
223         .init_IRQ       = mpc83xx_ipic_and_qe_init_IRQ,
224         .get_irq        = ipic_get_irq,
225         .restart        = mpc83xx_restart,
226         .time_init      = mpc83xx_time_init,
227         .calibrate_decr = generic_calibrate_decr,
228         .progress       = udbg_progress,
229 };
230 

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