Version:  2.0.40 2.2.26 2.4.37 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2

Linux/arch/mips/pci/pci-lantiq.c

  1 /*
  2  *  This program is free software; you can redistribute it and/or modify it
  3  *  under the terms of the GNU General Public License version 2 as published
  4  *  by the Free Software Foundation.
  5  *
  6  *  Copyright (C) 2010 John Crispin <blogic@openwrt.org>
  7  */
  8 
  9 #include <linux/types.h>
 10 #include <linux/pci.h>
 11 #include <linux/kernel.h>
 12 #include <linux/init.h>
 13 #include <linux/delay.h>
 14 #include <linux/mm.h>
 15 #include <linux/vmalloc.h>
 16 #include <linux/module.h>
 17 #include <linux/clk.h>
 18 #include <linux/of_platform.h>
 19 #include <linux/of_gpio.h>
 20 #include <linux/of_irq.h>
 21 #include <linux/of_pci.h>
 22 
 23 #include <asm/gpio.h>
 24 #include <asm/addrspace.h>
 25 
 26 #include <lantiq_soc.h>
 27 #include <lantiq_irq.h>
 28 
 29 #include "pci-lantiq.h"
 30 
 31 #define PCI_CR_FCI_ADDR_MAP0            0x00C0
 32 #define PCI_CR_FCI_ADDR_MAP1            0x00C4
 33 #define PCI_CR_FCI_ADDR_MAP2            0x00C8
 34 #define PCI_CR_FCI_ADDR_MAP3            0x00CC
 35 #define PCI_CR_FCI_ADDR_MAP4            0x00D0
 36 #define PCI_CR_FCI_ADDR_MAP5            0x00D4
 37 #define PCI_CR_FCI_ADDR_MAP6            0x00D8
 38 #define PCI_CR_FCI_ADDR_MAP7            0x00DC
 39 #define PCI_CR_CLK_CTRL                 0x0000
 40 #define PCI_CR_PCI_MOD                  0x0030
 41 #define PCI_CR_PC_ARB                   0x0080
 42 #define PCI_CR_FCI_ADDR_MAP11hg         0x00E4
 43 #define PCI_CR_BAR11MASK                0x0044
 44 #define PCI_CR_BAR12MASK                0x0048
 45 #define PCI_CR_BAR13MASK                0x004C
 46 #define PCI_CS_BASE_ADDR1               0x0010
 47 #define PCI_CR_PCI_ADDR_MAP11           0x0064
 48 #define PCI_CR_FCI_BURST_LENGTH         0x00E8
 49 #define PCI_CR_PCI_EOI                  0x002C
 50 #define PCI_CS_STS_CMD                  0x0004
 51 
 52 #define PCI_MASTER0_REQ_MASK_2BITS      8
 53 #define PCI_MASTER1_REQ_MASK_2BITS      10
 54 #define PCI_MASTER2_REQ_MASK_2BITS      12
 55 #define INTERNAL_ARB_ENABLE_BIT         0
 56 
 57 #define LTQ_CGU_IFCCR           0x0018
 58 #define LTQ_CGU_PCICR           0x0034
 59 
 60 #define ltq_pci_w32(x, y)       ltq_w32((x), ltq_pci_membase + (y))
 61 #define ltq_pci_r32(x)          ltq_r32(ltq_pci_membase + (x))
 62 
 63 #define ltq_pci_cfg_w32(x, y)   ltq_w32((x), ltq_pci_mapped_cfg + (y))
 64 #define ltq_pci_cfg_r32(x)      ltq_r32(ltq_pci_mapped_cfg + (x))
 65 
 66 __iomem void *ltq_pci_mapped_cfg;
 67 static __iomem void *ltq_pci_membase;
 68 
 69 static int reset_gpio;
 70 static struct clk *clk_pci, *clk_external;
 71 static struct resource pci_io_resource;
 72 static struct resource pci_mem_resource;
 73 static struct pci_ops pci_ops = {
 74         .read   = ltq_pci_read_config_dword,
 75         .write  = ltq_pci_write_config_dword
 76 };
 77 
 78 static struct pci_controller pci_controller = {
 79         .pci_ops        = &pci_ops,
 80         .mem_resource   = &pci_mem_resource,
 81         .mem_offset     = 0x00000000UL,
 82         .io_resource    = &pci_io_resource,
 83         .io_offset      = 0x00000000UL,
 84 };
 85 
 86 static inline u32 ltq_calc_bar11mask(void)
 87 {
 88         u32 mem, bar11mask;
 89 
 90         /* BAR11MASK value depends on available memory on system. */
 91         mem = get_num_physpages() * PAGE_SIZE;
 92         bar11mask = (0x0ffffff0 & ~((1 << (fls(mem) - 1)) - 1)) | 8;
 93 
 94         return bar11mask;
 95 }
 96 
 97 static int ltq_pci_startup(struct platform_device *pdev)
 98 {
 99         struct device_node *node = pdev->dev.of_node;
100         const __be32 *req_mask, *bus_clk;
101         u32 temp_buffer;
102 
103         /* get our clocks */
104         clk_pci = clk_get(&pdev->dev, NULL);
105         if (IS_ERR(clk_pci)) {
106                 dev_err(&pdev->dev, "failed to get pci clock\n");
107                 return PTR_ERR(clk_pci);
108         }
109 
110         clk_external = clk_get(&pdev->dev, "external");
111         if (IS_ERR(clk_external)) {
112                 clk_put(clk_pci);
113                 dev_err(&pdev->dev, "failed to get external pci clock\n");
114                 return PTR_ERR(clk_external);
115         }
116 
117         /* read the bus speed that we want */
118         bus_clk = of_get_property(node, "lantiq,bus-clock", NULL);
119         if (bus_clk)
120                 clk_set_rate(clk_pci, *bus_clk);
121 
122         /* and enable the clocks */
123         clk_enable(clk_pci);
124         if (of_find_property(node, "lantiq,external-clock", NULL))
125                 clk_enable(clk_external);
126         else
127                 clk_disable(clk_external);
128 
129         /* setup reset gpio used by pci */
130         reset_gpio = of_get_named_gpio(node, "gpio-reset", 0);
131         if (gpio_is_valid(reset_gpio)) {
132                 int ret = devm_gpio_request(&pdev->dev,
133                                                 reset_gpio, "pci-reset");
134                 if (ret) {
135                         dev_err(&pdev->dev,
136                                 "failed to request gpio %d\n", reset_gpio);
137                         return ret;
138                 }
139                 gpio_direction_output(reset_gpio, 1);
140         }
141 
142         /* enable auto-switching between PCI and EBU */
143         ltq_pci_w32(0xa, PCI_CR_CLK_CTRL);
144 
145         /* busy, i.e. configuration is not done, PCI access has to be retried */
146         ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) & ~(1 << 24), PCI_CR_PCI_MOD);
147         wmb();
148         /* BUS Master/IO/MEM access */
149         ltq_pci_cfg_w32(ltq_pci_cfg_r32(PCI_CS_STS_CMD) | 7, PCI_CS_STS_CMD);
150 
151         /* enable external 2 PCI masters */
152         temp_buffer = ltq_pci_r32(PCI_CR_PC_ARB);
153         /* setup the request mask */
154         req_mask = of_get_property(node, "req-mask", NULL);
155         if (req_mask)
156                 temp_buffer &= ~((*req_mask & 0xf) << 16);
157         else
158                 temp_buffer &= ~0xf0000;
159         /* enable internal arbiter */
160         temp_buffer |= (1 << INTERNAL_ARB_ENABLE_BIT);
161         /* enable internal PCI master reqest */
162         temp_buffer &= (~(3 << PCI_MASTER0_REQ_MASK_2BITS));
163 
164         /* enable EBU request */
165         temp_buffer &= (~(3 << PCI_MASTER1_REQ_MASK_2BITS));
166 
167         /* enable all external masters request */
168         temp_buffer &= (~(3 << PCI_MASTER2_REQ_MASK_2BITS));
169         ltq_pci_w32(temp_buffer, PCI_CR_PC_ARB);
170         wmb();
171 
172         /* setup BAR memory regions */
173         ltq_pci_w32(0x18000000, PCI_CR_FCI_ADDR_MAP0);
174         ltq_pci_w32(0x18400000, PCI_CR_FCI_ADDR_MAP1);
175         ltq_pci_w32(0x18800000, PCI_CR_FCI_ADDR_MAP2);
176         ltq_pci_w32(0x18c00000, PCI_CR_FCI_ADDR_MAP3);
177         ltq_pci_w32(0x19000000, PCI_CR_FCI_ADDR_MAP4);
178         ltq_pci_w32(0x19400000, PCI_CR_FCI_ADDR_MAP5);
179         ltq_pci_w32(0x19800000, PCI_CR_FCI_ADDR_MAP6);
180         ltq_pci_w32(0x19c00000, PCI_CR_FCI_ADDR_MAP7);
181         ltq_pci_w32(0x1ae00000, PCI_CR_FCI_ADDR_MAP11hg);
182         ltq_pci_w32(ltq_calc_bar11mask(), PCI_CR_BAR11MASK);
183         ltq_pci_w32(0, PCI_CR_PCI_ADDR_MAP11);
184         ltq_pci_w32(0, PCI_CS_BASE_ADDR1);
185         /* both TX and RX endian swap are enabled */
186         ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_EOI) | 3, PCI_CR_PCI_EOI);
187         wmb();
188         ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR12MASK) | 0x80000000,
189                 PCI_CR_BAR12MASK);
190         ltq_pci_w32(ltq_pci_r32(PCI_CR_BAR13MASK) | 0x80000000,
191                 PCI_CR_BAR13MASK);
192         /*use 8 dw burst length */
193         ltq_pci_w32(0x303, PCI_CR_FCI_BURST_LENGTH);
194         ltq_pci_w32(ltq_pci_r32(PCI_CR_PCI_MOD) | (1 << 24), PCI_CR_PCI_MOD);
195         wmb();
196 
197         /* setup irq line */
198         ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_CON) | 0xc, LTQ_EBU_PCC_CON);
199         ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_IEN) | 0x10, LTQ_EBU_PCC_IEN);
200 
201         /* toggle reset pin */
202         if (gpio_is_valid(reset_gpio)) {
203                 __gpio_set_value(reset_gpio, 0);
204                 wmb();
205                 mdelay(1);
206                 __gpio_set_value(reset_gpio, 1);
207         }
208         return 0;
209 }
210 
211 static int ltq_pci_probe(struct platform_device *pdev)
212 {
213         struct resource *res_cfg, *res_bridge;
214 
215         pci_clear_flags(PCI_PROBE_ONLY);
216 
217         res_bridge = platform_get_resource(pdev, IORESOURCE_MEM, 1);
218         ltq_pci_membase = devm_ioremap_resource(&pdev->dev, res_bridge);
219         if (IS_ERR(ltq_pci_membase))
220                 return PTR_ERR(ltq_pci_membase);
221 
222         res_cfg = platform_get_resource(pdev, IORESOURCE_MEM, 0);
223         ltq_pci_mapped_cfg = devm_ioremap_resource(&pdev->dev, res_cfg);
224         if (IS_ERR(ltq_pci_mapped_cfg))
225                 return PTR_ERR(ltq_pci_mapped_cfg);
226 
227         ltq_pci_startup(pdev);
228 
229         pci_load_of_ranges(&pci_controller, pdev->dev.of_node);
230         register_pci_controller(&pci_controller);
231         return 0;
232 }
233 
234 static const struct of_device_id ltq_pci_match[] = {
235         { .compatible = "lantiq,pci-xway" },
236         {},
237 };
238 MODULE_DEVICE_TABLE(of, ltq_pci_match);
239 
240 static struct platform_driver ltq_pci_driver = {
241         .probe = ltq_pci_probe,
242         .driver = {
243                 .name = "pci-xway",
244                 .of_match_table = ltq_pci_match,
245         },
246 };
247 
248 int __init pcibios_init(void)
249 {
250         int ret = platform_driver_register(&ltq_pci_driver);
251         if (ret)
252                 pr_info("pci-xway: Error registering platform driver!");
253         return ret;
254 }
255 
256 arch_initcall(pcibios_init);
257 

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