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Linux/arch/metag/Kconfig.soc

  1 choice
  2         prompt "SoC Type"
  3         default META21_FPGA
  4 
  5 config META12_FPGA
  6         bool "Meta 1.2 FPGA"
  7         select METAG_META12
  8         help
  9           This is a Meta 1.2 FPGA bitstream, just a bare CPU.
 10 
 11 config META21_FPGA
 12         bool "Meta 2.1 FPGA"
 13         select METAG_META21
 14         help
 15           This is a Meta 2.1 FPGA bitstream, just a bare CPU.
 16 
 17 config SOC_TZ1090
 18         bool "Toumaz Xenif TZ1090 SoC (Comet)"
 19         select ARCH_WANT_OPTIONAL_GPIOLIB
 20         select IMGPDC_IRQ
 21         select METAG_LNKGET_AROUND_CACHE
 22         select METAG_META21
 23         select METAG_SMP_WRITE_REORDERING
 24         select PINCTRL
 25         select PINCTRL_TZ1090
 26         select PINCTRL_TZ1090_PDC
 27         help
 28           This is a Toumaz Technology Xenif TZ1090 (A.K.A. Comet) SoC containing
 29           a 2-threaded HTP.
 30 
 31 endchoice
 32 
 33 menu "SoC configuration"
 34 
 35 if METAG_META21
 36 
 37 # Meta 2.x specific options
 38 
 39 config METAG_META21_MMU
 40         bool "Meta 2.x MMU mode"
 41         default y
 42         help
 43           Use the Meta 2.x MMU in extended mode.
 44 
 45 config METAG_UNALIGNED
 46         bool "Meta 2.x unaligned access checking"
 47         default y
 48         help
 49           All memory accesses will be checked for alignment and an exception
 50           raised on unaligned accesses. This feature does cost performance
 51           but without it there will be no notification of this type of error.
 52 
 53 config METAG_USER_TCM
 54         bool "Meta on-chip memory support for userland"
 55         select GENERIC_ALLOCATOR
 56         default y
 57         help
 58           Allow the on-chip memories of Meta SoCs to be used by user
 59           applications.
 60 
 61 endif
 62 
 63 config METAG_HALT_ON_PANIC
 64         bool "Halt the core on panic"
 65         help
 66           Halt the core when a panic occurs. This is useful when running
 67           pre-production silicon or in an FPGA environment.
 68 
 69 endmenu

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