• source navigation • diff markup • identifier search • freetext search •
Version: 2.6.24 2.6.25 2.6.26 2.6.27 2.6.28 2.6.29 2.6.30 2.6.31 2.6.32 2.6.33 2.6.34
Architecture: x86 arm avr32 blackfin m68k m68knommu microblaze mips powerpc sh
1 /* 2 * Simple synchronous serial port driver for ETRAX 100LX. 3 * 4 * Synchronous serial ports are used for continuous streamed data like audio. 5 * The default setting for this driver is compatible with the STA 013 MP3 6 * decoder. The driver can easily be tuned to fit other audio encoder/decoders 7 * and SPI 8 * 9 * Copyright (c) 2001-2008 Axis Communications AB 10 * 11 * Author: Mikael Starvik, Johan Adolfsson 12 * 13 */ 14 #include <linux/module.h> 15 #include <linux/kernel.h> 16 #include <linux/types.h> 17 #include <linux/errno.h> 18 #include <linux/major.h> 19 #include <linux/sched.h> 20 #include <linux/interrupt.h> 21 #include <linux/poll.h> 22 #include <linux/init.h> 23 #include <linux/smp_lock.h> 24 #include <linux/timer.h> 25 #include <asm/irq.h> 26 #include <asm/dma.h> 27 #include <asm/io.h> 28 #include <arch/svinto.h> 29 #include <asm/uaccess.h> 30 #include <asm/system.h> 31 #include <asm/sync_serial.h> 32 #include <arch/io_interface_mux.h> 33 34 /* The receiver is a bit tricky beacuse of the continuous stream of data.*/ 35 /* */ 36 /* Three DMA descriptors are linked together. Each DMA descriptor is */ 37 /* responsible for port->bufchunk of a common buffer. */ 38 /* */ 39 /* +---------------------------------------------+ */ 40 /* | +----------+ +----------+ +----------+ | */ 41 /* +-> | Descr[0] |-->| Descr[1] |-->| Descr[2] |-+ */ 42 /* +----------+ +----------+ +----------+ */ 43 /* | | | */ 44 /* v v v */ 45 /* +-------------------------------------+ */ 46 /* | BUFFER | */ 47 /* +-------------------------------------+ */ 48 /* |<- data_avail ->| */ 49 /* readp writep */ 50 /* */ 51 /* If the application keeps up the pace readp will be right after writep.*/ 52 /* If the application can't keep the pace we have to throw away data. */ 53 /* The idea is that readp should be ready with the data pointed out by */ 54 /* Descr[i] when the DMA has filled in Descr[i+1]. */ 55 /* Otherwise we will discard */ 56 /* the rest of the data pointed out by Descr1 and set readp to the start */ 57 /* of Descr2 */ 58 59 #define SYNC_SERIAL_MAJOR 125 60 61 /* IN_BUFFER_SIZE should be a multiple of 6 to make sure that 24 bit */ 62 /* words can be handled */ 63 #define IN_BUFFER_SIZE 12288 64 #define IN_DESCR_SIZE 256 65 #define NUM_IN_DESCR (IN_BUFFER_SIZE/IN_DESCR_SIZE) 66 #define OUT_BUFFER_SIZE 4096 67 68 #define DEFAULT_FRAME_RATE 0 69 #define DEFAULT_WORD_RATE 7 70 71 /* NOTE: Enabling some debug will likely cause overrun or underrun, 72 * especially if manual mode is use. 73 */ 74 #define DEBUG(x) 75 #define DEBUGREAD(x) 76 #define DEBUGWRITE(x) 77 #define DEBUGPOLL(x) 78 #define DEBUGRXINT(x) 79 #define DEBUGTXINT(x) 80 81 /* Define some macros to access ETRAX 100 registers */ 82 #define SETF(var, reg, field, val) \ 83 do { \ 84 var = (var & ~IO_MASK_(reg##_, field##_)) | \ 85 IO_FIELD_(reg##_, field##_, val); \ 86 } while (0) 87 88 #define SETS(var, reg, field, val) \ 89 do { \ 90 var = (var & ~IO_MASK_(reg##_, field##_)) | \ 91 IO_STATE_(reg##_, field##_, _##val); \ 92 } while (0) 93 94 struct sync_port { 95 /* Etrax registers and bits*/ 96 const volatile unsigned *const status; 97 volatile unsigned *const ctrl_data; 98 volatile unsigned *const output_dma_first; 99 volatile unsigned char *const output_dma_cmd; 100 volatile unsigned char *const output_dma_clr_irq; 101 volatile unsigned *const input_dma_first; 102 volatile unsigned char *const input_dma_cmd; 103 volatile unsigned *const input_dma_descr; 104 /* 8*4 */ 105 volatile unsigned char *const input_dma_clr_irq; 106 volatile unsigned *const data_out; 107 const volatile unsigned *const data_in; 108 char data_avail_bit; /* In R_IRQ_MASK1_RD/SET/CLR */ 109 char transmitter_ready_bit; /* In R_IRQ_MASK1_RD/SET/CLR */ 110 char input_dma_descr_bit; /* In R_IRQ_MASK2_RD */ 111 112 char output_dma_bit; /* In R_IRQ_MASK2_RD */ 113 /* End of fields initialised in array */ 114 char started; /* 1 if port has been started */ 115 char port_nbr; /* Port 0 or 1 */ 116 char busy; /* 1 if port is busy */ 117 118 char enabled; /* 1 if port is enabled */ 119 char use_dma; /* 1 if port uses dma */ 120 char tr_running; 121 122 char init_irqs; 123 124 /* Register shadow */ 125 unsigned int ctrl_data_shadow; 126 /* Remaining bytes for current transfer */ 127 volatile unsigned int out_count; 128 /* Current position in out_buffer */ 129 unsigned char *outp; 130 /* 16*4 */ 131 /* Next byte to be read by application */ 132 volatile unsigned char *volatile readp; 133 /* Next byte to be written by etrax */ 134 volatile unsigned char *volatile writep; 135 136 unsigned int in_buffer_size; 137 unsigned int inbufchunk; 138 struct etrax_dma_descr out_descr __attribute__ ((aligned(32))); 139 struct etrax_dma_descr in_descr[NUM_IN_DESCR] __attribute__ ((aligned(32))); 140 unsigned char out_buffer[OUT_BUFFER_SIZE] __attribute__ ((aligned(32))); 141 unsigned char in_buffer[IN_BUFFER_SIZE]__attribute__ ((aligned(32))); 142 unsigned char flip[IN_BUFFER_SIZE] __attribute__ ((aligned(32))); 143 struct etrax_dma_descr *next_rx_desc; 144 struct etrax_dma_descr *prev_rx_desc; 145 int full; 146 147 wait_queue_head_t out_wait_q; 148 wait_queue_head_t in_wait_q; 149 }; 150 151 152 static int etrax_sync_serial_init(void); 153 static void initialize_port(int portnbr); 154 static inline int sync_data_avail(struct sync_port *port); 155 156 static int sync_serial_open(struct inode *inode, struct file *file); 157 static int sync_serial_release(struct inode *inode, struct file *file); 158 static unsigned int sync_serial_poll(struct file *filp, poll_table *wait); 159 160 static int sync_serial_ioctl(struct inode *inode, struct file *file, 161 unsigned int cmd, unsigned long arg); 162 static ssize_t sync_serial_write(struct file *file, const char *buf, 163 size_t count, loff_t *ppos); 164 static ssize_t sync_serial_read(struct file *file, char *buf, 165 size_t count, loff_t *ppos); 166 167 #if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \ 168 defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \ 169 (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \ 170 defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))) 171 #define SYNC_SER_DMA 172 #endif 173 174 static void send_word(struct sync_port *port); 175 static void start_dma(struct sync_port *port, const char *data, int count); 176 static void start_dma_in(struct sync_port *port); 177 #ifdef SYNC_SER_DMA 178 static irqreturn_t tr_interrupt(int irq, void *dev_id); 179 static irqreturn_t rx_interrupt(int irq, void *dev_id); 180 #endif 181 #if ((defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) && \ 182 !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA)) || \ 183 (defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) && \ 184 !defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA))) 185 #define SYNC_SER_MANUAL 186 #endif 187 #ifdef SYNC_SER_MANUAL 188 static irqreturn_t manual_interrupt(int irq, void *dev_id); 189 #endif 190 191 /* The ports */ 192 static struct sync_port ports[] = { 193 { 194 .status = R_SYNC_SERIAL1_STATUS, 195 .ctrl_data = R_SYNC_SERIAL1_CTRL, 196 .output_dma_first = R_DMA_CH8_FIRST, 197 .output_dma_cmd = R_DMA_CH8_CMD, 198 .output_dma_clr_irq = R_DMA_CH8_CLR_INTR, 199 .input_dma_first = R_DMA_CH9_FIRST, 200 .input_dma_cmd = R_DMA_CH9_CMD, 201 .input_dma_descr = R_DMA_CH9_DESCR, 202 .input_dma_clr_irq = R_DMA_CH9_CLR_INTR, 203 .data_out = R_SYNC_SERIAL1_TR_DATA, 204 .data_in = R_SYNC_SERIAL1_REC_DATA, 205 .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_data), 206 .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser1_ready), 207 .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma9_descr), 208 .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma8_eop), 209 .init_irqs = 1, 210 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA) 211 .use_dma = 1, 212 #else 213 .use_dma = 0, 214 #endif 215 }, 216 { 217 .status = R_SYNC_SERIAL3_STATUS, 218 .ctrl_data = R_SYNC_SERIAL3_CTRL, 219 .output_dma_first = R_DMA_CH4_FIRST, 220 .output_dma_cmd = R_DMA_CH4_CMD, 221 .output_dma_clr_irq = R_DMA_CH4_CLR_INTR, 222 .input_dma_first = R_DMA_CH5_FIRST, 223 .input_dma_cmd = R_DMA_CH5_CMD, 224 .input_dma_descr = R_DMA_CH5_DESCR, 225 .input_dma_clr_irq = R_DMA_CH5_CLR_INTR, 226 .data_out = R_SYNC_SERIAL3_TR_DATA, 227 .data_in = R_SYNC_SERIAL3_REC_DATA, 228 .data_avail_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_data), 229 .transmitter_ready_bit = IO_BITNR(R_IRQ_MASK1_RD, ser3_ready), 230 .input_dma_descr_bit = IO_BITNR(R_IRQ_MASK2_RD, dma5_descr), 231 .output_dma_bit = IO_BITNR(R_IRQ_MASK2_RD, dma4_eop), 232 .init_irqs = 1, 233 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA) 234 .use_dma = 1, 235 #else 236 .use_dma = 0, 237 #endif 238 } 239 }; 240 241 /* Register shadows */ 242 static unsigned sync_serial_prescale_shadow; 243 244 #define NUMBER_OF_PORTS 2 245 246 static const struct file_operations sync_serial_fops = { 247 .owner = THIS_MODULE, 248 .write = sync_serial_write, 249 .read = sync_serial_read, 250 .poll = sync_serial_poll, 251 .ioctl = sync_serial_ioctl, 252 .open = sync_serial_open, 253 .release = sync_serial_release 254 }; 255 256 static int __init etrax_sync_serial_init(void) 257 { 258 ports[0].enabled = 0; 259 ports[1].enabled = 0; 260 261 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) 262 if (cris_request_io_interface(if_sync_serial_1, "sync_ser1")) { 263 printk(KERN_CRIT "ETRAX100LX sync_serial: " 264 "Could not allocate IO group for port %d\n", 0); 265 return -EBUSY; 266 } 267 #endif 268 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) 269 if (cris_request_io_interface(if_sync_serial_3, "sync_ser3")) { 270 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) 271 cris_free_io_interface(if_sync_serial_1); 272 #endif 273 printk(KERN_CRIT "ETRAX100LX sync_serial: " 274 "Could not allocate IO group for port %d\n", 1); 275 return -EBUSY; 276 } 277 #endif 278 279 if (register_chrdev(SYNC_SERIAL_MAJOR, "sync serial", 280 &sync_serial_fops) < 0) { 281 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) 282 cris_free_io_interface(if_sync_serial_3); 283 #endif 284 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) 285 cris_free_io_interface(if_sync_serial_1); 286 #endif 287 printk("unable to get major for synchronous serial port\n"); 288 return -EBUSY; 289 } 290 291 /* Deselect synchronous serial ports while configuring. */ 292 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async); 293 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async); 294 *R_GEN_CONFIG_II = gen_config_ii_shadow; 295 296 /* Initialize Ports */ 297 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT0) 298 ports[0].enabled = 1; 299 SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser1, ss1extra); 300 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync); 301 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL0_DMA) 302 ports[0].use_dma = 1; 303 #else 304 ports[0].use_dma = 0; 305 #endif 306 initialize_port(0); 307 #endif 308 309 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL_PORT1) 310 ports[1].enabled = 1; 311 SETS(port_pb_i2c_shadow, R_PORT_PB_I2C, syncser3, ss3extra); 312 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync); 313 #if defined(CONFIG_ETRAX_SYNCHRONOUS_SERIAL1_DMA) 314 ports[1].use_dma = 1; 315 #else 316 ports[1].use_dma = 0; 317 #endif 318 initialize_port(1); 319 #endif 320 321 *R_PORT_PB_I2C = port_pb_i2c_shadow; /* Use PB4/PB7 */ 322 323 /* Set up timing */ 324 *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow = ( 325 IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u1, codec) | 326 IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u1, external) | 327 IO_STATE(R_SYNC_SERIAL_PRESCALE, clk_sel_u3, codec) | 328 IO_STATE(R_SYNC_SERIAL_PRESCALE, word_stb_sel_u3, external) | 329 IO_STATE(R_SYNC_SERIAL_PRESCALE, prescaler, div4) | 330 IO_FIELD(R_SYNC_SERIAL_PRESCALE, frame_rate, 331 DEFAULT_FRAME_RATE) | 332 IO_FIELD(R_SYNC_SERIAL_PRESCALE, word_rate, DEFAULT_WORD_RATE) | 333 IO_STATE(R_SYNC_SERIAL_PRESCALE, warp_mode, normal)); 334 335 /* Select synchronous ports */ 336 *R_GEN_CONFIG_II = gen_config_ii_shadow; 337 338 printk(KERN_INFO "ETRAX 100LX synchronous serial port driver\n"); 339 return 0; 340 } 341 342 static void __init initialize_port(int portnbr) 343 { 344 struct sync_port *port = &ports[portnbr]; 345 346 DEBUG(printk(KERN_DEBUG "Init sync serial port %d\n", portnbr)); 347 348 port->started = 0; 349 port->port_nbr = portnbr; 350 port->busy = 0; 351 port->tr_running = 0; 352 353 port->out_count = 0; 354 port->outp = port->out_buffer; 355 356 port->readp = port->flip; 357 port->writep = port->flip; 358 port->in_buffer_size = IN_BUFFER_SIZE; 359 port->inbufchunk = IN_DESCR_SIZE; 360 port->next_rx_desc = &port->in_descr[0]; 361 port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR-1]; 362 port->prev_rx_desc->ctrl = d_eol; 363 364 init_waitqueue_head(&port->out_wait_q); 365 init_waitqueue_head(&port->in_wait_q); 366 367 port->ctrl_data_shadow = 368 IO_STATE(R_SYNC_SERIAL1_CTRL, tr_baud, c115k2Hz) | 369 IO_STATE(R_SYNC_SERIAL1_CTRL, mode, master_output) | 370 IO_STATE(R_SYNC_SERIAL1_CTRL, error, ignore) | 371 IO_STATE(R_SYNC_SERIAL1_CTRL, rec_enable, disable) | 372 IO_STATE(R_SYNC_SERIAL1_CTRL, f_synctype, normal) | 373 IO_STATE(R_SYNC_SERIAL1_CTRL, f_syncsize, word) | 374 IO_STATE(R_SYNC_SERIAL1_CTRL, f_sync, on) | 375 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_mode, normal) | 376 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_halt, stopped) | 377 IO_STATE(R_SYNC_SERIAL1_CTRL, bitorder, msb) | 378 IO_STATE(R_SYNC_SERIAL1_CTRL, tr_enable, disable) | 379 IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit) | 380 IO_STATE(R_SYNC_SERIAL1_CTRL, buf_empty, lmt_8) | 381 IO_STATE(R_SYNC_SERIAL1_CTRL, buf_full, lmt_8) | 382 IO_STATE(R_SYNC_SERIAL1_CTRL, flow_ctrl, enabled) | 383 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_polarity, neg) | 384 IO_STATE(R_SYNC_SERIAL1_CTRL, frame_polarity, normal)| 385 IO_STATE(R_SYNC_SERIAL1_CTRL, status_polarity, inverted)| 386 IO_STATE(R_SYNC_SERIAL1_CTRL, clk_driver, normal) | 387 IO_STATE(R_SYNC_SERIAL1_CTRL, frame_driver, normal) | 388 IO_STATE(R_SYNC_SERIAL1_CTRL, status_driver, normal)| 389 IO_STATE(R_SYNC_SERIAL1_CTRL, def_out0, high); 390 391 if (port->use_dma) 392 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL, 393 dma_enable, on); 394 else 395 port->ctrl_data_shadow |= IO_STATE(R_SYNC_SERIAL1_CTRL, 396 dma_enable, off); 397 398 *port->ctrl_data = port->ctrl_data_shadow; 399 } 400 401 static inline int sync_data_avail(struct sync_port *port) 402 { 403 int avail; 404 unsigned char *start; 405 unsigned char *end; 406 407 start = (unsigned char *)port->readp; /* cast away volatile */ 408 end = (unsigned char *)port->writep; /* cast away volatile */ 409 /* 0123456789 0123456789 410 * ----- - ----- 411 * ^rp ^wp ^wp ^rp 412 */ 413 if (end >= start) 414 avail = end - start; 415 else 416 avail = port->in_buffer_size - (start - end); 417 return avail; 418 } 419 420 static inline int sync_data_avail_to_end(struct sync_port *port) 421 { 422 int avail; 423 unsigned char *start; 424 unsigned char *end; 425 426 start = (unsigned char *)port->readp; /* cast away volatile */ 427 end = (unsigned char *)port->writep; /* cast away volatile */ 428 /* 0123456789 0123456789 429 * ----- ----- 430 * ^rp ^wp ^wp ^rp 431 */ 432 433 if (end >= start) 434 avail = end - start; 435 else 436 avail = port->flip + port->in_buffer_size - start; 437 return avail; 438 } 439 440 441 static int sync_serial_open(struct inode *inode, struct file *file) 442 { 443 int dev = MINOR(inode->i_rdev); 444 struct sync_port *port; 445 int mode; 446 int err = -EBUSY; 447 448 lock_kernel(); 449 DEBUG(printk(KERN_DEBUG "Open sync serial port %d\n", dev)); 450 451 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { 452 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); 453 err = -ENODEV; 454 goto out; 455 } 456 port = &ports[dev]; 457 /* Allow open this device twice (assuming one reader and one writer) */ 458 if (port->busy == 2) { 459 DEBUG(printk(KERN_DEBUG "Device is busy.. \n")); 460 goto out; 461 } 462 if (port->init_irqs) { 463 if (port->use_dma) { 464 if (port == &ports[0]) { 465 #ifdef SYNC_SER_DMA 466 if (request_irq(24, tr_interrupt, 0, 467 "synchronous serial 1 dma tr", 468 &ports[0])) { 469 printk(KERN_CRIT "Can't alloc " 470 "sync serial port 1 IRQ"); 471 goto out; 472 } else if (request_irq(25, rx_interrupt, 0, 473 "synchronous serial 1 dma rx", 474 &ports[0])) { 475 free_irq(24, &port[0]); 476 printk(KERN_CRIT "Can't alloc " 477 "sync serial port 1 IRQ"); 478 goto out; 479 } else if (cris_request_dma(8, 480 "synchronous serial 1 dma tr", 481 DMA_VERBOSE_ON_ERROR, 482 dma_ser1)) { 483 free_irq(24, &port[0]); 484 free_irq(25, &port[0]); 485 printk(KERN_CRIT "Can't alloc " 486 "sync serial port 1 " 487 "TX DMA channel"); 488 goto out; 489 } else if (cris_request_dma(9, 490 "synchronous serial 1 dma rec", 491 DMA_VERBOSE_ON_ERROR, 492 dma_ser1)) { 493 cris_free_dma(8, NULL); 494 free_irq(24, &port[0]); 495 free_irq(25, &port[0]); 496 printk(KERN_CRIT "Can't alloc " 497 "sync serial port 1 " 498 "RX DMA channel"); 499 goto out; 500 } 501 #endif 502 RESET_DMA(8); WAIT_DMA(8); 503 RESET_DMA(9); WAIT_DMA(9); 504 *R_DMA_CH8_CLR_INTR = 505 IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, 506 do) | 507 IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, 508 do); 509 *R_DMA_CH9_CLR_INTR = 510 IO_STATE(R_DMA_CH9_CLR_INTR, clr_eop, 511 do) | 512 IO_STATE(R_DMA_CH9_CLR_INTR, clr_descr, 513 do); 514 *R_IRQ_MASK2_SET = 515 IO_STATE(R_IRQ_MASK2_SET, dma8_eop, 516 set) | 517 IO_STATE(R_IRQ_MASK2_SET, dma9_descr, 518 set); 519 } else if (port == &ports[1]) { 520 #ifdef SYNC_SER_DMA 521 if (request_irq(20, tr_interrupt, 0, 522 "synchronous serial 3 dma tr", 523 &ports[1])) { 524 printk(KERN_CRIT "Can't alloc " 525 "sync serial port 3 IRQ"); 526 goto out; 527 } else if (request_irq(21, rx_interrupt, 0, 528 "synchronous serial 3 dma rx", 529 &ports[1])) { 530 free_irq(20, &ports[1]); 531 printk(KERN_CRIT "Can't alloc " 532 "sync serial port 3 IRQ"); 533 goto out; 534 } else if (cris_request_dma(4, 535 "synchronous serial 3 dma tr", 536 DMA_VERBOSE_ON_ERROR, 537 dma_ser3)) { 538 free_irq(21, &ports[1]); 539 free_irq(20, &ports[1]); 540 printk(KERN_CRIT "Can't alloc " 541 "sync serial port 3 " 542 "TX DMA channel"); 543 goto out; 544 } else if (cris_request_dma(5, 545 "synchronous serial 3 dma rec", 546 DMA_VERBOSE_ON_ERROR, 547 dma_ser3)) { 548 cris_free_dma(4, NULL); 549 free_irq(21, &ports[1]); 550 free_irq(20, &ports[1]); 551 printk(KERN_CRIT "Can't alloc " 552 "sync serial port 3 " 553 "RX DMA channel"); 554 goto out; 555 } 556 #endif 557 RESET_DMA(4); WAIT_DMA(4); 558 RESET_DMA(5); WAIT_DMA(5); 559 *R_DMA_CH4_CLR_INTR = 560 IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, 561 do) | 562 IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, 563 do); 564 *R_DMA_CH5_CLR_INTR = 565 IO_STATE(R_DMA_CH5_CLR_INTR, clr_eop, 566 do) | 567 IO_STATE(R_DMA_CH5_CLR_INTR, clr_descr, 568 do); 569 *R_IRQ_MASK2_SET = 570 IO_STATE(R_IRQ_MASK2_SET, dma4_eop, 571 set) | 572 IO_STATE(R_IRQ_MASK2_SET, dma5_descr, 573 set); 574 } 575 start_dma_in(port); 576 port->init_irqs = 0; 577 } else { /* !port->use_dma */ 578 #ifdef SYNC_SER_MANUAL 579 if (port == &ports[0]) { 580 if (request_irq(8, 581 manual_interrupt, 582 IRQF_SHARED | IRQF_DISABLED, 583 "synchronous serial manual irq", 584 &ports[0])) { 585 printk(KERN_CRIT "Can't alloc " 586 "sync serial manual irq"); 587 goto out; 588 } 589 } else if (port == &ports[1]) { 590 if (request_irq(8, 591 manual_interrupt, 592 IRQF_SHARED | IRQF_DISABLED, 593 "synchronous serial manual irq", 594 &ports[1])) { 595 printk(KERN_CRIT "Can't alloc " 596 "sync serial manual irq"); 597 goto out; 598 } 599 } 600 port->init_irqs = 0; 601 #else 602 panic("sync_serial: Manual mode not supported.\n"); 603 #endif /* SYNC_SER_MANUAL */ 604 } 605 } /* port->init_irqs */ 606 607 port->busy++; 608 /* Start port if we use it as input */ 609 mode = IO_EXTRACT(R_SYNC_SERIAL1_CTRL, mode, port->ctrl_data_shadow); 610 if (mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_input) || 611 mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_input) || 612 mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, master_bidir) || 613 mode == IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, mode, slave_bidir)) { 614 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, 615 running); 616 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, 617 enable); 618 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, 619 enable); 620 port->started = 1; 621 *port->ctrl_data = port->ctrl_data_shadow; 622 if (!port->use_dma) 623 *R_IRQ_MASK1_SET = 1 << port->data_avail_bit; 624 DEBUG(printk(KERN_DEBUG "sser%d rec started\n", dev)); 625 } 626 ret = 0; 627 628 out: 629 unlock_kernel(); 630 return ret; 631 } 632 633 static int sync_serial_release(struct inode *inode, struct file *file) 634 { 635 int dev = MINOR(inode->i_rdev); 636 struct sync_port *port; 637 638 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { 639 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); 640 return -ENODEV; 641 } 642 port = &ports[dev]; 643 if (port->busy) 644 port->busy--; 645 if (!port->busy) 646 *R_IRQ_MASK1_CLR = ((1 << port->data_avail_bit) | 647 (1 << port->transmitter_ready_bit)); 648 649 return 0; 650 } 651 652 653 654 static unsigned int sync_serial_poll(struct file *file, poll_table *wait) 655 { 656 int dev = MINOR(file->f_dentry->d_inode->i_rdev); 657 unsigned int mask = 0; 658 struct sync_port *port; 659 DEBUGPOLL(static unsigned int prev_mask = 0); 660 661 port = &ports[dev]; 662 poll_wait(file, &port->out_wait_q, wait); 663 poll_wait(file, &port->in_wait_q, wait); 664 /* Some room to write */ 665 if (port->out_count < OUT_BUFFER_SIZE) 666 mask |= POLLOUT | POLLWRNORM; 667 /* At least an inbufchunk of data */ 668 if (sync_data_avail(port) >= port->inbufchunk) 669 mask |= POLLIN | POLLRDNORM; 670 671 DEBUGPOLL(if (mask != prev_mask) 672 printk(KERN_DEBUG "sync_serial_poll: mask 0x%08X %s %s\n", 673 mask, 674 mask & POLLOUT ? "POLLOUT" : "", 675 mask & POLLIN ? "POLLIN" : ""); 676 prev_mask = mask; 677 ); 678 return mask; 679 } 680 681 static int sync_serial_ioctl(struct inode *inode, struct file *file, 682 unsigned int cmd, unsigned long arg) 683 { 684 int return_val = 0; 685 unsigned long flags; 686 687 int dev = MINOR(file->f_dentry->d_inode->i_rdev); 688 struct sync_port *port; 689 690 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { 691 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); 692 return -1; 693 } 694 port = &ports[dev]; 695 696 local_irq_save(flags); 697 /* Disable port while changing config */ 698 if (dev) { 699 if (port->use_dma) { 700 RESET_DMA(4); WAIT_DMA(4); 701 port->tr_running = 0; 702 port->out_count = 0; 703 port->outp = port->out_buffer; 704 *R_DMA_CH4_CLR_INTR = 705 IO_STATE(R_DMA_CH4_CLR_INTR, clr_eop, do) | 706 IO_STATE(R_DMA_CH4_CLR_INTR, clr_descr, do); 707 } 708 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, async); 709 } else { 710 if (port->use_dma) { 711 RESET_DMA(8); WAIT_DMA(8); 712 port->tr_running = 0; 713 port->out_count = 0; 714 port->outp = port->out_buffer; 715 *R_DMA_CH8_CLR_INTR = 716 IO_STATE(R_DMA_CH8_CLR_INTR, clr_eop, do) | 717 IO_STATE(R_DMA_CH8_CLR_INTR, clr_descr, do); 718 } 719 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, async); 720 } 721 *R_GEN_CONFIG_II = gen_config_ii_shadow; 722 local_irq_restore(flags); 723 724 switch (cmd) { 725 case SSP_SPEED: 726 if (GET_SPEED(arg) == CODEC) { 727 if (dev) 728 SETS(sync_serial_prescale_shadow, 729 R_SYNC_SERIAL_PRESCALE, clk_sel_u3, 730 codec); 731 else 732 SETS(sync_serial_prescale_shadow, 733 R_SYNC_SERIAL_PRESCALE, clk_sel_u1, 734 codec); 735 736 SETF(sync_serial_prescale_shadow, 737 R_SYNC_SERIAL_PRESCALE, prescaler, 738 GET_FREQ(arg)); 739 SETF(sync_serial_prescale_shadow, 740 R_SYNC_SERIAL_PRESCALE, frame_rate, 741 GET_FRAME_RATE(arg)); 742 SETF(sync_serial_prescale_shadow, 743 R_SYNC_SERIAL_PRESCALE, word_rate, 744 GET_WORD_RATE(arg)); 745 } else { 746 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 747 tr_baud, GET_SPEED(arg)); 748 if (dev) 749 SETS(sync_serial_prescale_shadow, 750 R_SYNC_SERIAL_PRESCALE, clk_sel_u3, 751 baudrate); 752 else 753 SETS(sync_serial_prescale_shadow, 754 R_SYNC_SERIAL_PRESCALE, clk_sel_u1, 755 baudrate); 756 } 757 break; 758 case SSP_MODE: 759 if (arg > 5) 760 return -EINVAL; 761 if (arg == MASTER_OUTPUT || arg == SLAVE_OUTPUT) 762 *R_IRQ_MASK1_CLR = 1 << port->data_avail_bit; 763 else if (!port->use_dma) 764 *R_IRQ_MASK1_SET = 1 << port->data_avail_bit; 765 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, mode, arg); 766 break; 767 case SSP_FRAME_SYNC: 768 if (arg & NORMAL_SYNC) 769 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 770 f_synctype, normal); 771 else if (arg & EARLY_SYNC) 772 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 773 f_synctype, early); 774 775 if (arg & BIT_SYNC) 776 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 777 f_syncsize, bit); 778 else if (arg & WORD_SYNC) 779 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 780 f_syncsize, word); 781 else if (arg & EXTENDED_SYNC) 782 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 783 f_syncsize, extended); 784 785 if (arg & SYNC_ON) 786 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 787 f_sync, on); 788 else if (arg & SYNC_OFF) 789 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 790 f_sync, off); 791 792 if (arg & WORD_SIZE_8) 793 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 794 wordsize, size8bit); 795 else if (arg & WORD_SIZE_12) 796 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 797 wordsize, size12bit); 798 else if (arg & WORD_SIZE_16) 799 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 800 wordsize, size16bit); 801 else if (arg & WORD_SIZE_24) 802 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 803 wordsize, size24bit); 804 else if (arg & WORD_SIZE_32) 805 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 806 wordsize, size32bit); 807 808 if (arg & BIT_ORDER_MSB) 809 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 810 bitorder, msb); 811 else if (arg & BIT_ORDER_LSB) 812 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 813 bitorder, lsb); 814 815 if (arg & FLOW_CONTROL_ENABLE) 816 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 817 flow_ctrl, enabled); 818 else if (arg & FLOW_CONTROL_DISABLE) 819 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 820 flow_ctrl, disabled); 821 822 if (arg & CLOCK_NOT_GATED) 823 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 824 clk_mode, normal); 825 else if (arg & CLOCK_GATED) 826 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 827 clk_mode, gated); 828 829 break; 830 case SSP_IPOLARITY: 831 /* NOTE!! negedge is considered NORMAL */ 832 if (arg & CLOCK_NORMAL) 833 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 834 clk_polarity, neg); 835 else if (arg & CLOCK_INVERT) 836 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 837 clk_polarity, pos); 838 839 if (arg & FRAME_NORMAL) 840 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 841 frame_polarity, normal); 842 else if (arg & FRAME_INVERT) 843 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 844 frame_polarity, inverted); 845 846 if (arg & STATUS_NORMAL) 847 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 848 status_polarity, normal); 849 else if (arg & STATUS_INVERT) 850 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 851 status_polarity, inverted); 852 break; 853 case SSP_OPOLARITY: 854 if (arg & CLOCK_NORMAL) 855 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 856 clk_driver, normal); 857 else if (arg & CLOCK_INVERT) 858 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 859 clk_driver, inverted); 860 861 if (arg & FRAME_NORMAL) 862 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 863 frame_driver, normal); 864 else if (arg & FRAME_INVERT) 865 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 866 frame_driver, inverted); 867 868 if (arg & STATUS_NORMAL) 869 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 870 status_driver, normal); 871 else if (arg & STATUS_INVERT) 872 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 873 status_driver, inverted); 874 break; 875 case SSP_SPI: 876 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, flow_ctrl, 877 disabled); 878 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, bitorder, 879 msb); 880 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, wordsize, 881 size8bit); 882 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_sync, on); 883 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_syncsize, 884 word); 885 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, f_synctype, 886 normal); 887 if (arg & SPI_SLAVE) { 888 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 889 frame_polarity, inverted); 890 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 891 clk_polarity, neg); 892 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 893 mode, SLAVE_INPUT); 894 } else { 895 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 896 frame_driver, inverted); 897 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 898 clk_driver, inverted); 899 SETF(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, 900 mode, MASTER_OUTPUT); 901 } 902 break; 903 case SSP_INBUFCHUNK: 904 #if 0 905 if (arg > port->in_buffer_size/NUM_IN_DESCR) 906 return -EINVAL; 907 port->inbufchunk = arg; 908 /* Make sure in_buffer_size is a multiple of inbufchunk */ 909 port->in_buffer_size = 910 (port->in_buffer_size/port->inbufchunk) * 911 port->inbufchunk; 912 DEBUG(printk(KERN_DEBUG "inbufchunk %i in_buffer_size: %i\n", 913 port->inbufchunk, port->in_buffer_size)); 914 if (port->use_dma) { 915 if (port->port_nbr == 0) { 916 RESET_DMA(9); 917 WAIT_DMA(9); 918 } else { 919 RESET_DMA(5); 920 WAIT_DMA(5); 921 } 922 start_dma_in(port); 923 } 924 #endif 925 break; 926 default: 927 return_val = -1; 928 } 929 /* Make sure we write the config without interruption */ 930 local_irq_save(flags); 931 /* Set config and enable port */ 932 *port->ctrl_data = port->ctrl_data_shadow; 933 nop(); nop(); nop(); nop(); 934 *R_SYNC_SERIAL_PRESCALE = sync_serial_prescale_shadow; 935 nop(); nop(); nop(); nop(); 936 if (dev) 937 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode3, sync); 938 else 939 SETS(gen_config_ii_shadow, R_GEN_CONFIG_II, sermode1, sync); 940 941 *R_GEN_CONFIG_II = gen_config_ii_shadow; 942 /* Reset DMA. At readout from serial port the data could be shifted 943 * one byte if not resetting DMA. 944 */ 945 if (port->use_dma) { 946 if (port->port_nbr == 0) { 947 RESET_DMA(9); 948 WAIT_DMA(9); 949 } else { 950 RESET_DMA(5); 951 WAIT_DMA(5); 952 } 953 start_dma_in(port); 954 } 955 local_irq_restore(flags); 956 return return_val; 957 } 958 959 960 static ssize_t sync_serial_write(struct file *file, const char *buf, 961 size_t count, loff_t *ppos) 962 { 963 int dev = MINOR(file->f_dentry->d_inode->i_rdev); 964 DECLARE_WAITQUEUE(wait, current); 965 struct sync_port *port; 966 unsigned long flags; 967 unsigned long c, c1; 968 unsigned long free_outp; 969 unsigned long outp; 970 unsigned long out_buffer; 971 972 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { 973 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); 974 return -ENODEV; 975 } 976 port = &ports[dev]; 977 978 DEBUGWRITE(printk(KERN_DEBUG "W d%d c %lu (%d/%d)\n", 979 port->port_nbr, count, port->out_count, OUT_BUFFER_SIZE)); 980 /* Space to end of buffer */ 981 /* 982 * out_buffer <c1>012345<- c ->OUT_BUFFER_SIZE 983 * outp^ +out_count 984 * ^free_outp 985 * out_buffer 45<- c ->0123OUT_BUFFER_SIZE 986 * +out_count outp^ 987 * free_outp 988 * 989 */ 990 991 /* Read variables that may be updated by interrupts */ 992 local_irq_save(flags); 993 if (count > OUT_BUFFER_SIZE - port->out_count) 994 count = OUT_BUFFER_SIZE - port->out_count; 995 996 outp = (unsigned long)port->outp; 997 free_outp = outp + port->out_count; 998 local_irq_restore(flags); 999 out_buffer = (unsigned long)port->out_buffer; 1000 1001 /* Find out where and how much to write */ 1002 if (free_outp >= out_buffer + OUT_BUFFER_SIZE) 1003 free_outp -= OUT_BUFFER_SIZE; 1004 if (free_outp >= outp) 1005 c = out_buffer + OUT_BUFFER_SIZE - free_outp; 1006 else 1007 c = outp - free_outp; 1008 if (c > count) 1009 c = count; 1010 1011 DEBUGWRITE(printk(KERN_DEBUG "w op %08lX fop %08lX c %lu\n", 1012 outp, free_outp, c)); 1013 if (copy_from_user((void *)free_outp, buf, c)) 1014 return -EFAULT; 1015 1016 if (c != count) { 1017 buf += c; 1018 c1 = count - c; 1019 DEBUGWRITE(printk(KERN_DEBUG "w2 fi %lu c %lu c1 %lu\n", 1020 free_outp-out_buffer, c, c1)); 1021 if (copy_from_user((void *)out_buffer, buf, c1)) 1022 return -EFAULT; 1023 } 1024 local_irq_save(flags); 1025 port->out_count += count; 1026 local_irq_restore(flags); 1027 1028 /* Make sure transmitter/receiver is running */ 1029 if (!port->started) { 1030 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, 1031 running); 1032 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, 1033 enable); 1034 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, 1035 enable); 1036 port->started = 1; 1037 } 1038 1039 *port->ctrl_data = port->ctrl_data_shadow; 1040 1041 if (file->f_flags & O_NONBLOCK) { 1042 local_irq_save(flags); 1043 if (!port->tr_running) { 1044 if (!port->use_dma) { 1045 /* Start sender by writing data */ 1046 send_word(port); 1047 /* and enable transmitter ready IRQ */ 1048 *R_IRQ_MASK1_SET = 1 << 1049 port->transmitter_ready_bit; 1050 } else 1051 start_dma(port, 1052 (unsigned char *volatile)port->outp, c); 1053 } 1054 local_irq_restore(flags); 1055 DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu NB\n", 1056 port->port_nbr, count)); 1057 return count; 1058 } 1059 1060 /* Sleep until all sent */ 1061 add_wait_queue(&port->out_wait_q, &wait); 1062 set_current_state(TASK_INTERRUPTIBLE); 1063 local_irq_save(flags); 1064 if (!port->tr_running) { 1065 if (!port->use_dma) { 1066 /* Start sender by writing data */ 1067 send_word(port); 1068 /* and enable transmitter ready IRQ */ 1069 *R_IRQ_MASK1_SET = 1 << port->transmitter_ready_bit; 1070 } else 1071 start_dma(port, port->outp, c); 1072 } 1073 local_irq_restore(flags); 1074 schedule(); 1075 set_current_state(TASK_RUNNING); 1076 remove_wait_queue(&port->out_wait_q, &wait); 1077 if (signal_pending(current)) 1078 return -EINTR; 1079 1080 DEBUGWRITE(printk(KERN_DEBUG "w d%d c %lu\n", port->port_nbr, count)); 1081 return count; 1082 } 1083 1084 static ssize_t sync_serial_read(struct file *file, char *buf, 1085 size_t count, loff_t *ppos) 1086 { 1087 int dev = MINOR(file->f_dentry->d_inode->i_rdev); 1088 int avail; 1089 struct sync_port *port; 1090 unsigned char *start; 1091 unsigned char *end; 1092 unsigned long flags; 1093 1094 if (dev < 0 || dev >= NUMBER_OF_PORTS || !ports[dev].enabled) { 1095 DEBUG(printk(KERN_DEBUG "Invalid minor %d\n", dev)); 1096 return -ENODEV; 1097 } 1098 port = &ports[dev]; 1099 1100 DEBUGREAD(printk(KERN_DEBUG "R%d c %d ri %lu wi %lu /%lu\n", 1101 dev, count, port->readp - port->flip, 1102 port->writep - port->flip, port->in_buffer_size)); 1103 1104 if (!port->started) { 1105 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, clk_halt, 1106 running); 1107 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, tr_enable, 1108 enable); 1109 SETS(port->ctrl_data_shadow, R_SYNC_SERIAL1_CTRL, rec_enable, 1110 enable); 1111 port->started = 1; 1112 } 1113 *port->ctrl_data = port->ctrl_data_shadow; 1114 1115 /* Calculate number of available bytes */ 1116 /* Save pointers to avoid that they are modified by interrupt */ 1117 local_irq_save(flags); 1118 start = (unsigned char *)port->readp; /* cast away volatile */ 1119 end = (unsigned char *)port->writep; /* cast away volatile */ 1120 local_irq_restore(flags); 1121 while (start == end && !port->full) { 1122 /* No data */ 1123 if (file->f_flags & O_NONBLOCK) 1124 return -EAGAIN; 1125 1126 interruptible_sleep_on(&port->in_wait_q); 1127 if (signal_pending(current)) 1128 return -EINTR; 1129 1130 local_irq_save(flags); 1131 start = (unsigned char *)port->readp; /* cast away volatile */ 1132 end = (unsigned char *)port->writep; /* cast away volatile */ 1133 local_irq_restore(flags); 1134 } 1135 1136 /* Lazy read, never return wrapped data. */ 1137 if (port->full) 1138 avail = port->in_buffer_size; 1139 else if (end > start) 1140 avail = end - start; 1141 else 1142 avail = port->flip + port->in_buffer_size - start; 1143 1144 count = count > avail ? avail : count; 1145 if (copy_to_user(buf, start, count)) 1146 return -EFAULT; 1147 /* Disable interrupts while updating readp */ 1148 local_irq_save(flags); 1149 port->readp += count; 1150 if (port->readp >= port->flip + port->in_buffer_size) /* Wrap? */ 1151 port->readp = port->flip; 1152 port->full = 0; 1153 local_irq_restore(flags); 1154 DEBUGREAD(printk(KERN_DEBUG "r %d\n", count)); 1155 return count; 1156 } 1157 1158 static void send_word(struct sync_port *port) 1159 { 1160 switch (IO_EXTRACT(R_SYNC_SERIAL1_CTRL, wordsize, 1161 port->ctrl_data_shadow)) { 1162 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit): 1163 port->out_count--; 1164 *port->data_out = *port->outp++; 1165 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) 1166 port->outp = port->out_buffer; 1167 break; 1168 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit): 1169 { 1170 int data = (*port->outp++) << 8; 1171 data |= *port->outp++; 1172 port->out_count -= 2; 1173 *port->data_out = data; 1174 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) 1175 port->outp = port->out_buffer; 1176 break; 1177 } 1178 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit): 1179 port->out_count -= 2; 1180 *port->data_out = *(unsigned short *)port->outp; 1181 port->outp += 2; 1182 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) 1183 port->outp = port->out_buffer; 1184 break; 1185 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit): 1186 port->out_count -= 3; 1187 *port->data_out = *(unsigned int *)port->outp; 1188 port->outp += 3; 1189 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) 1190 port->outp = port->out_buffer; 1191 break; 1192 case IO_STATE_VALUE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit): 1193 port->out_count -= 4; 1194 *port->data_out = *(unsigned int *)port->outp; 1195 port->outp += 4; 1196 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) 1197 port->outp = port->out_buffer; 1198 break; 1199 } 1200 } 1201 1202 1203 static void start_dma(struct sync_port *port, const char *data, int count) 1204 { 1205 port->tr_running = 1; 1206 port->out_descr.hw_len = 0; 1207 port->out_descr.next = 0; 1208 port->out_descr.ctrl = d_eol | d_eop; /* No d_wait to avoid glitches */ 1209 port->out_descr.sw_len = count; 1210 port->out_descr.buf = virt_to_phys(data); 1211 port->out_descr.status = 0; 1212 1213 *port->output_dma_first = virt_to_phys(&port->out_descr); 1214 *port->output_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start); 1215 DEBUGTXINT(printk(KERN_DEBUG "dma %08lX c %d\n", 1216 (unsigned long)data, count)); 1217 } 1218 1219 static void start_dma_in(struct sync_port *port) 1220 { 1221 int i; 1222 unsigned long buf; 1223 port->writep = port->flip; 1224 1225 if (port->writep > port->flip + port->in_buffer_size) { 1226 panic("Offset too large in sync serial driver\n"); 1227 return; 1228 } 1229 buf = virt_to_phys(port->in_buffer); 1230 for (i = 0; i < NUM_IN_DESCR; i++) { 1231 port->in_descr[i].sw_len = port->inbufchunk; 1232 port->in_descr[i].ctrl = d_int; 1233 port->in_descr[i].next = virt_to_phys(&port->in_descr[i+1]); 1234 port->in_descr[i].buf = buf; 1235 port->in_descr[i].hw_len = 0; 1236 port->in_descr[i].status = 0; 1237 port->in_descr[i].fifo_len = 0; 1238 buf += port->inbufchunk; 1239 prepare_rx_descriptor(&port->in_descr[i]); 1240 } 1241 /* Link the last descriptor to the first */ 1242 port->in_descr[i-1].next = virt_to_phys(&port->in_descr[0]); 1243 port->in_descr[i-1].ctrl |= d_eol; 1244 port->next_rx_desc = &port->in_descr[0]; 1245 port->prev_rx_desc = &port->in_descr[NUM_IN_DESCR - 1]; 1246 *port->input_dma_first = virt_to_phys(port->next_rx_desc); 1247 *port->input_dma_cmd = IO_STATE(R_DMA_CH0_CMD, cmd, start); 1248 } 1249 1250 #ifdef SYNC_SER_DMA 1251 static irqreturn_t tr_interrupt(int irq, void *dev_id) 1252 { 1253 unsigned long ireg = *R_IRQ_MASK2_RD; 1254 struct etrax_dma_descr *descr; 1255 unsigned int sentl; 1256 int handled = 0; 1257 int i; 1258 1259 for (i = 0; i < NUMBER_OF_PORTS; i++) { 1260 struct sync_port *port = &ports[i]; 1261 if (!port->enabled || !port->use_dma) 1262 continue; 1263 1264 /* IRQ active for the port? */ 1265 if (!(ireg & (1 << port->output_dma_bit))) 1266 continue; 1267 1268 handled = 1; 1269 1270 /* Clear IRQ */ 1271 *port->output_dma_clr_irq = 1272 IO_STATE(R_DMA_CH0_CLR_INTR, clr_eop, do) | 1273 IO_STATE(R_DMA_CH0_CLR_INTR, clr_descr, do); 1274 1275 descr = &port->out_descr; 1276 if (!(descr->status & d_stop)) 1277 sentl = descr->sw_len; 1278 else 1279 /* Otherwise find amount of data sent here */ 1280 sentl = descr->hw_len; 1281 1282 port->out_count -= sentl; 1283 port->outp += sentl; 1284 if (port->outp >= port->out_buffer + OUT_BUFFER_SIZE) 1285 port->outp = port->out_buffer; 1286 if (port->out_count) { 1287 int c = port->out_buffer + OUT_BUFFER_SIZE - port->outp; 1288 if (c > port->out_count) 1289 c = port->out_count; 1290 DEBUGTXINT(printk(KERN_DEBUG 1291 "tx_int DMAWRITE %i %i\n", sentl, c)); 1292 start_dma(port, port->outp, c); 1293 } else { 1294 DEBUGTXINT(printk(KERN_DEBUG 1295 "tx_int DMA stop %i\n", sentl)); 1296 port->tr_running = 0; 1297 } 1298 /* wake up the waiting process */ 1299 wake_up_interruptible(&port->out_wait_q); 1300 } 1301 return IRQ_RETVAL(handled); 1302 } /* tr_interrupt */ 1303 1304 static irqreturn_t rx_interrupt(int irq, void *dev_id) 1305 { 1306 unsigned long ireg = *R_IRQ_MASK2_RD; 1307 int i; 1308 int handled = 0; 1309 1310 for (i = 0; i < NUMBER_OF_PORTS; i++) { 1311 struct sync_port *port = &ports[i]; 1312 1313 if (!port->enabled || !port->use_dma) 1314 continue; 1315 1316 if (!(ireg & (1 << port->input_dma_descr_bit))) 1317 continue; 1318 1319 /* Descriptor interrupt */ 1320 handled = 1; 1321 while (*port->input_dma_descr != 1322 virt_to_phys(port->next_rx_desc)) { 1323 if (port->writep + port->inbufchunk > port->flip + 1324 port->in_buffer_size) { 1325 int first_size = port->flip + 1326 port->in_buffer_size - port->writep; 1327 memcpy(port->writep, 1328 phys_to_virt(port->next_rx_desc->buf), 1329 first_size); 1330 memcpy(port->flip, 1331 phys_to_virt(port->next_rx_desc->buf + 1332 first_size), 1333 port->inbufchunk - first_size); 1334 port->writep = port->flip + 1335 port->inbufchunk - first_size; 1336 } else { 1337 memcpy(port->writep, 1338 phys_to_virt(port->next_rx_desc->buf), 1339 port->inbufchunk); 1340 port->writep += port->inbufchunk; 1341 if (port->writep >= port->flip 1342 + port->in_buffer_size) 1343 port->writep = port->flip; 1344 } 1345 if (port->writep == port->readp) 1346 port->full = 1; 1347 prepare_rx_descriptor(port->next_rx_desc); 1348 port->next_rx_desc->ctrl |= d_eol; 1349 port->prev_rx_desc->ctrl &= ~d_eol; 1350 port->prev_rx_desc = phys_to_virt((unsigned) 1351 port->next_rx_desc); 1352 port->next_rx_desc = phys_to_virt((unsigned) 1353 port->next_rx_desc->next); 1354 /* Wake up the waiting process */ 1355 wake_up_interruptible(&port->in_wait_q); 1356 *port->input_dma_cmd = IO_STATE(R_DMA_CH1_CMD, 1357 cmd, restart); 1358 /* DMA has reached end of descriptor */ 1359 *port->input_dma_clr_irq = IO_STATE(R_DMA_CH0_CLR_INTR, 1360 clr_descr, do); 1361 } 1362 } 1363 return IRQ_RETVAL(handled); 1364 } /* rx_interrupt */ 1365 #endif /* SYNC_SER_DMA */ 1366 1367 #ifdef SYNC_SER_MANUAL 1368 static irqreturn_t manual_interrupt(int irq, void *dev_id) 1369 { 1370 int i; 1371 int handled = 0; 1372 1373 for (i = 0; i < NUMBER_OF_PORTS; i++) { 1374 struct sync_port *port = &ports[i]; 1375 1376 if (!port->enabled || port->use_dma) 1377 continue; 1378 1379 /* Data received? */ 1380 if (*R_IRQ_MASK1_RD & (1 << port->data_avail_bit)) { 1381 handled = 1; 1382 /* Read data */ 1383 switch (port->ctrl_data_shadow & 1384 IO_MASK(R_SYNC_SERIAL1_CTRL, wordsize)) { 1385 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size8bit): 1386 *port->writep++ = 1387 *(volatile char *)port->data_in; 1388 break; 1389 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size12bit): 1390 { 1391 int data = *(unsigned short *)port->data_in; 1392 *port->writep = (data & 0x0ff0) >> 4; 1393 *(port->writep + 1) = data & 0x0f; 1394 port->writep += 2; 1395 break; 1396 } 1397 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size16bit): 1398 *(unsigned short *)port->writep = 1399 *(volatile unsigned short *)port->data_in; 1400 port->writep += 2; 1401 break; 1402 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size24bit): 1403 *(unsigned int *)port->writep = *port->data_in; 1404 port->writep += 3; 1405 break; 1406 case IO_STATE(R_SYNC_SERIAL1_CTRL, wordsize, size32bit): 1407 *(unsigned int *)port->writep = *port->data_in; 1408 port->writep += 4; 1409 break; 1410 } 1411 1412 /* Wrap? */ 1413 if (port->writep >= port->flip + port->in_buffer_size) 1414 port->writep = port->flip; 1415 if (port->writep == port->readp) { 1416 /* Receive buffer overrun, discard oldest */ 1417 port->readp++; 1418 /* Wrap? */ 1419 if (port->readp >= port->flip + 1420 port->in_buffer_size) 1421 port->readp = port->flip; 1422 } 1423 if (sync_data_avail(port) >= port->inbufchunk) { 1424 /* Wake up application */ 1425 wake_up_interruptible(&port->in_wait_q); 1426 } 1427 } 1428 1429 /* Transmitter ready? */ 1430 if (*R_IRQ_MASK1_RD & (1 << port->transmitter_ready_bit)) { 1431 if (port->out_count > 0) { 1432 /* More data to send */ 1433 send_word(port); 1434 } else { 1435 /* Transmission finished */ 1436 /* Turn off IRQ */ 1437 *R_IRQ_MASK1_CLR = 1 << 1438 port->transmitter_ready_bit; 1439 /* Wake up application */ 1440 wake_up_interruptible(&port->out_wait_q); 1441 } 1442 } 1443 } 1444 return IRQ_RETVAL(handled); 1445 } 1446 #endif 1447 1448 module_init(etrax_sync_serial_init); 1449
This page was automatically generated by LXR 0.3.1. • Linux is a registered trademark of Linus Torvalds