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Linux/arch/arm64/Kconfig

  1 config ARM64
  2         def_bool y
  3         select ACPI_CCA_REQUIRED if ACPI
  4         select ACPI_GENERIC_GSI if ACPI
  5         select ACPI_REDUCED_HARDWARE_ONLY if ACPI
  6         select ARCH_HAS_DEVMEM_IS_ALLOWED
  7         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
  8         select ARCH_HAS_ELF_RANDOMIZE
  9         select ARCH_HAS_GCOV_PROFILE_ALL
 10         select ARCH_HAS_SG_CHAIN
 11         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
 12         select ARCH_USE_CMPXCHG_LOCKREF
 13         select ARCH_SUPPORTS_ATOMIC_RMW
 14         select ARCH_WANT_OPTIONAL_GPIOLIB
 15         select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
 16         select ARCH_WANT_FRAME_POINTERS
 17         select ARM_AMBA
 18         select ARM_ARCH_TIMER
 19         select ARM_GIC
 20         select AUDIT_ARCH_COMPAT_GENERIC
 21         select ARM_GIC_V2M if PCI_MSI
 22         select ARM_GIC_V3
 23         select ARM_GIC_V3_ITS if PCI_MSI
 24         select ARM_PSCI_FW
 25         select BUILDTIME_EXTABLE_SORT
 26         select CLONE_BACKWARDS
 27         select COMMON_CLK
 28         select CPU_PM if (SUSPEND || CPU_IDLE)
 29         select DCACHE_WORD_ACCESS
 30         select EDAC_SUPPORT
 31         select FRAME_POINTER
 32         select GENERIC_ALLOCATOR
 33         select GENERIC_CLOCKEVENTS
 34         select GENERIC_CLOCKEVENTS_BROADCAST
 35         select GENERIC_CPU_AUTOPROBE
 36         select GENERIC_EARLY_IOREMAP
 37         select GENERIC_IDLE_POLL_SETUP
 38         select GENERIC_IRQ_PROBE
 39         select GENERIC_IRQ_SHOW
 40         select GENERIC_IRQ_SHOW_LEVEL
 41         select GENERIC_PCI_IOMAP
 42         select GENERIC_SCHED_CLOCK
 43         select GENERIC_SMP_IDLE_THREAD
 44         select GENERIC_STRNCPY_FROM_USER
 45         select GENERIC_STRNLEN_USER
 46         select GENERIC_TIME_VSYSCALL
 47         select HANDLE_DOMAIN_IRQ
 48         select HARDIRQS_SW_RESEND
 49         select HAVE_ALIGNED_STRUCT_PAGE if SLUB
 50         select HAVE_ARCH_AUDITSYSCALL
 51         select HAVE_ARCH_BITREVERSE
 52         select HAVE_ARCH_JUMP_LABEL
 53         select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
 54         select HAVE_ARCH_KGDB
 55         select HAVE_ARCH_MMAP_RND_BITS
 56         select HAVE_ARCH_MMAP_RND_COMPAT_BITS if COMPAT
 57         select HAVE_ARCH_SECCOMP_FILTER
 58         select HAVE_ARCH_TRACEHOOK
 59         select HAVE_BPF_JIT
 60         select HAVE_C_RECORDMCOUNT
 61         select HAVE_CC_STACKPROTECTOR
 62         select HAVE_CMPXCHG_DOUBLE
 63         select HAVE_CMPXCHG_LOCAL
 64         select HAVE_DEBUG_BUGVERBOSE
 65         select HAVE_DEBUG_KMEMLEAK
 66         select HAVE_DMA_API_DEBUG
 67         select HAVE_DMA_CONTIGUOUS
 68         select HAVE_DYNAMIC_FTRACE
 69         select HAVE_EFFICIENT_UNALIGNED_ACCESS
 70         select HAVE_FTRACE_MCOUNT_RECORD
 71         select HAVE_FUNCTION_TRACER
 72         select HAVE_FUNCTION_GRAPH_TRACER
 73         select HAVE_GENERIC_DMA_COHERENT
 74         select HAVE_HW_BREAKPOINT if PERF_EVENTS
 75         select HAVE_IRQ_TIME_ACCOUNTING
 76         select HAVE_MEMBLOCK
 77         select HAVE_PATA_PLATFORM
 78         select HAVE_PERF_EVENTS
 79         select HAVE_PERF_REGS
 80         select HAVE_PERF_USER_STACK_DUMP
 81         select HAVE_RCU_TABLE_FREE
 82         select HAVE_SYSCALL_TRACEPOINTS
 83         select IOMMU_DMA if IOMMU_SUPPORT
 84         select IRQ_DOMAIN
 85         select IRQ_FORCED_THREADING
 86         select MODULES_USE_ELF_RELA
 87         select NO_BOOTMEM
 88         select OF
 89         select OF_EARLY_FLATTREE
 90         select OF_RESERVED_MEM
 91         select PERF_USE_VMALLOC
 92         select POWER_RESET
 93         select POWER_SUPPLY
 94         select RTC_LIB
 95         select SPARSE_IRQ
 96         select SYSCTL_EXCEPTION_TRACE
 97         select HAVE_CONTEXT_TRACKING
 98         select HAVE_ARM_SMCCC
 99         help
100           ARM 64-bit (AArch64) Linux support.
101 
102 config 64BIT
103         def_bool y
104 
105 config ARCH_PHYS_ADDR_T_64BIT
106         def_bool y
107 
108 config MMU
109         def_bool y
110 
111 config ARCH_MMAP_RND_BITS_MIN
112        default 14 if ARM64_64K_PAGES
113        default 16 if ARM64_16K_PAGES
114        default 18
115 
116 # max bits determined by the following formula:
117 #  VA_BITS - PAGE_SHIFT - 3
118 config ARCH_MMAP_RND_BITS_MAX
119        default 19 if ARM64_VA_BITS=36
120        default 24 if ARM64_VA_BITS=39
121        default 27 if ARM64_VA_BITS=42
122        default 30 if ARM64_VA_BITS=47
123        default 29 if ARM64_VA_BITS=48 && ARM64_64K_PAGES
124        default 31 if ARM64_VA_BITS=48 && ARM64_16K_PAGES
125        default 33 if ARM64_VA_BITS=48
126        default 14 if ARM64_64K_PAGES
127        default 16 if ARM64_16K_PAGES
128        default 18
129 
130 config ARCH_MMAP_RND_COMPAT_BITS_MIN
131        default 7 if ARM64_64K_PAGES
132        default 9 if ARM64_16K_PAGES
133        default 11
134 
135 config ARCH_MMAP_RND_COMPAT_BITS_MAX
136        default 16
137 
138 config NO_IOPORT_MAP
139         def_bool y if !PCI
140 
141 config STACKTRACE_SUPPORT
142         def_bool y
143 
144 config ILLEGAL_POINTER_VALUE
145         hex
146         default 0xdead000000000000
147 
148 config LOCKDEP_SUPPORT
149         def_bool y
150 
151 config TRACE_IRQFLAGS_SUPPORT
152         def_bool y
153 
154 config RWSEM_XCHGADD_ALGORITHM
155         def_bool y
156 
157 config GENERIC_BUG
158         def_bool y
159         depends on BUG
160 
161 config GENERIC_BUG_RELATIVE_POINTERS
162         def_bool y
163         depends on GENERIC_BUG
164 
165 config GENERIC_HWEIGHT
166         def_bool y
167 
168 config GENERIC_CSUM
169         def_bool y
170 
171 config GENERIC_CALIBRATE_DELAY
172         def_bool y
173 
174 config ZONE_DMA
175         def_bool y
176 
177 config HAVE_GENERIC_RCU_GUP
178         def_bool y
179 
180 config ARCH_DMA_ADDR_T_64BIT
181         def_bool y
182 
183 config NEED_DMA_MAP_STATE
184         def_bool y
185 
186 config NEED_SG_DMA_LENGTH
187         def_bool y
188 
189 config SMP
190         def_bool y
191 
192 config SWIOTLB
193         def_bool y
194 
195 config IOMMU_HELPER
196         def_bool SWIOTLB
197 
198 config KERNEL_MODE_NEON
199         def_bool y
200 
201 config FIX_EARLYCON_MEM
202         def_bool y
203 
204 config PGTABLE_LEVELS
205         int
206         default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
207         default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
208         default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
209         default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
210         default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
211         default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
212 
213 source "init/Kconfig"
214 
215 source "kernel/Kconfig.freezer"
216 
217 source "arch/arm64/Kconfig.platforms"
218 
219 menu "Bus support"
220 
221 config PCI
222         bool "PCI support"
223         help
224           This feature enables support for PCI bus system. If you say Y
225           here, the kernel will include drivers and infrastructure code
226           to support PCI bus devices.
227 
228 config PCI_DOMAINS
229         def_bool PCI
230 
231 config PCI_DOMAINS_GENERIC
232         def_bool PCI
233 
234 config PCI_SYSCALL
235         def_bool PCI
236 
237 source "drivers/pci/Kconfig"
238 source "drivers/pci/pcie/Kconfig"
239 source "drivers/pci/hotplug/Kconfig"
240 
241 endmenu
242 
243 menu "Kernel Features"
244 
245 menu "ARM errata workarounds via the alternatives framework"
246 
247 config ARM64_ERRATUM_826319
248         bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
249         default y
250         help
251           This option adds an alternative code sequence to work around ARM
252           erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
253           AXI master interface and an L2 cache.
254 
255           If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
256           and is unable to accept a certain write via this interface, it will
257           not progress on read data presented on the read data channel and the
258           system can deadlock.
259 
260           The workaround promotes data cache clean instructions to
261           data cache clean-and-invalidate.
262           Please note that this does not necessarily enable the workaround,
263           as it depends on the alternative framework, which will only patch
264           the kernel if an affected CPU is detected.
265 
266           If unsure, say Y.
267 
268 config ARM64_ERRATUM_827319
269         bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
270         default y
271         help
272           This option adds an alternative code sequence to work around ARM
273           erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
274           master interface and an L2 cache.
275 
276           Under certain conditions this erratum can cause a clean line eviction
277           to occur at the same time as another transaction to the same address
278           on the AMBA 5 CHI interface, which can cause data corruption if the
279           interconnect reorders the two transactions.
280 
281           The workaround promotes data cache clean instructions to
282           data cache clean-and-invalidate.
283           Please note that this does not necessarily enable the workaround,
284           as it depends on the alternative framework, which will only patch
285           the kernel if an affected CPU is detected.
286 
287           If unsure, say Y.
288 
289 config ARM64_ERRATUM_824069
290         bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
291         default y
292         help
293           This option adds an alternative code sequence to work around ARM
294           erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
295           to a coherent interconnect.
296 
297           If a Cortex-A53 processor is executing a store or prefetch for
298           write instruction at the same time as a processor in another
299           cluster is executing a cache maintenance operation to the same
300           address, then this erratum might cause a clean cache line to be
301           incorrectly marked as dirty.
302 
303           The workaround promotes data cache clean instructions to
304           data cache clean-and-invalidate.
305           Please note that this option does not necessarily enable the
306           workaround, as it depends on the alternative framework, which will
307           only patch the kernel if an affected CPU is detected.
308 
309           If unsure, say Y.
310 
311 config ARM64_ERRATUM_819472
312         bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
313         default y
314         help
315           This option adds an alternative code sequence to work around ARM
316           erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
317           present when it is connected to a coherent interconnect.
318 
319           If the processor is executing a load and store exclusive sequence at
320           the same time as a processor in another cluster is executing a cache
321           maintenance operation to the same address, then this erratum might
322           cause data corruption.
323 
324           The workaround promotes data cache clean instructions to
325           data cache clean-and-invalidate.
326           Please note that this does not necessarily enable the workaround,
327           as it depends on the alternative framework, which will only patch
328           the kernel if an affected CPU is detected.
329 
330           If unsure, say Y.
331 
332 config ARM64_ERRATUM_832075
333         bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
334         default y
335         help
336           This option adds an alternative code sequence to work around ARM
337           erratum 832075 on Cortex-A57 parts up to r1p2.
338 
339           Affected Cortex-A57 parts might deadlock when exclusive load/store
340           instructions to Write-Back memory are mixed with Device loads.
341 
342           The workaround is to promote device loads to use Load-Acquire
343           semantics.
344           Please note that this does not necessarily enable the workaround,
345           as it depends on the alternative framework, which will only patch
346           the kernel if an affected CPU is detected.
347 
348           If unsure, say Y.
349 
350 config ARM64_ERRATUM_834220
351         bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
352         depends on KVM
353         default y
354         help
355           This option adds an alternative code sequence to work around ARM
356           erratum 834220 on Cortex-A57 parts up to r1p2.
357 
358           Affected Cortex-A57 parts might report a Stage 2 translation
359           fault as the result of a Stage 1 fault for load crossing a
360           page boundary when there is a permission or device memory
361           alignment fault at Stage 1 and a translation fault at Stage 2.
362 
363           The workaround is to verify that the Stage 1 translation
364           doesn't generate a fault before handling the Stage 2 fault.
365           Please note that this does not necessarily enable the workaround,
366           as it depends on the alternative framework, which will only patch
367           the kernel if an affected CPU is detected.
368 
369           If unsure, say Y.
370 
371 config ARM64_ERRATUM_845719
372         bool "Cortex-A53: 845719: a load might read incorrect data"
373         depends on COMPAT
374         default y
375         help
376           This option adds an alternative code sequence to work around ARM
377           erratum 845719 on Cortex-A53 parts up to r0p4.
378 
379           When running a compat (AArch32) userspace on an affected Cortex-A53
380           part, a load at EL0 from a virtual address that matches the bottom 32
381           bits of the virtual address used by a recent load at (AArch64) EL1
382           might return incorrect data.
383 
384           The workaround is to write the contextidr_el1 register on exception
385           return to a 32-bit task.
386           Please note that this does not necessarily enable the workaround,
387           as it depends on the alternative framework, which will only patch
388           the kernel if an affected CPU is detected.
389 
390           If unsure, say Y.
391 
392 config ARM64_ERRATUM_843419
393         bool "Cortex-A53: 843419: A load or store might access an incorrect address"
394         depends on MODULES
395         default y
396         help
397           This option builds kernel modules using the large memory model in
398           order to avoid the use of the ADRP instruction, which can cause
399           a subsequent memory access to use an incorrect address on Cortex-A53
400           parts up to r0p4.
401 
402           Note that the kernel itself must be linked with a version of ld
403           which fixes potentially affected ADRP instructions through the
404           use of veneers.
405 
406           If unsure, say Y.
407 
408 config CAVIUM_ERRATUM_22375
409         bool "Cavium erratum 22375, 24313"
410         default y
411         help
412           Enable workaround for erratum 22375, 24313.
413 
414           This implements two gicv3-its errata workarounds for ThunderX. Both
415           with small impact affecting only ITS table allocation.
416 
417             erratum 22375: only alloc 8MB table size
418             erratum 24313: ignore memory access type
419 
420           The fixes are in ITS initialization and basically ignore memory access
421           type and table size provided by the TYPER and BASER registers.
422 
423           If unsure, say Y.
424 
425 config CAVIUM_ERRATUM_23154
426         bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
427         default y
428         help
429           The gicv3 of ThunderX requires a modified version for
430           reading the IAR status to ensure data synchronization
431           (access to icc_iar1_el1 is not sync'ed before and after).
432 
433           If unsure, say Y.
434 
435 endmenu
436 
437 
438 choice
439         prompt "Page size"
440         default ARM64_4K_PAGES
441         help
442           Page size (translation granule) configuration.
443 
444 config ARM64_4K_PAGES
445         bool "4KB"
446         help
447           This feature enables 4KB pages support.
448 
449 config ARM64_16K_PAGES
450         bool "16KB"
451         help
452           The system will use 16KB pages support. AArch32 emulation
453           requires applications compiled with 16K (or a multiple of 16K)
454           aligned segments.
455 
456 config ARM64_64K_PAGES
457         bool "64KB"
458         help
459           This feature enables 64KB pages support (4KB by default)
460           allowing only two levels of page tables and faster TLB
461           look-up. AArch32 emulation requires applications compiled
462           with 64K aligned segments.
463 
464 endchoice
465 
466 choice
467         prompt "Virtual address space size"
468         default ARM64_VA_BITS_39 if ARM64_4K_PAGES
469         default ARM64_VA_BITS_47 if ARM64_16K_PAGES
470         default ARM64_VA_BITS_42 if ARM64_64K_PAGES
471         help
472           Allows choosing one of multiple possible virtual address
473           space sizes. The level of translation table is determined by
474           a combination of page size and virtual address space size.
475 
476 config ARM64_VA_BITS_36
477         bool "36-bit" if EXPERT
478         depends on ARM64_16K_PAGES
479 
480 config ARM64_VA_BITS_39
481         bool "39-bit"
482         depends on ARM64_4K_PAGES
483 
484 config ARM64_VA_BITS_42
485         bool "42-bit"
486         depends on ARM64_64K_PAGES
487 
488 config ARM64_VA_BITS_47
489         bool "47-bit"
490         depends on ARM64_16K_PAGES
491 
492 config ARM64_VA_BITS_48
493         bool "48-bit"
494 
495 endchoice
496 
497 config ARM64_VA_BITS
498         int
499         default 36 if ARM64_VA_BITS_36
500         default 39 if ARM64_VA_BITS_39
501         default 42 if ARM64_VA_BITS_42
502         default 47 if ARM64_VA_BITS_47
503         default 48 if ARM64_VA_BITS_48
504 
505 config CPU_BIG_ENDIAN
506        bool "Build big-endian kernel"
507        help
508          Say Y if you plan on running a kernel in big-endian mode.
509 
510 config SCHED_MC
511         bool "Multi-core scheduler support"
512         help
513           Multi-core scheduler support improves the CPU scheduler's decision
514           making when dealing with multi-core CPU chips at a cost of slightly
515           increased overhead in some places. If unsure say N here.
516 
517 config SCHED_SMT
518         bool "SMT scheduler support"
519         help
520           Improves the CPU scheduler's decision making when dealing with
521           MultiThreading at a cost of slightly increased overhead in some
522           places. If unsure say N here.
523 
524 config NR_CPUS
525         int "Maximum number of CPUs (2-4096)"
526         range 2 4096
527         # These have to remain sorted largest to smallest
528         default "64"
529 
530 config HOTPLUG_CPU
531         bool "Support for hot-pluggable CPUs"
532         select GENERIC_IRQ_MIGRATION
533         help
534           Say Y here to experiment with turning CPUs off and on.  CPUs
535           can be controlled through /sys/devices/system/cpu.
536 
537 source kernel/Kconfig.preempt
538 source kernel/Kconfig.hz
539 
540 config ARCH_HAS_HOLES_MEMORYMODEL
541         def_bool y if SPARSEMEM
542 
543 config ARCH_SPARSEMEM_ENABLE
544         def_bool y
545         select SPARSEMEM_VMEMMAP_ENABLE
546 
547 config ARCH_SPARSEMEM_DEFAULT
548         def_bool ARCH_SPARSEMEM_ENABLE
549 
550 config ARCH_SELECT_MEMORY_MODEL
551         def_bool ARCH_SPARSEMEM_ENABLE
552 
553 config HAVE_ARCH_PFN_VALID
554         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
555 
556 config HW_PERF_EVENTS
557         def_bool y
558         depends on ARM_PMU
559 
560 config SYS_SUPPORTS_HUGETLBFS
561         def_bool y
562 
563 config ARCH_WANT_HUGE_PMD_SHARE
564         def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
565 
566 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
567         def_bool y
568 
569 config ARCH_HAS_CACHE_LINE_SIZE
570         def_bool y
571 
572 source "mm/Kconfig"
573 
574 config SECCOMP
575         bool "Enable seccomp to safely compute untrusted bytecode"
576         ---help---
577           This kernel feature is useful for number crunching applications
578           that may need to compute untrusted bytecode during their
579           execution. By using pipes or other transports made available to
580           the process as file descriptors supporting the read/write
581           syscalls, it's possible to isolate those applications in
582           their own address space using seccomp. Once seccomp is
583           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
584           and the task is only allowed to execute a few safe syscalls
585           defined by each seccomp mode.
586 
587 config PARAVIRT
588         bool "Enable paravirtualization code"
589         help
590           This changes the kernel so it can modify itself when it is run
591           under a hypervisor, potentially improving performance significantly
592           over full virtualization.
593 
594 config PARAVIRT_TIME_ACCOUNTING
595         bool "Paravirtual steal time accounting"
596         select PARAVIRT
597         default n
598         help
599           Select this option to enable fine granularity task steal time
600           accounting. Time spent executing other tasks in parallel with
601           the current vCPU is discounted from the vCPU power. To account for
602           that, there can be a small performance impact.
603 
604           If in doubt, say N here.
605 
606 config XEN_DOM0
607         def_bool y
608         depends on XEN
609 
610 config XEN
611         bool "Xen guest support on ARM64"
612         depends on ARM64 && OF
613         select SWIOTLB_XEN
614         select PARAVIRT
615         help
616           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
617 
618 config FORCE_MAX_ZONEORDER
619         int
620         default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
621         default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
622         default "11"
623         help
624           The kernel memory allocator divides physically contiguous memory
625           blocks into "zones", where each zone is a power of two number of
626           pages.  This option selects the largest power of two that the kernel
627           keeps in the memory allocator.  If you need to allocate very large
628           blocks of physically contiguous memory, then you may need to
629           increase this value.
630 
631           This config option is actually maximum order plus one. For example,
632           a value of 11 means that the largest free memory block is 2^10 pages.
633 
634           We make sure that we can allocate upto a HugePage size for each configuration.
635           Hence we have :
636                 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
637 
638           However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
639           4M allocations matching the default size used by generic code.
640 
641 menuconfig ARMV8_DEPRECATED
642         bool "Emulate deprecated/obsolete ARMv8 instructions"
643         depends on COMPAT
644         help
645           Legacy software support may require certain instructions
646           that have been deprecated or obsoleted in the architecture.
647 
648           Enable this config to enable selective emulation of these
649           features.
650 
651           If unsure, say Y
652 
653 if ARMV8_DEPRECATED
654 
655 config SWP_EMULATION
656         bool "Emulate SWP/SWPB instructions"
657         help
658           ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
659           they are always undefined. Say Y here to enable software
660           emulation of these instructions for userspace using LDXR/STXR.
661 
662           In some older versions of glibc [<=2.8] SWP is used during futex
663           trylock() operations with the assumption that the code will not
664           be preempted. This invalid assumption may be more likely to fail
665           with SWP emulation enabled, leading to deadlock of the user
666           application.
667 
668           NOTE: when accessing uncached shared regions, LDXR/STXR rely
669           on an external transaction monitoring block called a global
670           monitor to maintain update atomicity. If your system does not
671           implement a global monitor, this option can cause programs that
672           perform SWP operations to uncached memory to deadlock.
673 
674           If unsure, say Y
675 
676 config CP15_BARRIER_EMULATION
677         bool "Emulate CP15 Barrier instructions"
678         help
679           The CP15 barrier instructions - CP15ISB, CP15DSB, and
680           CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
681           strongly recommended to use the ISB, DSB, and DMB
682           instructions instead.
683 
684           Say Y here to enable software emulation of these
685           instructions for AArch32 userspace code. When this option is
686           enabled, CP15 barrier usage is traced which can help
687           identify software that needs updating.
688 
689           If unsure, say Y
690 
691 config SETEND_EMULATION
692         bool "Emulate SETEND instruction"
693         help
694           The SETEND instruction alters the data-endianness of the
695           AArch32 EL0, and is deprecated in ARMv8.
696 
697           Say Y here to enable software emulation of the instruction
698           for AArch32 userspace code.
699 
700           Note: All the cpus on the system must have mixed endian support at EL0
701           for this feature to be enabled. If a new CPU - which doesn't support mixed
702           endian - is hotplugged in after this feature has been enabled, there could
703           be unexpected results in the applications.
704 
705           If unsure, say Y
706 endif
707 
708 menu "ARMv8.1 architectural features"
709 
710 config ARM64_HW_AFDBM
711         bool "Support for hardware updates of the Access and Dirty page flags"
712         default y
713         help
714           The ARMv8.1 architecture extensions introduce support for
715           hardware updates of the access and dirty information in page
716           table entries. When enabled in TCR_EL1 (HA and HD bits) on
717           capable processors, accesses to pages with PTE_AF cleared will
718           set this bit instead of raising an access flag fault.
719           Similarly, writes to read-only pages with the DBM bit set will
720           clear the read-only bit (AP[2]) instead of raising a
721           permission fault.
722 
723           Kernels built with this configuration option enabled continue
724           to work on pre-ARMv8.1 hardware and the performance impact is
725           minimal. If unsure, say Y.
726 
727 config ARM64_PAN
728         bool "Enable support for Privileged Access Never (PAN)"
729         default y
730         help
731          Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
732          prevents the kernel or hypervisor from accessing user-space (EL0)
733          memory directly.
734 
735          Choosing this option will cause any unprotected (not using
736          copy_to_user et al) memory access to fail with a permission fault.
737 
738          The feature is detected at runtime, and will remain as a 'nop'
739          instruction if the cpu does not implement the feature.
740 
741 config ARM64_LSE_ATOMICS
742         bool "Atomic instructions"
743         help
744           As part of the Large System Extensions, ARMv8.1 introduces new
745           atomic instructions that are designed specifically to scale in
746           very large systems.
747 
748           Say Y here to make use of these instructions for the in-kernel
749           atomic routines. This incurs a small overhead on CPUs that do
750           not support these instructions and requires the kernel to be
751           built with binutils >= 2.25.
752 
753 endmenu
754 
755 endmenu
756 
757 menu "Boot options"
758 
759 config CMDLINE
760         string "Default kernel command string"
761         default ""
762         help
763           Provide a set of default command-line options at build time by
764           entering them here. As a minimum, you should specify the the
765           root device (e.g. root=/dev/nfs).
766 
767 config CMDLINE_FORCE
768         bool "Always use the default kernel command string"
769         help
770           Always use the default kernel command string, even if the boot
771           loader passes other arguments to the kernel.
772           This is useful if you cannot or don't want to change the
773           command-line options your boot loader passes to the kernel.
774 
775 config EFI_STUB
776         bool
777 
778 config EFI
779         bool "UEFI runtime support"
780         depends on OF && !CPU_BIG_ENDIAN
781         select LIBFDT
782         select UCS2_STRING
783         select EFI_PARAMS_FROM_FDT
784         select EFI_RUNTIME_WRAPPERS
785         select EFI_STUB
786         select EFI_ARMSTUB
787         default y
788         help
789           This option provides support for runtime services provided
790           by UEFI firmware (such as non-volatile variables, realtime
791           clock, and platform reset). A UEFI stub is also provided to
792           allow the kernel to be booted as an EFI application. This
793           is only useful on systems that have UEFI firmware.
794 
795 config DMI
796         bool "Enable support for SMBIOS (DMI) tables"
797         depends on EFI
798         default y
799         help
800           This enables SMBIOS/DMI feature for systems.
801 
802           This option is only useful on systems that have UEFI firmware.
803           However, even with this option, the resultant kernel should
804           continue to boot on existing non-UEFI platforms.
805 
806 endmenu
807 
808 menu "Userspace binary formats"
809 
810 source "fs/Kconfig.binfmt"
811 
812 config COMPAT
813         bool "Kernel support for 32-bit EL0"
814         depends on ARM64_4K_PAGES || EXPERT
815         select COMPAT_BINFMT_ELF
816         select HAVE_UID16
817         select OLD_SIGSUSPEND3
818         select COMPAT_OLD_SIGACTION
819         help
820           This option enables support for a 32-bit EL0 running under a 64-bit
821           kernel at EL1. AArch32-specific components such as system calls,
822           the user helper functions, VFP support and the ptrace interface are
823           handled appropriately by the kernel.
824 
825           If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
826           that you will only be able to execute AArch32 binaries that were compiled
827           with page size aligned segments.
828 
829           If you want to execute 32-bit userspace applications, say Y.
830 
831 config SYSVIPC_COMPAT
832         def_bool y
833         depends on COMPAT && SYSVIPC
834 
835 endmenu
836 
837 menu "Power management options"
838 
839 source "kernel/power/Kconfig"
840 
841 config ARCH_SUSPEND_POSSIBLE
842         def_bool y
843 
844 endmenu
845 
846 menu "CPU Power Management"
847 
848 source "drivers/cpuidle/Kconfig"
849 
850 source "drivers/cpufreq/Kconfig"
851 
852 endmenu
853 
854 source "net/Kconfig"
855 
856 source "drivers/Kconfig"
857 
858 source "drivers/firmware/Kconfig"
859 
860 source "drivers/acpi/Kconfig"
861 
862 source "fs/Kconfig"
863 
864 source "arch/arm64/kvm/Kconfig"
865 
866 source "arch/arm64/Kconfig.debug"
867 
868 source "security/Kconfig"
869 
870 source "crypto/Kconfig"
871 if CRYPTO
872 source "arch/arm64/crypto/Kconfig"
873 endif
874 
875 source "lib/Kconfig"

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