Version:  2.0.40 2.2.26 2.4.37 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4

Linux/arch/arm64/Kconfig

  1 config ARM64
  2         def_bool y
  3         select ACPI_CCA_REQUIRED if ACPI
  4         select ACPI_GENERIC_GSI if ACPI
  5         select ACPI_REDUCED_HARDWARE_ONLY if ACPI
  6         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
  7         select ARCH_HAS_ELF_RANDOMIZE
  8         select ARCH_HAS_GCOV_PROFILE_ALL
  9         select ARCH_HAS_SG_CHAIN
 10         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
 11         select ARCH_USE_CMPXCHG_LOCKREF
 12         select ARCH_SUPPORTS_ATOMIC_RMW
 13         select ARCH_WANT_OPTIONAL_GPIOLIB
 14         select ARCH_WANT_COMPAT_IPC_PARSE_VERSION
 15         select ARCH_WANT_FRAME_POINTERS
 16         select ARM_AMBA
 17         select ARM_ARCH_TIMER
 18         select ARM_GIC
 19         select AUDIT_ARCH_COMPAT_GENERIC
 20         select ARM_GIC_V2M if PCI_MSI
 21         select ARM_GIC_V3
 22         select ARM_GIC_V3_ITS if PCI_MSI
 23         select ARM_PSCI_FW
 24         select BUILDTIME_EXTABLE_SORT
 25         select CLONE_BACKWARDS
 26         select COMMON_CLK
 27         select CPU_PM if (SUSPEND || CPU_IDLE)
 28         select DCACHE_WORD_ACCESS
 29         select EDAC_SUPPORT
 30         select FRAME_POINTER
 31         select GENERIC_ALLOCATOR
 32         select GENERIC_CLOCKEVENTS
 33         select GENERIC_CLOCKEVENTS_BROADCAST
 34         select GENERIC_CPU_AUTOPROBE
 35         select GENERIC_EARLY_IOREMAP
 36         select GENERIC_IDLE_POLL_SETUP
 37         select GENERIC_IRQ_PROBE
 38         select GENERIC_IRQ_SHOW
 39         select GENERIC_IRQ_SHOW_LEVEL
 40         select GENERIC_PCI_IOMAP
 41         select GENERIC_SCHED_CLOCK
 42         select GENERIC_SMP_IDLE_THREAD
 43         select GENERIC_STRNCPY_FROM_USER
 44         select GENERIC_STRNLEN_USER
 45         select GENERIC_TIME_VSYSCALL
 46         select HANDLE_DOMAIN_IRQ
 47         select HARDIRQS_SW_RESEND
 48         select HAVE_ALIGNED_STRUCT_PAGE if SLUB
 49         select HAVE_ARCH_AUDITSYSCALL
 50         select HAVE_ARCH_BITREVERSE
 51         select HAVE_ARCH_JUMP_LABEL
 52         select HAVE_ARCH_KASAN if SPARSEMEM_VMEMMAP && !(ARM64_16K_PAGES && ARM64_VA_BITS_48)
 53         select HAVE_ARCH_KGDB
 54         select HAVE_ARCH_SECCOMP_FILTER
 55         select HAVE_ARCH_TRACEHOOK
 56         select HAVE_BPF_JIT
 57         select HAVE_C_RECORDMCOUNT
 58         select HAVE_CC_STACKPROTECTOR
 59         select HAVE_CMPXCHG_DOUBLE
 60         select HAVE_CMPXCHG_LOCAL
 61         select HAVE_DEBUG_BUGVERBOSE
 62         select HAVE_DEBUG_KMEMLEAK
 63         select HAVE_DMA_API_DEBUG
 64         select HAVE_DMA_ATTRS
 65         select HAVE_DMA_CONTIGUOUS
 66         select HAVE_DYNAMIC_FTRACE
 67         select HAVE_EFFICIENT_UNALIGNED_ACCESS
 68         select HAVE_FTRACE_MCOUNT_RECORD
 69         select HAVE_FUNCTION_TRACER
 70         select HAVE_FUNCTION_GRAPH_TRACER
 71         select HAVE_GENERIC_DMA_COHERENT
 72         select HAVE_HW_BREAKPOINT if PERF_EVENTS
 73         select HAVE_MEMBLOCK
 74         select HAVE_PATA_PLATFORM
 75         select HAVE_PERF_EVENTS
 76         select HAVE_PERF_REGS
 77         select HAVE_PERF_USER_STACK_DUMP
 78         select HAVE_RCU_TABLE_FREE
 79         select HAVE_SYSCALL_TRACEPOINTS
 80         select IOMMU_DMA if IOMMU_SUPPORT
 81         select IRQ_DOMAIN
 82         select IRQ_FORCED_THREADING
 83         select MODULES_USE_ELF_RELA
 84         select NO_BOOTMEM
 85         select OF
 86         select OF_EARLY_FLATTREE
 87         select OF_RESERVED_MEM
 88         select PERF_USE_VMALLOC
 89         select POWER_RESET
 90         select POWER_SUPPLY
 91         select RTC_LIB
 92         select SPARSE_IRQ
 93         select SYSCTL_EXCEPTION_TRACE
 94         select HAVE_CONTEXT_TRACKING
 95         help
 96           ARM 64-bit (AArch64) Linux support.
 97 
 98 config 64BIT
 99         def_bool y
100 
101 config ARCH_PHYS_ADDR_T_64BIT
102         def_bool y
103 
104 config MMU
105         def_bool y
106 
107 config NO_IOPORT_MAP
108         def_bool y if !PCI
109 
110 config STACKTRACE_SUPPORT
111         def_bool y
112 
113 config ILLEGAL_POINTER_VALUE
114         hex
115         default 0xdead000000000000
116 
117 config LOCKDEP_SUPPORT
118         def_bool y
119 
120 config TRACE_IRQFLAGS_SUPPORT
121         def_bool y
122 
123 config RWSEM_XCHGADD_ALGORITHM
124         def_bool y
125 
126 config GENERIC_BUG
127         def_bool y
128         depends on BUG
129 
130 config GENERIC_BUG_RELATIVE_POINTERS
131         def_bool y
132         depends on GENERIC_BUG
133 
134 config GENERIC_HWEIGHT
135         def_bool y
136 
137 config GENERIC_CSUM
138         def_bool y
139 
140 config GENERIC_CALIBRATE_DELAY
141         def_bool y
142 
143 config ZONE_DMA
144         def_bool y
145 
146 config HAVE_GENERIC_RCU_GUP
147         def_bool y
148 
149 config ARCH_DMA_ADDR_T_64BIT
150         def_bool y
151 
152 config NEED_DMA_MAP_STATE
153         def_bool y
154 
155 config NEED_SG_DMA_LENGTH
156         def_bool y
157 
158 config SMP
159         def_bool y
160 
161 config SWIOTLB
162         def_bool y
163 
164 config IOMMU_HELPER
165         def_bool SWIOTLB
166 
167 config KERNEL_MODE_NEON
168         def_bool y
169 
170 config FIX_EARLYCON_MEM
171         def_bool y
172 
173 config PGTABLE_LEVELS
174         int
175         default 2 if ARM64_16K_PAGES && ARM64_VA_BITS_36
176         default 2 if ARM64_64K_PAGES && ARM64_VA_BITS_42
177         default 3 if ARM64_64K_PAGES && ARM64_VA_BITS_48
178         default 3 if ARM64_4K_PAGES && ARM64_VA_BITS_39
179         default 3 if ARM64_16K_PAGES && ARM64_VA_BITS_47
180         default 4 if !ARM64_64K_PAGES && ARM64_VA_BITS_48
181 
182 source "init/Kconfig"
183 
184 source "kernel/Kconfig.freezer"
185 
186 source "arch/arm64/Kconfig.platforms"
187 
188 menu "Bus support"
189 
190 config PCI
191         bool "PCI support"
192         help
193           This feature enables support for PCI bus system. If you say Y
194           here, the kernel will include drivers and infrastructure code
195           to support PCI bus devices.
196 
197 config PCI_DOMAINS
198         def_bool PCI
199 
200 config PCI_DOMAINS_GENERIC
201         def_bool PCI
202 
203 config PCI_SYSCALL
204         def_bool PCI
205 
206 source "drivers/pci/Kconfig"
207 source "drivers/pci/pcie/Kconfig"
208 source "drivers/pci/hotplug/Kconfig"
209 
210 endmenu
211 
212 menu "Kernel Features"
213 
214 menu "ARM errata workarounds via the alternatives framework"
215 
216 config ARM64_ERRATUM_826319
217         bool "Cortex-A53: 826319: System might deadlock if a write cannot complete until read data is accepted"
218         default y
219         help
220           This option adds an alternative code sequence to work around ARM
221           erratum 826319 on Cortex-A53 parts up to r0p2 with an AMBA 4 ACE or
222           AXI master interface and an L2 cache.
223 
224           If a Cortex-A53 uses an AMBA AXI4 ACE interface to other processors
225           and is unable to accept a certain write via this interface, it will
226           not progress on read data presented on the read data channel and the
227           system can deadlock.
228 
229           The workaround promotes data cache clean instructions to
230           data cache clean-and-invalidate.
231           Please note that this does not necessarily enable the workaround,
232           as it depends on the alternative framework, which will only patch
233           the kernel if an affected CPU is detected.
234 
235           If unsure, say Y.
236 
237 config ARM64_ERRATUM_827319
238         bool "Cortex-A53: 827319: Data cache clean instructions might cause overlapping transactions to the interconnect"
239         default y
240         help
241           This option adds an alternative code sequence to work around ARM
242           erratum 827319 on Cortex-A53 parts up to r0p2 with an AMBA 5 CHI
243           master interface and an L2 cache.
244 
245           Under certain conditions this erratum can cause a clean line eviction
246           to occur at the same time as another transaction to the same address
247           on the AMBA 5 CHI interface, which can cause data corruption if the
248           interconnect reorders the two transactions.
249 
250           The workaround promotes data cache clean instructions to
251           data cache clean-and-invalidate.
252           Please note that this does not necessarily enable the workaround,
253           as it depends on the alternative framework, which will only patch
254           the kernel if an affected CPU is detected.
255 
256           If unsure, say Y.
257 
258 config ARM64_ERRATUM_824069
259         bool "Cortex-A53: 824069: Cache line might not be marked as clean after a CleanShared snoop"
260         default y
261         help
262           This option adds an alternative code sequence to work around ARM
263           erratum 824069 on Cortex-A53 parts up to r0p2 when it is connected
264           to a coherent interconnect.
265 
266           If a Cortex-A53 processor is executing a store or prefetch for
267           write instruction at the same time as a processor in another
268           cluster is executing a cache maintenance operation to the same
269           address, then this erratum might cause a clean cache line to be
270           incorrectly marked as dirty.
271 
272           The workaround promotes data cache clean instructions to
273           data cache clean-and-invalidate.
274           Please note that this option does not necessarily enable the
275           workaround, as it depends on the alternative framework, which will
276           only patch the kernel if an affected CPU is detected.
277 
278           If unsure, say Y.
279 
280 config ARM64_ERRATUM_819472
281         bool "Cortex-A53: 819472: Store exclusive instructions might cause data corruption"
282         default y
283         help
284           This option adds an alternative code sequence to work around ARM
285           erratum 819472 on Cortex-A53 parts up to r0p1 with an L2 cache
286           present when it is connected to a coherent interconnect.
287 
288           If the processor is executing a load and store exclusive sequence at
289           the same time as a processor in another cluster is executing a cache
290           maintenance operation to the same address, then this erratum might
291           cause data corruption.
292 
293           The workaround promotes data cache clean instructions to
294           data cache clean-and-invalidate.
295           Please note that this does not necessarily enable the workaround,
296           as it depends on the alternative framework, which will only patch
297           the kernel if an affected CPU is detected.
298 
299           If unsure, say Y.
300 
301 config ARM64_ERRATUM_832075
302         bool "Cortex-A57: 832075: possible deadlock on mixing exclusive memory accesses with device loads"
303         default y
304         help
305           This option adds an alternative code sequence to work around ARM
306           erratum 832075 on Cortex-A57 parts up to r1p2.
307 
308           Affected Cortex-A57 parts might deadlock when exclusive load/store
309           instructions to Write-Back memory are mixed with Device loads.
310 
311           The workaround is to promote device loads to use Load-Acquire
312           semantics.
313           Please note that this does not necessarily enable the workaround,
314           as it depends on the alternative framework, which will only patch
315           the kernel if an affected CPU is detected.
316 
317           If unsure, say Y.
318 
319 config ARM64_ERRATUM_834220
320         bool "Cortex-A57: 834220: Stage 2 translation fault might be incorrectly reported in presence of a Stage 1 fault"
321         depends on KVM
322         default y
323         help
324           This option adds an alternative code sequence to work around ARM
325           erratum 834220 on Cortex-A57 parts up to r1p2.
326 
327           Affected Cortex-A57 parts might report a Stage 2 translation
328           fault as the result of a Stage 1 fault for load crossing a
329           page boundary when there is a permission or device memory
330           alignment fault at Stage 1 and a translation fault at Stage 2.
331 
332           The workaround is to verify that the Stage 1 translation
333           doesn't generate a fault before handling the Stage 2 fault.
334           Please note that this does not necessarily enable the workaround,
335           as it depends on the alternative framework, which will only patch
336           the kernel if an affected CPU is detected.
337 
338           If unsure, say Y.
339 
340 config ARM64_ERRATUM_845719
341         bool "Cortex-A53: 845719: a load might read incorrect data"
342         depends on COMPAT
343         default y
344         help
345           This option adds an alternative code sequence to work around ARM
346           erratum 845719 on Cortex-A53 parts up to r0p4.
347 
348           When running a compat (AArch32) userspace on an affected Cortex-A53
349           part, a load at EL0 from a virtual address that matches the bottom 32
350           bits of the virtual address used by a recent load at (AArch64) EL1
351           might return incorrect data.
352 
353           The workaround is to write the contextidr_el1 register on exception
354           return to a 32-bit task.
355           Please note that this does not necessarily enable the workaround,
356           as it depends on the alternative framework, which will only patch
357           the kernel if an affected CPU is detected.
358 
359           If unsure, say Y.
360 
361 config ARM64_ERRATUM_843419
362         bool "Cortex-A53: 843419: A load or store might access an incorrect address"
363         depends on MODULES
364         default y
365         help
366           This option builds kernel modules using the large memory model in
367           order to avoid the use of the ADRP instruction, which can cause
368           a subsequent memory access to use an incorrect address on Cortex-A53
369           parts up to r0p4.
370 
371           Note that the kernel itself must be linked with a version of ld
372           which fixes potentially affected ADRP instructions through the
373           use of veneers.
374 
375           If unsure, say Y.
376 
377 config CAVIUM_ERRATUM_22375
378         bool "Cavium erratum 22375, 24313"
379         default y
380         help
381           Enable workaround for erratum 22375, 24313.
382 
383           This implements two gicv3-its errata workarounds for ThunderX. Both
384           with small impact affecting only ITS table allocation.
385 
386             erratum 22375: only alloc 8MB table size
387             erratum 24313: ignore memory access type
388 
389           The fixes are in ITS initialization and basically ignore memory access
390           type and table size provided by the TYPER and BASER registers.
391 
392           If unsure, say Y.
393 
394 config CAVIUM_ERRATUM_23154
395         bool "Cavium erratum 23154: Access to ICC_IAR1_EL1 is not sync'ed"
396         default y
397         help
398           The gicv3 of ThunderX requires a modified version for
399           reading the IAR status to ensure data synchronization
400           (access to icc_iar1_el1 is not sync'ed before and after).
401 
402           If unsure, say Y.
403 
404 endmenu
405 
406 
407 choice
408         prompt "Page size"
409         default ARM64_4K_PAGES
410         help
411           Page size (translation granule) configuration.
412 
413 config ARM64_4K_PAGES
414         bool "4KB"
415         help
416           This feature enables 4KB pages support.
417 
418 config ARM64_16K_PAGES
419         bool "16KB"
420         help
421           The system will use 16KB pages support. AArch32 emulation
422           requires applications compiled with 16K (or a multiple of 16K)
423           aligned segments.
424 
425 config ARM64_64K_PAGES
426         bool "64KB"
427         help
428           This feature enables 64KB pages support (4KB by default)
429           allowing only two levels of page tables and faster TLB
430           look-up. AArch32 emulation requires applications compiled
431           with 64K aligned segments.
432 
433 endchoice
434 
435 choice
436         prompt "Virtual address space size"
437         default ARM64_VA_BITS_39 if ARM64_4K_PAGES
438         default ARM64_VA_BITS_47 if ARM64_16K_PAGES
439         default ARM64_VA_BITS_42 if ARM64_64K_PAGES
440         help
441           Allows choosing one of multiple possible virtual address
442           space sizes. The level of translation table is determined by
443           a combination of page size and virtual address space size.
444 
445 config ARM64_VA_BITS_36
446         bool "36-bit" if EXPERT
447         depends on ARM64_16K_PAGES
448 
449 config ARM64_VA_BITS_39
450         bool "39-bit"
451         depends on ARM64_4K_PAGES
452 
453 config ARM64_VA_BITS_42
454         bool "42-bit"
455         depends on ARM64_64K_PAGES
456 
457 config ARM64_VA_BITS_47
458         bool "47-bit"
459         depends on ARM64_16K_PAGES
460 
461 config ARM64_VA_BITS_48
462         bool "48-bit"
463 
464 endchoice
465 
466 config ARM64_VA_BITS
467         int
468         default 36 if ARM64_VA_BITS_36
469         default 39 if ARM64_VA_BITS_39
470         default 42 if ARM64_VA_BITS_42
471         default 47 if ARM64_VA_BITS_47
472         default 48 if ARM64_VA_BITS_48
473 
474 config CPU_BIG_ENDIAN
475        bool "Build big-endian kernel"
476        help
477          Say Y if you plan on running a kernel in big-endian mode.
478 
479 config SCHED_MC
480         bool "Multi-core scheduler support"
481         help
482           Multi-core scheduler support improves the CPU scheduler's decision
483           making when dealing with multi-core CPU chips at a cost of slightly
484           increased overhead in some places. If unsure say N here.
485 
486 config SCHED_SMT
487         bool "SMT scheduler support"
488         help
489           Improves the CPU scheduler's decision making when dealing with
490           MultiThreading at a cost of slightly increased overhead in some
491           places. If unsure say N here.
492 
493 config NR_CPUS
494         int "Maximum number of CPUs (2-4096)"
495         range 2 4096
496         # These have to remain sorted largest to smallest
497         default "64"
498 
499 config HOTPLUG_CPU
500         bool "Support for hot-pluggable CPUs"
501         select GENERIC_IRQ_MIGRATION
502         help
503           Say Y here to experiment with turning CPUs off and on.  CPUs
504           can be controlled through /sys/devices/system/cpu.
505 
506 source kernel/Kconfig.preempt
507 source kernel/Kconfig.hz
508 
509 config ARCH_HAS_HOLES_MEMORYMODEL
510         def_bool y if SPARSEMEM
511 
512 config ARCH_SPARSEMEM_ENABLE
513         def_bool y
514         select SPARSEMEM_VMEMMAP_ENABLE
515 
516 config ARCH_SPARSEMEM_DEFAULT
517         def_bool ARCH_SPARSEMEM_ENABLE
518 
519 config ARCH_SELECT_MEMORY_MODEL
520         def_bool ARCH_SPARSEMEM_ENABLE
521 
522 config HAVE_ARCH_PFN_VALID
523         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
524 
525 config HW_PERF_EVENTS
526         def_bool y
527         depends on ARM_PMU
528 
529 config SYS_SUPPORTS_HUGETLBFS
530         def_bool y
531 
532 config ARCH_WANT_GENERAL_HUGETLB
533         def_bool y
534 
535 config ARCH_WANT_HUGE_PMD_SHARE
536         def_bool y if ARM64_4K_PAGES || (ARM64_16K_PAGES && !ARM64_VA_BITS_36)
537 
538 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
539         def_bool y
540 
541 config ARCH_HAS_CACHE_LINE_SIZE
542         def_bool y
543 
544 source "mm/Kconfig"
545 
546 config SECCOMP
547         bool "Enable seccomp to safely compute untrusted bytecode"
548         ---help---
549           This kernel feature is useful for number crunching applications
550           that may need to compute untrusted bytecode during their
551           execution. By using pipes or other transports made available to
552           the process as file descriptors supporting the read/write
553           syscalls, it's possible to isolate those applications in
554           their own address space using seccomp. Once seccomp is
555           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
556           and the task is only allowed to execute a few safe syscalls
557           defined by each seccomp mode.
558 
559 config XEN_DOM0
560         def_bool y
561         depends on XEN
562 
563 config XEN
564         bool "Xen guest support on ARM64"
565         depends on ARM64 && OF
566         select SWIOTLB_XEN
567         help
568           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM64.
569 
570 config FORCE_MAX_ZONEORDER
571         int
572         default "14" if (ARM64_64K_PAGES && TRANSPARENT_HUGEPAGE)
573         default "12" if (ARM64_16K_PAGES && TRANSPARENT_HUGEPAGE)
574         default "11"
575         help
576           The kernel memory allocator divides physically contiguous memory
577           blocks into "zones", where each zone is a power of two number of
578           pages.  This option selects the largest power of two that the kernel
579           keeps in the memory allocator.  If you need to allocate very large
580           blocks of physically contiguous memory, then you may need to
581           increase this value.
582 
583           This config option is actually maximum order plus one. For example,
584           a value of 11 means that the largest free memory block is 2^10 pages.
585 
586           We make sure that we can allocate upto a HugePage size for each configuration.
587           Hence we have :
588                 MAX_ORDER = (PMD_SHIFT - PAGE_SHIFT) + 1 => PAGE_SHIFT - 2
589 
590           However for 4K, we choose a higher default value, 11 as opposed to 10, giving us
591           4M allocations matching the default size used by generic code.
592 
593 menuconfig ARMV8_DEPRECATED
594         bool "Emulate deprecated/obsolete ARMv8 instructions"
595         depends on COMPAT
596         help
597           Legacy software support may require certain instructions
598           that have been deprecated or obsoleted in the architecture.
599 
600           Enable this config to enable selective emulation of these
601           features.
602 
603           If unsure, say Y
604 
605 if ARMV8_DEPRECATED
606 
607 config SWP_EMULATION
608         bool "Emulate SWP/SWPB instructions"
609         help
610           ARMv8 obsoletes the use of A32 SWP/SWPB instructions such that
611           they are always undefined. Say Y here to enable software
612           emulation of these instructions for userspace using LDXR/STXR.
613 
614           In some older versions of glibc [<=2.8] SWP is used during futex
615           trylock() operations with the assumption that the code will not
616           be preempted. This invalid assumption may be more likely to fail
617           with SWP emulation enabled, leading to deadlock of the user
618           application.
619 
620           NOTE: when accessing uncached shared regions, LDXR/STXR rely
621           on an external transaction monitoring block called a global
622           monitor to maintain update atomicity. If your system does not
623           implement a global monitor, this option can cause programs that
624           perform SWP operations to uncached memory to deadlock.
625 
626           If unsure, say Y
627 
628 config CP15_BARRIER_EMULATION
629         bool "Emulate CP15 Barrier instructions"
630         help
631           The CP15 barrier instructions - CP15ISB, CP15DSB, and
632           CP15DMB - are deprecated in ARMv8 (and ARMv7). It is
633           strongly recommended to use the ISB, DSB, and DMB
634           instructions instead.
635 
636           Say Y here to enable software emulation of these
637           instructions for AArch32 userspace code. When this option is
638           enabled, CP15 barrier usage is traced which can help
639           identify software that needs updating.
640 
641           If unsure, say Y
642 
643 config SETEND_EMULATION
644         bool "Emulate SETEND instruction"
645         help
646           The SETEND instruction alters the data-endianness of the
647           AArch32 EL0, and is deprecated in ARMv8.
648 
649           Say Y here to enable software emulation of the instruction
650           for AArch32 userspace code.
651 
652           Note: All the cpus on the system must have mixed endian support at EL0
653           for this feature to be enabled. If a new CPU - which doesn't support mixed
654           endian - is hotplugged in after this feature has been enabled, there could
655           be unexpected results in the applications.
656 
657           If unsure, say Y
658 endif
659 
660 menu "ARMv8.1 architectural features"
661 
662 config ARM64_HW_AFDBM
663         bool "Support for hardware updates of the Access and Dirty page flags"
664         default y
665         help
666           The ARMv8.1 architecture extensions introduce support for
667           hardware updates of the access and dirty information in page
668           table entries. When enabled in TCR_EL1 (HA and HD bits) on
669           capable processors, accesses to pages with PTE_AF cleared will
670           set this bit instead of raising an access flag fault.
671           Similarly, writes to read-only pages with the DBM bit set will
672           clear the read-only bit (AP[2]) instead of raising a
673           permission fault.
674 
675           Kernels built with this configuration option enabled continue
676           to work on pre-ARMv8.1 hardware and the performance impact is
677           minimal. If unsure, say Y.
678 
679 config ARM64_PAN
680         bool "Enable support for Privileged Access Never (PAN)"
681         default y
682         help
683          Privileged Access Never (PAN; part of the ARMv8.1 Extensions)
684          prevents the kernel or hypervisor from accessing user-space (EL0)
685          memory directly.
686 
687          Choosing this option will cause any unprotected (not using
688          copy_to_user et al) memory access to fail with a permission fault.
689 
690          The feature is detected at runtime, and will remain as a 'nop'
691          instruction if the cpu does not implement the feature.
692 
693 config ARM64_LSE_ATOMICS
694         bool "Atomic instructions"
695         help
696           As part of the Large System Extensions, ARMv8.1 introduces new
697           atomic instructions that are designed specifically to scale in
698           very large systems.
699 
700           Say Y here to make use of these instructions for the in-kernel
701           atomic routines. This incurs a small overhead on CPUs that do
702           not support these instructions and requires the kernel to be
703           built with binutils >= 2.25.
704 
705 endmenu
706 
707 endmenu
708 
709 menu "Boot options"
710 
711 config CMDLINE
712         string "Default kernel command string"
713         default ""
714         help
715           Provide a set of default command-line options at build time by
716           entering them here. As a minimum, you should specify the the
717           root device (e.g. root=/dev/nfs).
718 
719 config CMDLINE_FORCE
720         bool "Always use the default kernel command string"
721         help
722           Always use the default kernel command string, even if the boot
723           loader passes other arguments to the kernel.
724           This is useful if you cannot or don't want to change the
725           command-line options your boot loader passes to the kernel.
726 
727 config EFI_STUB
728         bool
729 
730 config EFI
731         bool "UEFI runtime support"
732         depends on OF && !CPU_BIG_ENDIAN
733         select LIBFDT
734         select UCS2_STRING
735         select EFI_PARAMS_FROM_FDT
736         select EFI_RUNTIME_WRAPPERS
737         select EFI_STUB
738         select EFI_ARMSTUB
739         default y
740         help
741           This option provides support for runtime services provided
742           by UEFI firmware (such as non-volatile variables, realtime
743           clock, and platform reset). A UEFI stub is also provided to
744           allow the kernel to be booted as an EFI application. This
745           is only useful on systems that have UEFI firmware.
746 
747 config DMI
748         bool "Enable support for SMBIOS (DMI) tables"
749         depends on EFI
750         default y
751         help
752           This enables SMBIOS/DMI feature for systems.
753 
754           This option is only useful on systems that have UEFI firmware.
755           However, even with this option, the resultant kernel should
756           continue to boot on existing non-UEFI platforms.
757 
758 endmenu
759 
760 menu "Userspace binary formats"
761 
762 source "fs/Kconfig.binfmt"
763 
764 config COMPAT
765         bool "Kernel support for 32-bit EL0"
766         depends on ARM64_4K_PAGES || EXPERT
767         select COMPAT_BINFMT_ELF
768         select HAVE_UID16
769         select OLD_SIGSUSPEND3
770         select COMPAT_OLD_SIGACTION
771         help
772           This option enables support for a 32-bit EL0 running under a 64-bit
773           kernel at EL1. AArch32-specific components such as system calls,
774           the user helper functions, VFP support and the ptrace interface are
775           handled appropriately by the kernel.
776 
777           If you use a page size other than 4KB (i.e, 16KB or 64KB), please be aware
778           that you will only be able to execute AArch32 binaries that were compiled
779           with page size aligned segments.
780 
781           If you want to execute 32-bit userspace applications, say Y.
782 
783 config SYSVIPC_COMPAT
784         def_bool y
785         depends on COMPAT && SYSVIPC
786 
787 endmenu
788 
789 menu "Power management options"
790 
791 source "kernel/power/Kconfig"
792 
793 config ARCH_SUSPEND_POSSIBLE
794         def_bool y
795 
796 endmenu
797 
798 menu "CPU Power Management"
799 
800 source "drivers/cpuidle/Kconfig"
801 
802 source "drivers/cpufreq/Kconfig"
803 
804 endmenu
805 
806 source "net/Kconfig"
807 
808 source "drivers/Kconfig"
809 
810 source "drivers/firmware/Kconfig"
811 
812 source "drivers/acpi/Kconfig"
813 
814 source "fs/Kconfig"
815 
816 source "arch/arm64/kvm/Kconfig"
817 
818 source "arch/arm64/Kconfig.debug"
819 
820 source "security/Kconfig"
821 
822 source "crypto/Kconfig"
823 if CRYPTO
824 source "arch/arm64/crypto/Kconfig"
825 endif
826 
827 source "lib/Kconfig"

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