Version:  2.0.40 2.2.26 2.4.37 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10

Linux/arch/arm/mm/Kconfig

  1 comment "Processor Type"
  2 
  3 # Select CPU types depending on the architecture selected.  This selects
  4 # which CPUs we support in the kernel image, and the compiler instruction
  5 # optimiser behaviour.
  6 
  7 # ARM7TDMI
  8 config CPU_ARM7TDMI
  9         bool
 10         depends on !MMU
 11         select CPU_32v4T
 12         select CPU_ABRT_LV4T
 13         select CPU_CACHE_V4
 14         select CPU_PABRT_LEGACY
 15         help
 16           A 32-bit RISC microprocessor based on the ARM7 processor core
 17           which has no memory control unit and cache.
 18 
 19           Say Y if you want support for the ARM7TDMI processor.
 20           Otherwise, say N.
 21 
 22 # ARM720T
 23 config CPU_ARM720T
 24         bool
 25         select CPU_32v4T
 26         select CPU_ABRT_LV4T
 27         select CPU_CACHE_V4
 28         select CPU_CACHE_VIVT
 29         select CPU_COPY_V4WT if MMU
 30         select CPU_CP15_MMU
 31         select CPU_PABRT_LEGACY
 32         select CPU_TLB_V4WT if MMU
 33         help
 34           A 32-bit RISC processor with 8kByte Cache, Write Buffer and
 35           MMU built around an ARM7TDMI core.
 36 
 37           Say Y if you want support for the ARM720T processor.
 38           Otherwise, say N.
 39 
 40 # ARM740T
 41 config CPU_ARM740T
 42         bool
 43         depends on !MMU
 44         select CPU_32v4T
 45         select CPU_ABRT_LV4T
 46         select CPU_CACHE_V4
 47         select CPU_CP15_MPU
 48         select CPU_PABRT_LEGACY
 49         help
 50           A 32-bit RISC processor with 8KB cache or 4KB variants,
 51           write buffer and MPU(Protection Unit) built around
 52           an ARM7TDMI core.
 53 
 54           Say Y if you want support for the ARM740T processor.
 55           Otherwise, say N.
 56 
 57 # ARM9TDMI
 58 config CPU_ARM9TDMI
 59         bool
 60         depends on !MMU
 61         select CPU_32v4T
 62         select CPU_ABRT_NOMMU
 63         select CPU_CACHE_V4
 64         select CPU_PABRT_LEGACY
 65         help
 66           A 32-bit RISC microprocessor based on the ARM9 processor core
 67           which has no memory control unit and cache.
 68 
 69           Say Y if you want support for the ARM9TDMI processor.
 70           Otherwise, say N.
 71 
 72 # ARM920T
 73 config CPU_ARM920T
 74         bool
 75         select CPU_32v4T
 76         select CPU_ABRT_EV4T
 77         select CPU_CACHE_V4WT
 78         select CPU_CACHE_VIVT
 79         select CPU_COPY_V4WB if MMU
 80         select CPU_CP15_MMU
 81         select CPU_PABRT_LEGACY
 82         select CPU_TLB_V4WBI if MMU
 83         help
 84           The ARM920T is licensed to be produced by numerous vendors,
 85           and is used in the Cirrus EP93xx and the Samsung S3C2410.
 86 
 87           Say Y if you want support for the ARM920T processor.
 88           Otherwise, say N.
 89 
 90 # ARM922T
 91 config CPU_ARM922T
 92         bool
 93         select CPU_32v4T
 94         select CPU_ABRT_EV4T
 95         select CPU_CACHE_V4WT
 96         select CPU_CACHE_VIVT
 97         select CPU_COPY_V4WB if MMU
 98         select CPU_CP15_MMU
 99         select CPU_PABRT_LEGACY
100         select CPU_TLB_V4WBI if MMU
101         help
102           The ARM922T is a version of the ARM920T, but with smaller
103           instruction and data caches. It is used in Altera's
104           Excalibur XA device family and Micrel's KS8695 Centaur.
105 
106           Say Y if you want support for the ARM922T processor.
107           Otherwise, say N.
108 
109 # ARM925T
110 config CPU_ARM925T
111         bool
112         select CPU_32v4T
113         select CPU_ABRT_EV4T
114         select CPU_CACHE_V4WT
115         select CPU_CACHE_VIVT
116         select CPU_COPY_V4WB if MMU
117         select CPU_CP15_MMU
118         select CPU_PABRT_LEGACY
119         select CPU_TLB_V4WBI if MMU
120         help
121           The ARM925T is a mix between the ARM920T and ARM926T, but with
122           different instruction and data caches. It is used in TI's OMAP
123           device family.
124 
125           Say Y if you want support for the ARM925T processor.
126           Otherwise, say N.
127 
128 # ARM926T
129 config CPU_ARM926T
130         bool
131         select CPU_32v5
132         select CPU_ABRT_EV5TJ
133         select CPU_CACHE_VIVT
134         select CPU_COPY_V4WB if MMU
135         select CPU_CP15_MMU
136         select CPU_PABRT_LEGACY
137         select CPU_TLB_V4WBI if MMU
138         help
139           This is a variant of the ARM920.  It has slightly different
140           instruction sequences for cache and TLB operations.  Curiously,
141           there is no documentation on it at the ARM corporate website.
142 
143           Say Y if you want support for the ARM926T processor.
144           Otherwise, say N.
145 
146 # FA526
147 config CPU_FA526
148         bool
149         select CPU_32v4
150         select CPU_ABRT_EV4
151         select CPU_CACHE_FA
152         select CPU_CACHE_VIVT
153         select CPU_COPY_FA if MMU
154         select CPU_CP15_MMU
155         select CPU_PABRT_LEGACY
156         select CPU_TLB_FA if MMU
157         help
158           The FA526 is a version of the ARMv4 compatible processor with
159           Branch Target Buffer, Unified TLB and cache line size 16.
160 
161           Say Y if you want support for the FA526 processor.
162           Otherwise, say N.
163 
164 # ARM940T
165 config CPU_ARM940T
166         bool
167         depends on !MMU
168         select CPU_32v4T
169         select CPU_ABRT_NOMMU
170         select CPU_CACHE_VIVT
171         select CPU_CP15_MPU
172         select CPU_PABRT_LEGACY
173         help
174           ARM940T is a member of the ARM9TDMI family of general-
175           purpose microprocessors with MPU and separate 4KB
176           instruction and 4KB data cases, each with a 4-word line
177           length.
178 
179           Say Y if you want support for the ARM940T processor.
180           Otherwise, say N.
181 
182 # ARM946E-S
183 config CPU_ARM946E
184         bool
185         depends on !MMU
186         select CPU_32v5
187         select CPU_ABRT_NOMMU
188         select CPU_CACHE_VIVT
189         select CPU_CP15_MPU
190         select CPU_PABRT_LEGACY
191         help
192           ARM946E-S is a member of the ARM9E-S family of high-
193           performance, 32-bit system-on-chip processor solutions.
194           The TCM and ARMv5TE 32-bit instruction set is supported.
195 
196           Say Y if you want support for the ARM946E-S processor.
197           Otherwise, say N.
198 
199 # ARM1020 - needs validating
200 config CPU_ARM1020
201         bool
202         select CPU_32v5
203         select CPU_ABRT_EV4T
204         select CPU_CACHE_V4WT
205         select CPU_CACHE_VIVT
206         select CPU_COPY_V4WB if MMU
207         select CPU_CP15_MMU
208         select CPU_PABRT_LEGACY
209         select CPU_TLB_V4WBI if MMU
210         help
211           The ARM1020 is the 32K cached version of the ARM10 processor,
212           with an addition of a floating-point unit.
213 
214           Say Y if you want support for the ARM1020 processor.
215           Otherwise, say N.
216 
217 # ARM1020E - needs validating
218 config CPU_ARM1020E
219         bool
220         depends on n
221         select CPU_32v5
222         select CPU_ABRT_EV4T
223         select CPU_CACHE_V4WT
224         select CPU_CACHE_VIVT
225         select CPU_COPY_V4WB if MMU
226         select CPU_CP15_MMU
227         select CPU_PABRT_LEGACY
228         select CPU_TLB_V4WBI if MMU
229 
230 # ARM1022E
231 config CPU_ARM1022
232         bool
233         select CPU_32v5
234         select CPU_ABRT_EV4T
235         select CPU_CACHE_VIVT
236         select CPU_COPY_V4WB if MMU # can probably do better
237         select CPU_CP15_MMU
238         select CPU_PABRT_LEGACY
239         select CPU_TLB_V4WBI if MMU
240         help
241           The ARM1022E is an implementation of the ARMv5TE architecture
242           based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
243           embedded trace macrocell, and a floating-point unit.
244 
245           Say Y if you want support for the ARM1022E processor.
246           Otherwise, say N.
247 
248 # ARM1026EJ-S
249 config CPU_ARM1026
250         bool
251         select CPU_32v5
252         select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
253         select CPU_CACHE_VIVT
254         select CPU_COPY_V4WB if MMU # can probably do better
255         select CPU_CP15_MMU
256         select CPU_PABRT_LEGACY
257         select CPU_TLB_V4WBI if MMU
258         help
259           The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
260           based upon the ARM10 integer core.
261 
262           Say Y if you want support for the ARM1026EJ-S processor.
263           Otherwise, say N.
264 
265 # SA110
266 config CPU_SA110
267         bool
268         select CPU_32v3 if ARCH_RPC
269         select CPU_32v4 if !ARCH_RPC
270         select CPU_ABRT_EV4
271         select CPU_CACHE_V4WB
272         select CPU_CACHE_VIVT
273         select CPU_COPY_V4WB if MMU
274         select CPU_CP15_MMU
275         select CPU_PABRT_LEGACY
276         select CPU_TLB_V4WB if MMU
277         help
278           The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
279           is available at five speeds ranging from 100 MHz to 233 MHz.
280           More information is available at
281           <http://developer.intel.com/design/strong/sa110.htm>.
282 
283           Say Y if you want support for the SA-110 processor.
284           Otherwise, say N.
285 
286 # SA1100
287 config CPU_SA1100
288         bool
289         select CPU_32v4
290         select CPU_ABRT_EV4
291         select CPU_CACHE_V4WB
292         select CPU_CACHE_VIVT
293         select CPU_CP15_MMU
294         select CPU_PABRT_LEGACY
295         select CPU_TLB_V4WB if MMU
296 
297 # XScale
298 config CPU_XSCALE
299         bool
300         select CPU_32v5
301         select CPU_ABRT_EV5T
302         select CPU_CACHE_VIVT
303         select CPU_CP15_MMU
304         select CPU_PABRT_LEGACY
305         select CPU_TLB_V4WBI if MMU
306 
307 # XScale Core Version 3
308 config CPU_XSC3
309         bool
310         select CPU_32v5
311         select CPU_ABRT_EV5T
312         select CPU_CACHE_VIVT
313         select CPU_CP15_MMU
314         select CPU_PABRT_LEGACY
315         select CPU_TLB_V4WBI if MMU
316         select IO_36
317 
318 # Marvell PJ1 (Mohawk)
319 config CPU_MOHAWK
320         bool
321         select CPU_32v5
322         select CPU_ABRT_EV5T
323         select CPU_CACHE_VIVT
324         select CPU_COPY_V4WB if MMU
325         select CPU_CP15_MMU
326         select CPU_PABRT_LEGACY
327         select CPU_TLB_V4WBI if MMU
328 
329 # Feroceon
330 config CPU_FEROCEON
331         bool
332         select CPU_32v5
333         select CPU_ABRT_EV5T
334         select CPU_CACHE_VIVT
335         select CPU_COPY_FEROCEON if MMU
336         select CPU_CP15_MMU
337         select CPU_PABRT_LEGACY
338         select CPU_TLB_FEROCEON if MMU
339 
340 config CPU_FEROCEON_OLD_ID
341         bool "Accept early Feroceon cores with an ARM926 ID"
342         depends on CPU_FEROCEON && !CPU_ARM926T
343         default y
344         help
345           This enables the usage of some old Feroceon cores
346           for which the CPU ID is equal to the ARM926 ID.
347           Relevant for Feroceon-1850 and early Feroceon-2850.
348 
349 # Marvell PJ4
350 config CPU_PJ4
351         bool
352         select ARM_THUMBEE
353         select CPU_V7
354 
355 config CPU_PJ4B
356         bool
357         select CPU_V7
358 
359 # ARMv6
360 config CPU_V6
361         bool
362         select CPU_32v6
363         select CPU_ABRT_EV6
364         select CPU_CACHE_V6
365         select CPU_CACHE_VIPT
366         select CPU_COPY_V6 if MMU
367         select CPU_CP15_MMU
368         select CPU_HAS_ASID if MMU
369         select CPU_PABRT_V6
370         select CPU_TLB_V6 if MMU
371 
372 # ARMv6k
373 config CPU_V6K
374         bool
375         select CPU_32v6
376         select CPU_32v6K
377         select CPU_ABRT_EV6
378         select CPU_CACHE_V6
379         select CPU_CACHE_VIPT
380         select CPU_COPY_V6 if MMU
381         select CPU_CP15_MMU
382         select CPU_HAS_ASID if MMU
383         select CPU_PABRT_V6
384         select CPU_TLB_V6 if MMU
385 
386 # ARMv7
387 config CPU_V7
388         bool
389         select CPU_32v6K
390         select CPU_32v7
391         select CPU_ABRT_EV7
392         select CPU_CACHE_V7
393         select CPU_CACHE_VIPT
394         select CPU_COPY_V6 if MMU
395         select CPU_CP15_MMU if MMU
396         select CPU_CP15_MPU if !MMU
397         select CPU_HAS_ASID if MMU
398         select CPU_PABRT_V7
399         select CPU_TLB_V7 if MMU
400 
401 # ARMv7M
402 config CPU_V7M
403         bool
404         select CPU_32v7M
405         select CPU_ABRT_NOMMU
406         select CPU_CACHE_V7M
407         select CPU_CACHE_NOP
408         select CPU_PABRT_LEGACY
409         select CPU_THUMBONLY
410 
411 config CPU_THUMBONLY
412         bool
413         # There are no CPUs available with MMU that don't implement an ARM ISA:
414         depends on !MMU
415         help
416           Select this if your CPU doesn't support the 32 bit ARM instructions.
417 
418 # Figure out what processor architecture version we should be using.
419 # This defines the compiler instruction set which depends on the machine type.
420 config CPU_32v3
421         bool
422         select CPU_USE_DOMAINS if MMU
423         select NEED_KUSER_HELPERS
424         select TLS_REG_EMUL if SMP || !MMU
425         select CPU_NO_EFFICIENT_FFS
426 
427 config CPU_32v4
428         bool
429         select CPU_USE_DOMAINS if MMU
430         select NEED_KUSER_HELPERS
431         select TLS_REG_EMUL if SMP || !MMU
432         select CPU_NO_EFFICIENT_FFS
433 
434 config CPU_32v4T
435         bool
436         select CPU_USE_DOMAINS if MMU
437         select NEED_KUSER_HELPERS
438         select TLS_REG_EMUL if SMP || !MMU
439         select CPU_NO_EFFICIENT_FFS
440 
441 config CPU_32v5
442         bool
443         select CPU_USE_DOMAINS if MMU
444         select NEED_KUSER_HELPERS
445         select TLS_REG_EMUL if SMP || !MMU
446 
447 config CPU_32v6
448         bool
449         select TLS_REG_EMUL if !CPU_32v6K && !MMU
450 
451 config CPU_32v6K
452         bool
453 
454 config CPU_32v7
455         bool
456 
457 config CPU_32v7M
458         bool
459 
460 # The abort model
461 config CPU_ABRT_NOMMU
462         bool
463 
464 config CPU_ABRT_EV4
465         bool
466 
467 config CPU_ABRT_EV4T
468         bool
469 
470 config CPU_ABRT_LV4T
471         bool
472 
473 config CPU_ABRT_EV5T
474         bool
475 
476 config CPU_ABRT_EV5TJ
477         bool
478 
479 config CPU_ABRT_EV6
480         bool
481 
482 config CPU_ABRT_EV7
483         bool
484 
485 config CPU_PABRT_LEGACY
486         bool
487 
488 config CPU_PABRT_V6
489         bool
490 
491 config CPU_PABRT_V7
492         bool
493 
494 # The cache model
495 config CPU_CACHE_V4
496         bool
497 
498 config CPU_CACHE_V4WT
499         bool
500 
501 config CPU_CACHE_V4WB
502         bool
503 
504 config CPU_CACHE_V6
505         bool
506 
507 config CPU_CACHE_V7
508         bool
509 
510 config CPU_CACHE_NOP
511         bool
512 
513 config CPU_CACHE_VIVT
514         bool
515 
516 config CPU_CACHE_VIPT
517         bool
518 
519 config CPU_CACHE_FA
520         bool
521 
522 config CPU_CACHE_V7M
523         bool
524 
525 if MMU
526 # The copy-page model
527 config CPU_COPY_V4WT
528         bool
529 
530 config CPU_COPY_V4WB
531         bool
532 
533 config CPU_COPY_FEROCEON
534         bool
535 
536 config CPU_COPY_FA
537         bool
538 
539 config CPU_COPY_V6
540         bool
541 
542 # This selects the TLB model
543 config CPU_TLB_V4WT
544         bool
545         help
546           ARM Architecture Version 4 TLB with writethrough cache.
547 
548 config CPU_TLB_V4WB
549         bool
550         help
551           ARM Architecture Version 4 TLB with writeback cache.
552 
553 config CPU_TLB_V4WBI
554         bool
555         help
556           ARM Architecture Version 4 TLB with writeback cache and invalidate
557           instruction cache entry.
558 
559 config CPU_TLB_FEROCEON
560         bool
561         help
562           Feroceon TLB (v4wbi with non-outer-cachable page table walks).
563 
564 config CPU_TLB_FA
565         bool
566         help
567           Faraday ARM FA526 architecture, unified TLB with writeback cache
568           and invalidate instruction cache entry. Branch target buffer is
569           also supported.
570 
571 config CPU_TLB_V6
572         bool
573 
574 config CPU_TLB_V7
575         bool
576 
577 config VERIFY_PERMISSION_FAULT
578         bool
579 endif
580 
581 config CPU_HAS_ASID
582         bool
583         help
584           This indicates whether the CPU has the ASID register; used to
585           tag TLB and possibly cache entries.
586 
587 config CPU_CP15
588         bool
589         help
590           Processor has the CP15 register.
591 
592 config CPU_CP15_MMU
593         bool
594         select CPU_CP15
595         help
596           Processor has the CP15 register, which has MMU related registers.
597 
598 config CPU_CP15_MPU
599         bool
600         select CPU_CP15
601         help
602           Processor has the CP15 register, which has MPU related registers.
603 
604 config CPU_USE_DOMAINS
605         bool
606         help
607           This option enables or disables the use of domain switching
608           via the set_fs() function.
609 
610 config CPU_V7M_NUM_IRQ
611         int "Number of external interrupts connected to the NVIC"
612         depends on CPU_V7M
613         default 90 if ARCH_STM32
614         default 38 if ARCH_EFM32
615         default 112 if SOC_VF610
616         default 240
617         help
618           This option indicates the number of interrupts connected to the NVIC.
619           The value can be larger than the real number of interrupts supported
620           by the system, but must not be lower.
621           The default value is 240, corresponding to the maximum number of
622           interrupts supported by the NVIC on Cortex-M family.
623 
624           If unsure, keep default value.
625 
626 #
627 # CPU supports 36-bit I/O
628 #
629 config IO_36
630         bool
631 
632 comment "Processor Features"
633 
634 config ARM_LPAE
635         bool "Support for the Large Physical Address Extension"
636         depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
637                 !CPU_32v4 && !CPU_32v3
638         help
639           Say Y if you have an ARMv7 processor supporting the LPAE page
640           table format and you would like to access memory beyond the
641           4GB limit. The resulting kernel image will not run on
642           processors without the LPA extension.
643 
644           If unsure, say N.
645 
646 config ARM_PV_FIXUP
647         def_bool y
648         depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE
649 
650 config ARCH_PHYS_ADDR_T_64BIT
651         def_bool ARM_LPAE
652 
653 config ARCH_DMA_ADDR_T_64BIT
654         bool
655 
656 config ARM_THUMB
657         bool "Support Thumb user binaries" if !CPU_THUMBONLY
658         depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \
659                 CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \
660                 CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
661                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \
662                 CPU_V7 || CPU_FEROCEON || CPU_V7M
663         default y
664         help
665           Say Y if you want to include kernel support for running user space
666           Thumb binaries.
667 
668           The Thumb instruction set is a compressed form of the standard ARM
669           instruction set resulting in smaller binaries at the expense of
670           slightly less efficient code.
671 
672           If you don't know what this all is, saying Y is a safe choice.
673 
674 config ARM_THUMBEE
675         bool "Enable ThumbEE CPU extension"
676         depends on CPU_V7
677         help
678           Say Y here if you have a CPU with the ThumbEE extension and code to
679           make use of it. Say N for code that can run on CPUs without ThumbEE.
680 
681 config ARM_VIRT_EXT
682         bool
683         depends on MMU
684         default y if CPU_V7
685         help
686           Enable the kernel to make use of the ARM Virtualization
687           Extensions to install hypervisors without run-time firmware
688           assistance.
689 
690           A compliant bootloader is required in order to make maximum
691           use of this feature.  Refer to Documentation/arm/Booting for
692           details.
693 
694 config SWP_EMULATE
695         bool "Emulate SWP/SWPB instructions" if !SMP
696         depends on CPU_V7
697         default y if SMP
698         select HAVE_PROC_CPU if PROC_FS
699         help
700           ARMv6 architecture deprecates use of the SWP/SWPB instructions.
701           ARMv7 multiprocessing extensions introduce the ability to disable
702           these instructions, triggering an undefined instruction exception
703           when executed. Say Y here to enable software emulation of these
704           instructions for userspace (not kernel) using LDREX/STREX.
705           Also creates /proc/cpu/swp_emulation for statistics.
706 
707           In some older versions of glibc [<=2.8] SWP is used during futex
708           trylock() operations with the assumption that the code will not
709           be preempted. This invalid assumption may be more likely to fail
710           with SWP emulation enabled, leading to deadlock of the user
711           application.
712 
713           NOTE: when accessing uncached shared regions, LDREX/STREX rely
714           on an external transaction monitoring block called a global
715           monitor to maintain update atomicity. If your system does not
716           implement a global monitor, this option can cause programs that
717           perform SWP operations to uncached memory to deadlock.
718 
719           If unsure, say Y.
720 
721 config CPU_BIG_ENDIAN
722         bool "Build big-endian kernel"
723         depends on ARCH_SUPPORTS_BIG_ENDIAN
724         help
725           Say Y if you plan on running a kernel in big-endian mode.
726           Note that your board must be properly built and your board
727           port must properly enable any big-endian related features
728           of your chipset/board/processor.
729 
730 config CPU_ENDIAN_BE8
731         bool
732         depends on CPU_BIG_ENDIAN
733         default CPU_V6 || CPU_V6K || CPU_V7
734         help
735           Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
736 
737 config CPU_ENDIAN_BE32
738         bool
739         depends on CPU_BIG_ENDIAN
740         default !CPU_ENDIAN_BE8
741         help
742           Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
743 
744 config CPU_HIGH_VECTOR
745         depends on !MMU && CPU_CP15 && !CPU_ARM740T
746         bool "Select the High exception vector"
747         help
748           Say Y here to select high exception vector(0xFFFF0000~).
749           The exception vector can vary depending on the platform
750           design in nommu mode. If your platform needs to select
751           high exception vector, say Y.
752           Otherwise or if you are unsure, say N, and the low exception
753           vector (0x00000000~) will be used.
754 
755 config CPU_ICACHE_DISABLE
756         bool "Disable I-Cache (I-bit)"
757         depends on (CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)) || CPU_V7M
758         help
759           Say Y here to disable the processor instruction cache. Unless
760           you have a reason not to or are unsure, say N.
761 
762 config CPU_DCACHE_DISABLE
763         bool "Disable D-Cache (C-bit)"
764         depends on (CPU_CP15 && !SMP) || CPU_V7M
765         help
766           Say Y here to disable the processor data cache. Unless
767           you have a reason not to or are unsure, say N.
768 
769 config CPU_DCACHE_SIZE
770         hex
771         depends on CPU_ARM740T || CPU_ARM946E
772         default 0x00001000 if CPU_ARM740T
773         default 0x00002000 # default size for ARM946E-S
774         help
775           Some cores are synthesizable to have various sized cache. For
776           ARM946E-S case, it can vary from 0KB to 1MB.
777           To support such cache operations, it is efficient to know the size
778           before compile time.
779           If your SoC is configured to have a different size, define the value
780           here with proper conditions.
781 
782 config CPU_DCACHE_WRITETHROUGH
783         bool "Force write through D-cache"
784         depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
785         default y if CPU_ARM925T
786         help
787           Say Y here to use the data cache in writethrough mode. Unless you
788           specifically require this or are unsure, say N.
789 
790 config CPU_CACHE_ROUND_ROBIN
791         bool "Round robin I and D cache replacement algorithm"
792         depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
793         help
794           Say Y here to use the predictable round-robin cache replacement
795           policy.  Unless you specifically require this or are unsure, say N.
796 
797 config CPU_BPREDICT_DISABLE
798         bool "Disable branch prediction"
799         depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 || CPU_V7M
800         help
801           Say Y here to disable branch prediction.  If unsure, say N.
802 
803 config TLS_REG_EMUL
804         bool
805         select NEED_KUSER_HELPERS
806         help
807           An SMP system using a pre-ARMv6 processor (there are apparently
808           a few prototypes like that in existence) and therefore access to
809           that required register must be emulated.
810 
811 config NEED_KUSER_HELPERS
812         bool
813 
814 config KUSER_HELPERS
815         bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
816         depends on MMU
817         default y
818         help
819           Warning: disabling this option may break user programs.
820 
821           Provide kuser helpers in the vector page.  The kernel provides
822           helper code to userspace in read only form at a fixed location
823           in the high vector page to allow userspace to be independent of
824           the CPU type fitted to the system.  This permits binaries to be
825           run on ARMv4 through to ARMv7 without modification.
826 
827           See Documentation/arm/kernel_user_helpers.txt for details.
828 
829           However, the fixed address nature of these helpers can be used
830           by ROP (return orientated programming) authors when creating
831           exploits.
832 
833           If all of the binaries and libraries which run on your platform
834           are built specifically for your platform, and make no use of
835           these helpers, then you can turn this option off to hinder
836           such exploits. However, in that case, if a binary or library
837           relying on those helpers is run, it will receive a SIGILL signal,
838           which will terminate the program.
839 
840           Say N here only if you are absolutely certain that you do not
841           need these helpers; otherwise, the safe option is to say Y.
842 
843 config VDSO
844         bool "Enable VDSO for acceleration of some system calls"
845         depends on AEABI && MMU && CPU_V7
846         default y if ARM_ARCH_TIMER
847         select GENERIC_TIME_VSYSCALL
848         help
849           Place in the process address space an ELF shared object
850           providing fast implementations of gettimeofday and
851           clock_gettime.  Systems that implement the ARM architected
852           timer will receive maximum benefit.
853 
854           You must have glibc 2.22 or later for programs to seamlessly
855           take advantage of this.
856 
857 config DMA_CACHE_RWFO
858         bool "Enable read/write for ownership DMA cache maintenance"
859         depends on CPU_V6K && SMP
860         default y
861         help
862           The Snoop Control Unit on ARM11MPCore does not detect the
863           cache maintenance operations and the dma_{map,unmap}_area()
864           functions may leave stale cache entries on other CPUs. By
865           enabling this option, Read or Write For Ownership in the ARMv6
866           DMA cache maintenance functions is performed. These LDR/STR
867           instructions change the cache line state to shared or modified
868           so that the cache operation has the desired effect.
869 
870           Note that the workaround is only valid on processors that do
871           not perform speculative loads into the D-cache. For such
872           processors, if cache maintenance operations are not broadcast
873           in hardware, other workarounds are needed (e.g. cache
874           maintenance broadcasting in software via FIQ).
875 
876 config OUTER_CACHE
877         bool
878 
879 config OUTER_CACHE_SYNC
880         bool
881         select ARM_HEAVY_MB
882         help
883           The outer cache has a outer_cache_fns.sync function pointer
884           that can be used to drain the write buffer of the outer cache.
885 
886 config CACHE_FEROCEON_L2
887         bool "Enable the Feroceon L2 cache controller"
888         depends on ARCH_MV78XX0 || ARCH_MVEBU
889         default y
890         select OUTER_CACHE
891         help
892           This option enables the Feroceon L2 cache controller.
893 
894 config CACHE_FEROCEON_L2_WRITETHROUGH
895         bool "Force Feroceon L2 cache write through"
896         depends on CACHE_FEROCEON_L2
897         help
898           Say Y here to use the Feroceon L2 cache in writethrough mode.
899           Unless you specifically require this, say N for writeback mode.
900 
901 config MIGHT_HAVE_CACHE_L2X0
902         bool
903         help
904           This option should be selected by machines which have a L2x0
905           or PL310 cache controller, but where its use is optional.
906 
907           The only effect of this option is to make CACHE_L2X0 and
908           related options available to the user for configuration.
909 
910           Boards or SoCs which always require the cache controller
911           support to be present should select CACHE_L2X0 directly
912           instead of this option, thus preventing the user from
913           inadvertently configuring a broken kernel.
914 
915 config CACHE_L2X0
916         bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
917         default MIGHT_HAVE_CACHE_L2X0
918         select OUTER_CACHE
919         select OUTER_CACHE_SYNC
920         help
921           This option enables the L2x0 PrimeCell.
922 
923 config CACHE_L2X0_PMU
924         bool "L2x0 performance monitor support" if CACHE_L2X0
925         depends on PERF_EVENTS
926         help
927           This option enables support for the performance monitoring features
928           of the L220 and PL310 outer cache controllers.
929 
930 if CACHE_L2X0
931 
932 config PL310_ERRATA_588369
933         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
934         help
935            The PL310 L2 cache controller implements three types of Clean &
936            Invalidate maintenance operations: by Physical Address
937            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
938            They are architecturally defined to behave as the execution of a
939            clean operation followed immediately by an invalidate operation,
940            both performing to the same memory location. This functionality
941            is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
942            as clean lines are not invalidated as a result of these operations.
943 
944 config PL310_ERRATA_727915
945         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
946         help
947           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
948           operation (offset 0x7FC). This operation runs in background so that
949           PL310 can handle normal accesses while it is in progress. Under very
950           rare circumstances, due to this erratum, write data can be lost when
951           PL310 treats a cacheable write transaction during a Clean &
952           Invalidate by Way operation.  Revisions prior to r3p1 are affected by
953           this errata (fixed in r3p1).
954 
955 config PL310_ERRATA_753970
956         bool "PL310 errata: cache sync operation may be faulty"
957         help
958           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
959 
960           Under some condition the effect of cache sync operation on
961           the store buffer still remains when the operation completes.
962           This means that the store buffer is always asked to drain and
963           this prevents it from merging any further writes. The workaround
964           is to replace the normal offset of cache sync operation (0x730)
965           by another offset targeting an unmapped PL310 register 0x740.
966           This has the same effect as the cache sync operation: store buffer
967           drain and waiting for all buffers empty.
968 
969 config PL310_ERRATA_769419
970         bool "PL310 errata: no automatic Store Buffer drain"
971         help
972           On revisions of the PL310 prior to r3p2, the Store Buffer does
973           not automatically drain. This can cause normal, non-cacheable
974           writes to be retained when the memory system is idle, leading
975           to suboptimal I/O performance for drivers using coherent DMA.
976           This option adds a write barrier to the cpu_idle loop so that,
977           on systems with an outer cache, the store buffer is drained
978           explicitly.
979 
980 endif
981 
982 config CACHE_TAUROS2
983         bool "Enable the Tauros2 L2 cache controller"
984         depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
985         default y
986         select OUTER_CACHE
987         help
988           This option enables the Tauros2 L2 cache controller (as
989           found on PJ1/PJ4).
990 
991 config CACHE_UNIPHIER
992         bool "Enable the UniPhier outer cache controller"
993         depends on ARCH_UNIPHIER
994         select ARM_L1_CACHE_SHIFT_7
995         select OUTER_CACHE
996         select OUTER_CACHE_SYNC
997         help
998           This option enables the UniPhier outer cache (system cache)
999           controller.
1000 
1001 config CACHE_XSC3L2
1002         bool "Enable the L2 cache on XScale3"
1003         depends on CPU_XSC3
1004         default y
1005         select OUTER_CACHE
1006         help
1007           This option enables the L2 cache on XScale3.
1008 
1009 config ARM_L1_CACHE_SHIFT_6
1010         bool
1011         default y if CPU_V7
1012         help
1013           Setting ARM L1 cache line size to 64 Bytes.
1014 
1015 config ARM_L1_CACHE_SHIFT_7
1016         bool
1017         help
1018           Setting ARM L1 cache line size to 128 Bytes.
1019 
1020 config ARM_L1_CACHE_SHIFT
1021         int
1022         default 7 if ARM_L1_CACHE_SHIFT_7
1023         default 6 if ARM_L1_CACHE_SHIFT_6
1024         default 5
1025 
1026 config ARM_DMA_MEM_BUFFERABLE
1027         bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
1028         default y if CPU_V6 || CPU_V6K || CPU_V7
1029         help
1030           Historically, the kernel has used strongly ordered mappings to
1031           provide DMA coherent memory.  With the advent of ARMv7, mapping
1032           memory with differing types results in unpredictable behaviour,
1033           so on these CPUs, this option is forced on.
1034 
1035           Multiple mappings with differing attributes is also unpredictable
1036           on ARMv6 CPUs, but since they do not have aggressive speculative
1037           prefetch, no harm appears to occur.
1038 
1039           However, drivers may be missing the necessary barriers for ARMv6,
1040           and therefore turning this on may result in unpredictable driver
1041           behaviour.  Therefore, we offer this as an option.
1042 
1043           You are recommended say 'Y' here and debug any affected drivers.
1044 
1045 config ARM_HEAVY_MB
1046         bool
1047 
1048 config ARCH_SUPPORTS_BIG_ENDIAN
1049         bool
1050         help
1051           This option specifies the architecture can support big endian
1052           operation.
1053 
1054 config DEBUG_RODATA
1055         bool "Make kernel text and rodata read-only"
1056         depends on MMU && !XIP_KERNEL
1057         default y if CPU_V7
1058         help
1059           If this is set, kernel text and rodata memory will be made
1060           read-only, and non-text kernel memory will be made non-executable.
1061           The tradeoff is that each region is padded to section-size (1MiB)
1062           boundaries (because their permissions are different and splitting
1063           the 1M pages into 4K ones causes TLB performance problems), which
1064           can waste memory.
1065 
1066 config DEBUG_ALIGN_RODATA
1067         bool "Make rodata strictly non-executable"
1068         depends on DEBUG_RODATA
1069         default y
1070         help
1071           If this is set, rodata will be made explicitly non-executable. This
1072           provides protection on the rare chance that attackers might find and
1073           use ROP gadgets that exist in the rodata section. This adds an
1074           additional section-aligned split of rodata from kernel text so it
1075           can be made explicitly non-executable. This padding may waste memory
1076           space to gain the additional protection.

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