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Linux/arch/arm/mm/Kconfig

  1 comment "Processor Type"
  2 
  3 # Select CPU types depending on the architecture selected.  This selects
  4 # which CPUs we support in the kernel image, and the compiler instruction
  5 # optimiser behaviour.
  6 
  7 # ARM7TDMI
  8 config CPU_ARM7TDMI
  9         bool "Support ARM7TDMI processor"
 10         depends on !MMU
 11         select CPU_32v4T
 12         select CPU_ABRT_LV4T
 13         select CPU_CACHE_V4
 14         select CPU_PABRT_LEGACY
 15         help
 16           A 32-bit RISC microprocessor based on the ARM7 processor core
 17           which has no memory control unit and cache.
 18 
 19           Say Y if you want support for the ARM7TDMI processor.
 20           Otherwise, say N.
 21 
 22 # ARM720T
 23 config CPU_ARM720T
 24         bool "Support ARM720T processor" if ARCH_INTEGRATOR
 25         select CPU_32v4T
 26         select CPU_ABRT_LV4T
 27         select CPU_CACHE_V4
 28         select CPU_CACHE_VIVT
 29         select CPU_COPY_V4WT if MMU
 30         select CPU_CP15_MMU
 31         select CPU_PABRT_LEGACY
 32         select CPU_TLB_V4WT if MMU
 33         help
 34           A 32-bit RISC processor with 8kByte Cache, Write Buffer and
 35           MMU built around an ARM7TDMI core.
 36 
 37           Say Y if you want support for the ARM720T processor.
 38           Otherwise, say N.
 39 
 40 # ARM740T
 41 config CPU_ARM740T
 42         bool "Support ARM740T processor" if ARCH_INTEGRATOR
 43         depends on !MMU
 44         select CPU_32v4T
 45         select CPU_ABRT_LV4T
 46         select CPU_CACHE_V4
 47         select CPU_CP15_MPU
 48         select CPU_PABRT_LEGACY
 49         help
 50           A 32-bit RISC processor with 8KB cache or 4KB variants,
 51           write buffer and MPU(Protection Unit) built around
 52           an ARM7TDMI core.
 53 
 54           Say Y if you want support for the ARM740T processor.
 55           Otherwise, say N.
 56 
 57 # ARM9TDMI
 58 config CPU_ARM9TDMI
 59         bool "Support ARM9TDMI processor"
 60         depends on !MMU
 61         select CPU_32v4T
 62         select CPU_ABRT_NOMMU
 63         select CPU_CACHE_V4
 64         select CPU_PABRT_LEGACY
 65         help
 66           A 32-bit RISC microprocessor based on the ARM9 processor core
 67           which has no memory control unit and cache.
 68 
 69           Say Y if you want support for the ARM9TDMI processor.
 70           Otherwise, say N.
 71 
 72 # ARM920T
 73 config CPU_ARM920T
 74         bool "Support ARM920T processor" if ARCH_INTEGRATOR
 75         select CPU_32v4T
 76         select CPU_ABRT_EV4T
 77         select CPU_CACHE_V4WT
 78         select CPU_CACHE_VIVT
 79         select CPU_COPY_V4WB if MMU
 80         select CPU_CP15_MMU
 81         select CPU_PABRT_LEGACY
 82         select CPU_TLB_V4WBI if MMU
 83         help
 84           The ARM920T is licensed to be produced by numerous vendors,
 85           and is used in the Cirrus EP93xx and the Samsung S3C2410.
 86 
 87           Say Y if you want support for the ARM920T processor.
 88           Otherwise, say N.
 89 
 90 # ARM922T
 91 config CPU_ARM922T
 92         bool "Support ARM922T processor" if ARCH_INTEGRATOR
 93         select CPU_32v4T
 94         select CPU_ABRT_EV4T
 95         select CPU_CACHE_V4WT
 96         select CPU_CACHE_VIVT
 97         select CPU_COPY_V4WB if MMU
 98         select CPU_CP15_MMU
 99         select CPU_PABRT_LEGACY
100         select CPU_TLB_V4WBI if MMU
101         help
102           The ARM922T is a version of the ARM920T, but with smaller
103           instruction and data caches. It is used in Altera's
104           Excalibur XA device family and Micrel's KS8695 Centaur.
105 
106           Say Y if you want support for the ARM922T processor.
107           Otherwise, say N.
108 
109 # ARM925T
110 config CPU_ARM925T
111         bool "Support ARM925T processor" if ARCH_OMAP1
112         select CPU_32v4T
113         select CPU_ABRT_EV4T
114         select CPU_CACHE_V4WT
115         select CPU_CACHE_VIVT
116         select CPU_COPY_V4WB if MMU
117         select CPU_CP15_MMU
118         select CPU_PABRT_LEGACY
119         select CPU_TLB_V4WBI if MMU
120         help
121           The ARM925T is a mix between the ARM920T and ARM926T, but with
122           different instruction and data caches. It is used in TI's OMAP
123           device family.
124 
125           Say Y if you want support for the ARM925T processor.
126           Otherwise, say N.
127 
128 # ARM926T
129 config CPU_ARM926T
130         bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB
131         select CPU_32v5
132         select CPU_ABRT_EV5TJ
133         select CPU_CACHE_VIVT
134         select CPU_COPY_V4WB if MMU
135         select CPU_CP15_MMU
136         select CPU_PABRT_LEGACY
137         select CPU_TLB_V4WBI if MMU
138         help
139           This is a variant of the ARM920.  It has slightly different
140           instruction sequences for cache and TLB operations.  Curiously,
141           there is no documentation on it at the ARM corporate website.
142 
143           Say Y if you want support for the ARM926T processor.
144           Otherwise, say N.
145 
146 # FA526
147 config CPU_FA526
148         bool
149         select CPU_32v4
150         select CPU_ABRT_EV4
151         select CPU_CACHE_FA
152         select CPU_CACHE_VIVT
153         select CPU_COPY_FA if MMU
154         select CPU_CP15_MMU
155         select CPU_PABRT_LEGACY
156         select CPU_TLB_FA if MMU
157         help
158           The FA526 is a version of the ARMv4 compatible processor with
159           Branch Target Buffer, Unified TLB and cache line size 16.
160 
161           Say Y if you want support for the FA526 processor.
162           Otherwise, say N.
163 
164 # ARM940T
165 config CPU_ARM940T
166         bool "Support ARM940T processor" if ARCH_INTEGRATOR
167         depends on !MMU
168         select CPU_32v4T
169         select CPU_ABRT_NOMMU
170         select CPU_CACHE_VIVT
171         select CPU_CP15_MPU
172         select CPU_PABRT_LEGACY
173         help
174           ARM940T is a member of the ARM9TDMI family of general-
175           purpose microprocessors with MPU and separate 4KB
176           instruction and 4KB data cases, each with a 4-word line
177           length.
178 
179           Say Y if you want support for the ARM940T processor.
180           Otherwise, say N.
181 
182 # ARM946E-S
183 config CPU_ARM946E
184         bool "Support ARM946E-S processor" if ARCH_INTEGRATOR
185         depends on !MMU
186         select CPU_32v5
187         select CPU_ABRT_NOMMU
188         select CPU_CACHE_VIVT
189         select CPU_CP15_MPU
190         select CPU_PABRT_LEGACY
191         help
192           ARM946E-S is a member of the ARM9E-S family of high-
193           performance, 32-bit system-on-chip processor solutions.
194           The TCM and ARMv5TE 32-bit instruction set is supported.
195 
196           Say Y if you want support for the ARM946E-S processor.
197           Otherwise, say N.
198 
199 # ARM1020 - needs validating
200 config CPU_ARM1020
201         bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR
202         select CPU_32v5
203         select CPU_ABRT_EV4T
204         select CPU_CACHE_V4WT
205         select CPU_CACHE_VIVT
206         select CPU_COPY_V4WB if MMU
207         select CPU_CP15_MMU
208         select CPU_PABRT_LEGACY
209         select CPU_TLB_V4WBI if MMU
210         help
211           The ARM1020 is the 32K cached version of the ARM10 processor,
212           with an addition of a floating-point unit.
213 
214           Say Y if you want support for the ARM1020 processor.
215           Otherwise, say N.
216 
217 # ARM1020E - needs validating
218 config CPU_ARM1020E
219         bool "Support ARM1020E processor" if ARCH_INTEGRATOR
220         depends on n
221         select CPU_32v5
222         select CPU_ABRT_EV4T
223         select CPU_CACHE_V4WT
224         select CPU_CACHE_VIVT
225         select CPU_COPY_V4WB if MMU
226         select CPU_CP15_MMU
227         select CPU_PABRT_LEGACY
228         select CPU_TLB_V4WBI if MMU
229 
230 # ARM1022E
231 config CPU_ARM1022
232         bool "Support ARM1022E processor" if ARCH_INTEGRATOR
233         select CPU_32v5
234         select CPU_ABRT_EV4T
235         select CPU_CACHE_VIVT
236         select CPU_COPY_V4WB if MMU # can probably do better
237         select CPU_CP15_MMU
238         select CPU_PABRT_LEGACY
239         select CPU_TLB_V4WBI if MMU
240         help
241           The ARM1022E is an implementation of the ARMv5TE architecture
242           based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
243           embedded trace macrocell, and a floating-point unit.
244 
245           Say Y if you want support for the ARM1022E processor.
246           Otherwise, say N.
247 
248 # ARM1026EJ-S
249 config CPU_ARM1026
250         bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR
251         select CPU_32v5
252         select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
253         select CPU_CACHE_VIVT
254         select CPU_COPY_V4WB if MMU # can probably do better
255         select CPU_CP15_MMU
256         select CPU_PABRT_LEGACY
257         select CPU_TLB_V4WBI if MMU
258         help
259           The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
260           based upon the ARM10 integer core.
261 
262           Say Y if you want support for the ARM1026EJ-S processor.
263           Otherwise, say N.
264 
265 # SA110
266 config CPU_SA110
267         bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC
268         select CPU_32v3 if ARCH_RPC
269         select CPU_32v4 if !ARCH_RPC
270         select CPU_ABRT_EV4
271         select CPU_CACHE_V4WB
272         select CPU_CACHE_VIVT
273         select CPU_COPY_V4WB if MMU
274         select CPU_CP15_MMU
275         select CPU_PABRT_LEGACY
276         select CPU_TLB_V4WB if MMU
277         help
278           The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
279           is available at five speeds ranging from 100 MHz to 233 MHz.
280           More information is available at
281           <http://developer.intel.com/design/strong/sa110.htm>.
282 
283           Say Y if you want support for the SA-110 processor.
284           Otherwise, say N.
285 
286 # SA1100
287 config CPU_SA1100
288         bool
289         select CPU_32v4
290         select CPU_ABRT_EV4
291         select CPU_CACHE_V4WB
292         select CPU_CACHE_VIVT
293         select CPU_CP15_MMU
294         select CPU_PABRT_LEGACY
295         select CPU_TLB_V4WB if MMU
296 
297 # XScale
298 config CPU_XSCALE
299         bool
300         select CPU_32v5
301         select CPU_ABRT_EV5T
302         select CPU_CACHE_VIVT
303         select CPU_CP15_MMU
304         select CPU_PABRT_LEGACY
305         select CPU_TLB_V4WBI if MMU
306 
307 # XScale Core Version 3
308 config CPU_XSC3
309         bool
310         select CPU_32v5
311         select CPU_ABRT_EV5T
312         select CPU_CACHE_VIVT
313         select CPU_CP15_MMU
314         select CPU_PABRT_LEGACY
315         select CPU_TLB_V4WBI if MMU
316         select IO_36
317 
318 # Marvell PJ1 (Mohawk)
319 config CPU_MOHAWK
320         bool
321         select CPU_32v5
322         select CPU_ABRT_EV5T
323         select CPU_CACHE_VIVT
324         select CPU_COPY_V4WB if MMU
325         select CPU_CP15_MMU
326         select CPU_PABRT_LEGACY
327         select CPU_TLB_V4WBI if MMU
328 
329 # Feroceon
330 config CPU_FEROCEON
331         bool
332         select CPU_32v5
333         select CPU_ABRT_EV5T
334         select CPU_CACHE_VIVT
335         select CPU_COPY_FEROCEON if MMU
336         select CPU_CP15_MMU
337         select CPU_PABRT_LEGACY
338         select CPU_TLB_FEROCEON if MMU
339 
340 config CPU_FEROCEON_OLD_ID
341         bool "Accept early Feroceon cores with an ARM926 ID"
342         depends on CPU_FEROCEON && !CPU_ARM926T
343         default y
344         help
345           This enables the usage of some old Feroceon cores
346           for which the CPU ID is equal to the ARM926 ID.
347           Relevant for Feroceon-1850 and early Feroceon-2850.
348 
349 # Marvell PJ4
350 config CPU_PJ4
351         bool
352         select ARM_THUMBEE
353         select CPU_V7
354 
355 config CPU_PJ4B
356         bool
357         select CPU_V7
358 
359 # ARMv6
360 config CPU_V6
361         bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
362         select CPU_32v6
363         select CPU_ABRT_EV6
364         select CPU_CACHE_V6
365         select CPU_CACHE_VIPT
366         select CPU_COPY_V6 if MMU
367         select CPU_CP15_MMU
368         select CPU_HAS_ASID if MMU
369         select CPU_PABRT_V6
370         select CPU_TLB_V6 if MMU
371 
372 # ARMv6k
373 config CPU_V6K
374         bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
375         select CPU_32v6
376         select CPU_32v6K
377         select CPU_ABRT_EV6
378         select CPU_CACHE_V6
379         select CPU_CACHE_VIPT
380         select CPU_COPY_V6 if MMU
381         select CPU_CP15_MMU
382         select CPU_HAS_ASID if MMU
383         select CPU_PABRT_V6
384         select CPU_TLB_V6 if MMU
385 
386 # ARMv7
387 config CPU_V7
388         bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX
389         select CPU_32v6K
390         select CPU_32v7
391         select CPU_ABRT_EV7
392         select CPU_CACHE_V7
393         select CPU_CACHE_VIPT
394         select CPU_COPY_V6 if MMU
395         select CPU_CP15_MMU if MMU
396         select CPU_CP15_MPU if !MMU
397         select CPU_HAS_ASID if MMU
398         select CPU_PABRT_V7
399         select CPU_TLB_V7 if MMU
400 
401 # ARMv7M
402 config CPU_V7M
403         bool
404         select CPU_32v7M
405         select CPU_ABRT_NOMMU
406         select CPU_CACHE_NOP
407         select CPU_PABRT_LEGACY
408         select CPU_THUMBONLY
409 
410 config CPU_THUMBONLY
411         bool
412         # There are no CPUs available with MMU that don't implement an ARM ISA:
413         depends on !MMU
414         help
415           Select this if your CPU doesn't support the 32 bit ARM instructions.
416 
417 # Figure out what processor architecture version we should be using.
418 # This defines the compiler instruction set which depends on the machine type.
419 config CPU_32v3
420         bool
421         select CPU_USE_DOMAINS if MMU
422         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
423         select TLS_REG_EMUL if SMP || !MMU
424         select NEED_KUSER_HELPERS
425 
426 config CPU_32v4
427         bool
428         select CPU_USE_DOMAINS if MMU
429         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
430         select TLS_REG_EMUL if SMP || !MMU
431         select NEED_KUSER_HELPERS
432 
433 config CPU_32v4T
434         bool
435         select CPU_USE_DOMAINS if MMU
436         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
437         select TLS_REG_EMUL if SMP || !MMU
438         select NEED_KUSER_HELPERS
439 
440 config CPU_32v5
441         bool
442         select CPU_USE_DOMAINS if MMU
443         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
444         select TLS_REG_EMUL if SMP || !MMU
445         select NEED_KUSER_HELPERS
446 
447 config CPU_32v6
448         bool
449         select CPU_USE_DOMAINS if CPU_V6 && MMU
450         select TLS_REG_EMUL if !CPU_32v6K && !MMU
451 
452 config CPU_32v6K
453         bool
454 
455 config CPU_32v7
456         bool
457 
458 config CPU_32v7M
459         bool
460 
461 # The abort model
462 config CPU_ABRT_NOMMU
463         bool
464 
465 config CPU_ABRT_EV4
466         bool
467 
468 config CPU_ABRT_EV4T
469         bool
470 
471 config CPU_ABRT_LV4T
472         bool
473 
474 config CPU_ABRT_EV5T
475         bool
476 
477 config CPU_ABRT_EV5TJ
478         bool
479 
480 config CPU_ABRT_EV6
481         bool
482 
483 config CPU_ABRT_EV7
484         bool
485 
486 config CPU_PABRT_LEGACY
487         bool
488 
489 config CPU_PABRT_V6
490         bool
491 
492 config CPU_PABRT_V7
493         bool
494 
495 # The cache model
496 config CPU_CACHE_V4
497         bool
498 
499 config CPU_CACHE_V4WT
500         bool
501 
502 config CPU_CACHE_V4WB
503         bool
504 
505 config CPU_CACHE_V6
506         bool
507 
508 config CPU_CACHE_V7
509         bool
510 
511 config CPU_CACHE_NOP
512         bool
513 
514 config CPU_CACHE_VIVT
515         bool
516 
517 config CPU_CACHE_VIPT
518         bool
519 
520 config CPU_CACHE_FA
521         bool
522 
523 if MMU
524 # The copy-page model
525 config CPU_COPY_V4WT
526         bool
527 
528 config CPU_COPY_V4WB
529         bool
530 
531 config CPU_COPY_FEROCEON
532         bool
533 
534 config CPU_COPY_FA
535         bool
536 
537 config CPU_COPY_V6
538         bool
539 
540 # This selects the TLB model
541 config CPU_TLB_V4WT
542         bool
543         help
544           ARM Architecture Version 4 TLB with writethrough cache.
545 
546 config CPU_TLB_V4WB
547         bool
548         help
549           ARM Architecture Version 4 TLB with writeback cache.
550 
551 config CPU_TLB_V4WBI
552         bool
553         help
554           ARM Architecture Version 4 TLB with writeback cache and invalidate
555           instruction cache entry.
556 
557 config CPU_TLB_FEROCEON
558         bool
559         help
560           Feroceon TLB (v4wbi with non-outer-cachable page table walks).
561 
562 config CPU_TLB_FA
563         bool
564         help
565           Faraday ARM FA526 architecture, unified TLB with writeback cache
566           and invalidate instruction cache entry. Branch target buffer is
567           also supported.
568 
569 config CPU_TLB_V6
570         bool
571 
572 config CPU_TLB_V7
573         bool
574 
575 config VERIFY_PERMISSION_FAULT
576         bool
577 endif
578 
579 config CPU_HAS_ASID
580         bool
581         help
582           This indicates whether the CPU has the ASID register; used to
583           tag TLB and possibly cache entries.
584 
585 config CPU_CP15
586         bool
587         help
588           Processor has the CP15 register.
589 
590 config CPU_CP15_MMU
591         bool
592         select CPU_CP15
593         help
594           Processor has the CP15 register, which has MMU related registers.
595 
596 config CPU_CP15_MPU
597         bool
598         select CPU_CP15
599         help
600           Processor has the CP15 register, which has MPU related registers.
601 
602 config CPU_USE_DOMAINS
603         bool
604         help
605           This option enables or disables the use of domain switching
606           via the set_fs() function.
607 
608 #
609 # CPU supports 36-bit I/O
610 #
611 config IO_36
612         bool
613 
614 comment "Processor Features"
615 
616 config ARM_LPAE
617         bool "Support for the Large Physical Address Extension"
618         depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
619                 !CPU_32v4 && !CPU_32v3
620         help
621           Say Y if you have an ARMv7 processor supporting the LPAE page
622           table format and you would like to access memory beyond the
623           4GB limit. The resulting kernel image will not run on
624           processors without the LPA extension.
625 
626           If unsure, say N.
627 
628 config ARCH_PHYS_ADDR_T_64BIT
629         def_bool ARM_LPAE
630 
631 config ARCH_DMA_ADDR_T_64BIT
632         bool
633 
634 config ARM_THUMB
635         bool "Support Thumb user binaries" if !CPU_THUMBONLY
636         depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \
637                 CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \
638                 CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
639                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \
640                 CPU_V7 || CPU_FEROCEON || CPU_V7M
641         default y
642         help
643           Say Y if you want to include kernel support for running user space
644           Thumb binaries.
645 
646           The Thumb instruction set is a compressed form of the standard ARM
647           instruction set resulting in smaller binaries at the expense of
648           slightly less efficient code.
649 
650           If you don't know what this all is, saying Y is a safe choice.
651 
652 config ARM_THUMBEE
653         bool "Enable ThumbEE CPU extension"
654         depends on CPU_V7
655         help
656           Say Y here if you have a CPU with the ThumbEE extension and code to
657           make use of it. Say N for code that can run on CPUs without ThumbEE.
658 
659 config ARM_VIRT_EXT
660         bool
661         depends on MMU
662         default y if CPU_V7
663         help
664           Enable the kernel to make use of the ARM Virtualization
665           Extensions to install hypervisors without run-time firmware
666           assistance.
667 
668           A compliant bootloader is required in order to make maximum
669           use of this feature.  Refer to Documentation/arm/Booting for
670           details.
671 
672 config SWP_EMULATE
673         bool "Emulate SWP/SWPB instructions"
674         depends on !CPU_USE_DOMAINS && CPU_V7
675         default y if SMP
676         select HAVE_PROC_CPU if PROC_FS
677         help
678           ARMv6 architecture deprecates use of the SWP/SWPB instructions.
679           ARMv7 multiprocessing extensions introduce the ability to disable
680           these instructions, triggering an undefined instruction exception
681           when executed. Say Y here to enable software emulation of these
682           instructions for userspace (not kernel) using LDREX/STREX.
683           Also creates /proc/cpu/swp_emulation for statistics.
684 
685           In some older versions of glibc [<=2.8] SWP is used during futex
686           trylock() operations with the assumption that the code will not
687           be preempted. This invalid assumption may be more likely to fail
688           with SWP emulation enabled, leading to deadlock of the user
689           application.
690 
691           NOTE: when accessing uncached shared regions, LDREX/STREX rely
692           on an external transaction monitoring block called a global
693           monitor to maintain update atomicity. If your system does not
694           implement a global monitor, this option can cause programs that
695           perform SWP operations to uncached memory to deadlock.
696 
697           If unsure, say Y.
698 
699 config CPU_BIG_ENDIAN
700         bool "Build big-endian kernel"
701         depends on ARCH_SUPPORTS_BIG_ENDIAN
702         help
703           Say Y if you plan on running a kernel in big-endian mode.
704           Note that your board must be properly built and your board
705           port must properly enable any big-endian related features
706           of your chipset/board/processor.
707 
708 config CPU_ENDIAN_BE8
709         bool
710         depends on CPU_BIG_ENDIAN
711         default CPU_V6 || CPU_V6K || CPU_V7
712         help
713           Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
714 
715 config CPU_ENDIAN_BE32
716         bool
717         depends on CPU_BIG_ENDIAN
718         default !CPU_ENDIAN_BE8
719         help
720           Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
721 
722 config CPU_HIGH_VECTOR
723         depends on !MMU && CPU_CP15 && !CPU_ARM740T
724         bool "Select the High exception vector"
725         help
726           Say Y here to select high exception vector(0xFFFF0000~).
727           The exception vector can vary depending on the platform
728           design in nommu mode. If your platform needs to select
729           high exception vector, say Y.
730           Otherwise or if you are unsure, say N, and the low exception
731           vector (0x00000000~) will be used.
732 
733 config CPU_ICACHE_DISABLE
734         bool "Disable I-Cache (I-bit)"
735         depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
736         help
737           Say Y here to disable the processor instruction cache. Unless
738           you have a reason not to or are unsure, say N.
739 
740 config CPU_DCACHE_DISABLE
741         bool "Disable D-Cache (C-bit)"
742         depends on CPU_CP15
743         help
744           Say Y here to disable the processor data cache. Unless
745           you have a reason not to or are unsure, say N.
746 
747 config CPU_DCACHE_SIZE
748         hex
749         depends on CPU_ARM740T || CPU_ARM946E
750         default 0x00001000 if CPU_ARM740T
751         default 0x00002000 # default size for ARM946E-S
752         help
753           Some cores are synthesizable to have various sized cache. For
754           ARM946E-S case, it can vary from 0KB to 1MB.
755           To support such cache operations, it is efficient to know the size
756           before compile time.
757           If your SoC is configured to have a different size, define the value
758           here with proper conditions.
759 
760 config CPU_DCACHE_WRITETHROUGH
761         bool "Force write through D-cache"
762         depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
763         default y if CPU_ARM925T
764         help
765           Say Y here to use the data cache in writethrough mode. Unless you
766           specifically require this or are unsure, say N.
767 
768 config CPU_CACHE_ROUND_ROBIN
769         bool "Round robin I and D cache replacement algorithm"
770         depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
771         help
772           Say Y here to use the predictable round-robin cache replacement
773           policy.  Unless you specifically require this or are unsure, say N.
774 
775 config CPU_BPREDICT_DISABLE
776         bool "Disable branch prediction"
777         depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
778         help
779           Say Y here to disable branch prediction.  If unsure, say N.
780 
781 config TLS_REG_EMUL
782         bool
783         select NEED_KUSER_HELPERS
784         help
785           An SMP system using a pre-ARMv6 processor (there are apparently
786           a few prototypes like that in existence) and therefore access to
787           that required register must be emulated.
788 
789 config NEEDS_SYSCALL_FOR_CMPXCHG
790         bool
791         select NEED_KUSER_HELPERS
792         help
793           SMP on a pre-ARMv6 processor?  Well OK then.
794           Forget about fast user space cmpxchg support.
795           It is just not possible.
796 
797 config NEED_KUSER_HELPERS
798         bool
799 
800 config KUSER_HELPERS
801         bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
802         default y
803         help
804           Warning: disabling this option may break user programs.
805 
806           Provide kuser helpers in the vector page.  The kernel provides
807           helper code to userspace in read only form at a fixed location
808           in the high vector page to allow userspace to be independent of
809           the CPU type fitted to the system.  This permits binaries to be
810           run on ARMv4 through to ARMv7 without modification.
811 
812           See Documentation/arm/kernel_user_helpers.txt for details.
813 
814           However, the fixed address nature of these helpers can be used
815           by ROP (return orientated programming) authors when creating
816           exploits.
817 
818           If all of the binaries and libraries which run on your platform
819           are built specifically for your platform, and make no use of
820           these helpers, then you can turn this option off to hinder
821           such exploits. However, in that case, if a binary or library
822           relying on those helpers is run, it will receive a SIGILL signal,
823           which will terminate the program.
824 
825           Say N here only if you are absolutely certain that you do not
826           need these helpers; otherwise, the safe option is to say Y.
827 
828 config DMA_CACHE_RWFO
829         bool "Enable read/write for ownership DMA cache maintenance"
830         depends on CPU_V6K && SMP
831         default y
832         help
833           The Snoop Control Unit on ARM11MPCore does not detect the
834           cache maintenance operations and the dma_{map,unmap}_area()
835           functions may leave stale cache entries on other CPUs. By
836           enabling this option, Read or Write For Ownership in the ARMv6
837           DMA cache maintenance functions is performed. These LDR/STR
838           instructions change the cache line state to shared or modified
839           so that the cache operation has the desired effect.
840 
841           Note that the workaround is only valid on processors that do
842           not perform speculative loads into the D-cache. For such
843           processors, if cache maintenance operations are not broadcast
844           in hardware, other workarounds are needed (e.g. cache
845           maintenance broadcasting in software via FIQ).
846 
847 config OUTER_CACHE
848         bool
849 
850 config OUTER_CACHE_SYNC
851         bool
852         help
853           The outer cache has a outer_cache_fns.sync function pointer
854           that can be used to drain the write buffer of the outer cache.
855 
856 config CACHE_FEROCEON_L2
857         bool "Enable the Feroceon L2 cache controller"
858         depends on ARCH_KIRKWOOD || ARCH_MV78XX0
859         default y
860         select OUTER_CACHE
861         help
862           This option enables the Feroceon L2 cache controller.
863 
864 config CACHE_FEROCEON_L2_WRITETHROUGH
865         bool "Force Feroceon L2 cache write through"
866         depends on CACHE_FEROCEON_L2
867         help
868           Say Y here to use the Feroceon L2 cache in writethrough mode.
869           Unless you specifically require this, say N for writeback mode.
870 
871 config MIGHT_HAVE_CACHE_L2X0
872         bool
873         help
874           This option should be selected by machines which have a L2x0
875           or PL310 cache controller, but where its use is optional.
876 
877           The only effect of this option is to make CACHE_L2X0 and
878           related options available to the user for configuration.
879 
880           Boards or SoCs which always require the cache controller
881           support to be present should select CACHE_L2X0 directly
882           instead of this option, thus preventing the user from
883           inadvertently configuring a broken kernel.
884 
885 config CACHE_L2X0
886         bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
887         default MIGHT_HAVE_CACHE_L2X0
888         select OUTER_CACHE
889         select OUTER_CACHE_SYNC
890         help
891           This option enables the L2x0 PrimeCell.
892 
893 config CACHE_PL310
894         bool
895         depends on CACHE_L2X0
896         default y if CPU_V7 && !(CPU_V6 || CPU_V6K)
897         help
898           This option enables optimisations for the PL310 cache
899           controller.
900 
901 config CACHE_TAUROS2
902         bool "Enable the Tauros2 L2 cache controller"
903         depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
904         default y
905         select OUTER_CACHE
906         help
907           This option enables the Tauros2 L2 cache controller (as
908           found on PJ1/PJ4).
909 
910 config CACHE_XSC3L2
911         bool "Enable the L2 cache on XScale3"
912         depends on CPU_XSC3
913         default y
914         select OUTER_CACHE
915         help
916           This option enables the L2 cache on XScale3.
917 
918 config ARM_L1_CACHE_SHIFT_6
919         bool
920         default y if CPU_V7
921         help
922           Setting ARM L1 cache line size to 64 Bytes.
923 
924 config ARM_L1_CACHE_SHIFT
925         int
926         default 6 if ARM_L1_CACHE_SHIFT_6
927         default 5
928 
929 config ARM_DMA_MEM_BUFFERABLE
930         bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
931         depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
932                      MACH_REALVIEW_PB11MP)
933         default y if CPU_V6 || CPU_V6K || CPU_V7
934         help
935           Historically, the kernel has used strongly ordered mappings to
936           provide DMA coherent memory.  With the advent of ARMv7, mapping
937           memory with differing types results in unpredictable behaviour,
938           so on these CPUs, this option is forced on.
939 
940           Multiple mappings with differing attributes is also unpredictable
941           on ARMv6 CPUs, but since they do not have aggressive speculative
942           prefetch, no harm appears to occur.
943 
944           However, drivers may be missing the necessary barriers for ARMv6,
945           and therefore turning this on may result in unpredictable driver
946           behaviour.  Therefore, we offer this as an option.
947 
948           You are recommended say 'Y' here and debug any affected drivers.
949 
950 config ARCH_HAS_BARRIERS
951         bool
952         help
953           This option allows the use of custom mandatory barriers
954           included via the mach/barriers.h file.
955 
956 config ARCH_SUPPORTS_BIG_ENDIAN
957         bool
958         help
959           This option specifies the architecture can support big endian
960           operation.

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