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Linux/arch/arm/mm/Kconfig

  1 comment "Processor Type"
  2 
  3 # Select CPU types depending on the architecture selected.  This selects
  4 # which CPUs we support in the kernel image, and the compiler instruction
  5 # optimiser behaviour.
  6 
  7 # ARM7TDMI
  8 config CPU_ARM7TDMI
  9         bool
 10         depends on !MMU
 11         select CPU_32v4T
 12         select CPU_ABRT_LV4T
 13         select CPU_CACHE_V4
 14         select CPU_PABRT_LEGACY
 15         help
 16           A 32-bit RISC microprocessor based on the ARM7 processor core
 17           which has no memory control unit and cache.
 18 
 19           Say Y if you want support for the ARM7TDMI processor.
 20           Otherwise, say N.
 21 
 22 # ARM720T
 23 config CPU_ARM720T
 24         bool "Support ARM720T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
 25         select CPU_32v4T
 26         select CPU_ABRT_LV4T
 27         select CPU_CACHE_V4
 28         select CPU_CACHE_VIVT
 29         select CPU_COPY_V4WT if MMU
 30         select CPU_CP15_MMU
 31         select CPU_PABRT_LEGACY
 32         select CPU_TLB_V4WT if MMU
 33         help
 34           A 32-bit RISC processor with 8kByte Cache, Write Buffer and
 35           MMU built around an ARM7TDMI core.
 36 
 37           Say Y if you want support for the ARM720T processor.
 38           Otherwise, say N.
 39 
 40 # ARM740T
 41 config CPU_ARM740T
 42         bool "Support ARM740T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
 43         depends on !MMU
 44         select CPU_32v4T
 45         select CPU_ABRT_LV4T
 46         select CPU_CACHE_V4
 47         select CPU_CP15_MPU
 48         select CPU_PABRT_LEGACY
 49         help
 50           A 32-bit RISC processor with 8KB cache or 4KB variants,
 51           write buffer and MPU(Protection Unit) built around
 52           an ARM7TDMI core.
 53 
 54           Say Y if you want support for the ARM740T processor.
 55           Otherwise, say N.
 56 
 57 # ARM9TDMI
 58 config CPU_ARM9TDMI
 59         bool
 60         depends on !MMU
 61         select CPU_32v4T
 62         select CPU_ABRT_NOMMU
 63         select CPU_CACHE_V4
 64         select CPU_PABRT_LEGACY
 65         help
 66           A 32-bit RISC microprocessor based on the ARM9 processor core
 67           which has no memory control unit and cache.
 68 
 69           Say Y if you want support for the ARM9TDMI processor.
 70           Otherwise, say N.
 71 
 72 # ARM920T
 73 config CPU_ARM920T
 74         bool "Support ARM920T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
 75         select CPU_32v4T
 76         select CPU_ABRT_EV4T
 77         select CPU_CACHE_V4WT
 78         select CPU_CACHE_VIVT
 79         select CPU_COPY_V4WB if MMU
 80         select CPU_CP15_MMU
 81         select CPU_PABRT_LEGACY
 82         select CPU_TLB_V4WBI if MMU
 83         help
 84           The ARM920T is licensed to be produced by numerous vendors,
 85           and is used in the Cirrus EP93xx and the Samsung S3C2410.
 86 
 87           Say Y if you want support for the ARM920T processor.
 88           Otherwise, say N.
 89 
 90 # ARM922T
 91 config CPU_ARM922T
 92         bool "Support ARM922T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
 93         select CPU_32v4T
 94         select CPU_ABRT_EV4T
 95         select CPU_CACHE_V4WT
 96         select CPU_CACHE_VIVT
 97         select CPU_COPY_V4WB if MMU
 98         select CPU_CP15_MMU
 99         select CPU_PABRT_LEGACY
100         select CPU_TLB_V4WBI if MMU
101         help
102           The ARM922T is a version of the ARM920T, but with smaller
103           instruction and data caches. It is used in Altera's
104           Excalibur XA device family and Micrel's KS8695 Centaur.
105 
106           Say Y if you want support for the ARM922T processor.
107           Otherwise, say N.
108 
109 # ARM925T
110 config CPU_ARM925T
111         bool "Support ARM925T processor" if ARCH_OMAP1
112         select CPU_32v4T
113         select CPU_ABRT_EV4T
114         select CPU_CACHE_V4WT
115         select CPU_CACHE_VIVT
116         select CPU_COPY_V4WB if MMU
117         select CPU_CP15_MMU
118         select CPU_PABRT_LEGACY
119         select CPU_TLB_V4WBI if MMU
120         help
121           The ARM925T is a mix between the ARM920T and ARM926T, but with
122           different instruction and data caches. It is used in TI's OMAP
123           device family.
124 
125           Say Y if you want support for the ARM925T processor.
126           Otherwise, say N.
127 
128 # ARM926T
129 config CPU_ARM926T
130         bool "Support ARM926T processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V5) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB)
131         select CPU_32v5
132         select CPU_ABRT_EV5TJ
133         select CPU_CACHE_VIVT
134         select CPU_COPY_V4WB if MMU
135         select CPU_CP15_MMU
136         select CPU_PABRT_LEGACY
137         select CPU_TLB_V4WBI if MMU
138         help
139           This is a variant of the ARM920.  It has slightly different
140           instruction sequences for cache and TLB operations.  Curiously,
141           there is no documentation on it at the ARM corporate website.
142 
143           Say Y if you want support for the ARM926T processor.
144           Otherwise, say N.
145 
146 # FA526
147 config CPU_FA526
148         bool
149         select CPU_32v4
150         select CPU_ABRT_EV4
151         select CPU_CACHE_FA
152         select CPU_CACHE_VIVT
153         select CPU_COPY_FA if MMU
154         select CPU_CP15_MMU
155         select CPU_PABRT_LEGACY
156         select CPU_TLB_FA if MMU
157         help
158           The FA526 is a version of the ARMv4 compatible processor with
159           Branch Target Buffer, Unified TLB and cache line size 16.
160 
161           Say Y if you want support for the FA526 processor.
162           Otherwise, say N.
163 
164 # ARM940T
165 config CPU_ARM940T
166         bool "Support ARM940T processor" if (ARCH_MULTI_V4T && ARCH_INTEGRATOR)
167         depends on !MMU
168         select CPU_32v4T
169         select CPU_ABRT_NOMMU
170         select CPU_CACHE_VIVT
171         select CPU_CP15_MPU
172         select CPU_PABRT_LEGACY
173         help
174           ARM940T is a member of the ARM9TDMI family of general-
175           purpose microprocessors with MPU and separate 4KB
176           instruction and 4KB data cases, each with a 4-word line
177           length.
178 
179           Say Y if you want support for the ARM940T processor.
180           Otherwise, say N.
181 
182 # ARM946E-S
183 config CPU_ARM946E
184         bool "Support ARM946E-S processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
185         depends on !MMU
186         select CPU_32v5
187         select CPU_ABRT_NOMMU
188         select CPU_CACHE_VIVT
189         select CPU_CP15_MPU
190         select CPU_PABRT_LEGACY
191         help
192           ARM946E-S is a member of the ARM9E-S family of high-
193           performance, 32-bit system-on-chip processor solutions.
194           The TCM and ARMv5TE 32-bit instruction set is supported.
195 
196           Say Y if you want support for the ARM946E-S processor.
197           Otherwise, say N.
198 
199 # ARM1020 - needs validating
200 config CPU_ARM1020
201         bool "Support ARM1020T (rev 0) processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
202         select CPU_32v5
203         select CPU_ABRT_EV4T
204         select CPU_CACHE_V4WT
205         select CPU_CACHE_VIVT
206         select CPU_COPY_V4WB if MMU
207         select CPU_CP15_MMU
208         select CPU_PABRT_LEGACY
209         select CPU_TLB_V4WBI if MMU
210         help
211           The ARM1020 is the 32K cached version of the ARM10 processor,
212           with an addition of a floating-point unit.
213 
214           Say Y if you want support for the ARM1020 processor.
215           Otherwise, say N.
216 
217 # ARM1020E - needs validating
218 config CPU_ARM1020E
219         bool "Support ARM1020E processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
220         depends on n
221         select CPU_32v5
222         select CPU_ABRT_EV4T
223         select CPU_CACHE_V4WT
224         select CPU_CACHE_VIVT
225         select CPU_COPY_V4WB if MMU
226         select CPU_CP15_MMU
227         select CPU_PABRT_LEGACY
228         select CPU_TLB_V4WBI if MMU
229 
230 # ARM1022E
231 config CPU_ARM1022
232         bool "Support ARM1022E processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
233         select CPU_32v5
234         select CPU_ABRT_EV4T
235         select CPU_CACHE_VIVT
236         select CPU_COPY_V4WB if MMU # can probably do better
237         select CPU_CP15_MMU
238         select CPU_PABRT_LEGACY
239         select CPU_TLB_V4WBI if MMU
240         help
241           The ARM1022E is an implementation of the ARMv5TE architecture
242           based upon the ARM10 integer core with a 16KiB L1 Harvard cache,
243           embedded trace macrocell, and a floating-point unit.
244 
245           Say Y if you want support for the ARM1022E processor.
246           Otherwise, say N.
247 
248 # ARM1026EJ-S
249 config CPU_ARM1026
250         bool "Support ARM1026EJ-S processor" if (ARCH_MULTI_V5 && ARCH_INTEGRATOR)
251         select CPU_32v5
252         select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10
253         select CPU_CACHE_VIVT
254         select CPU_COPY_V4WB if MMU # can probably do better
255         select CPU_CP15_MMU
256         select CPU_PABRT_LEGACY
257         select CPU_TLB_V4WBI if MMU
258         help
259           The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture
260           based upon the ARM10 integer core.
261 
262           Say Y if you want support for the ARM1026EJ-S processor.
263           Otherwise, say N.
264 
265 # SA110
266 config CPU_SA110
267         bool
268         select CPU_32v3 if ARCH_RPC
269         select CPU_32v4 if !ARCH_RPC
270         select CPU_ABRT_EV4
271         select CPU_CACHE_V4WB
272         select CPU_CACHE_VIVT
273         select CPU_COPY_V4WB if MMU
274         select CPU_CP15_MMU
275         select CPU_PABRT_LEGACY
276         select CPU_TLB_V4WB if MMU
277         help
278           The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and
279           is available at five speeds ranging from 100 MHz to 233 MHz.
280           More information is available at
281           <http://developer.intel.com/design/strong/sa110.htm>.
282 
283           Say Y if you want support for the SA-110 processor.
284           Otherwise, say N.
285 
286 # SA1100
287 config CPU_SA1100
288         bool
289         select CPU_32v4
290         select CPU_ABRT_EV4
291         select CPU_CACHE_V4WB
292         select CPU_CACHE_VIVT
293         select CPU_CP15_MMU
294         select CPU_PABRT_LEGACY
295         select CPU_TLB_V4WB if MMU
296 
297 # XScale
298 config CPU_XSCALE
299         bool
300         select CPU_32v5
301         select CPU_ABRT_EV5T
302         select CPU_CACHE_VIVT
303         select CPU_CP15_MMU
304         select CPU_PABRT_LEGACY
305         select CPU_TLB_V4WBI if MMU
306 
307 # XScale Core Version 3
308 config CPU_XSC3
309         bool
310         select CPU_32v5
311         select CPU_ABRT_EV5T
312         select CPU_CACHE_VIVT
313         select CPU_CP15_MMU
314         select CPU_PABRT_LEGACY
315         select CPU_TLB_V4WBI if MMU
316         select IO_36
317 
318 # Marvell PJ1 (Mohawk)
319 config CPU_MOHAWK
320         bool
321         select CPU_32v5
322         select CPU_ABRT_EV5T
323         select CPU_CACHE_VIVT
324         select CPU_COPY_V4WB if MMU
325         select CPU_CP15_MMU
326         select CPU_PABRT_LEGACY
327         select CPU_TLB_V4WBI if MMU
328 
329 # Feroceon
330 config CPU_FEROCEON
331         bool
332         select CPU_32v5
333         select CPU_ABRT_EV5T
334         select CPU_CACHE_VIVT
335         select CPU_COPY_FEROCEON if MMU
336         select CPU_CP15_MMU
337         select CPU_PABRT_LEGACY
338         select CPU_TLB_FEROCEON if MMU
339 
340 config CPU_FEROCEON_OLD_ID
341         bool "Accept early Feroceon cores with an ARM926 ID"
342         depends on CPU_FEROCEON && !CPU_ARM926T
343         default y
344         help
345           This enables the usage of some old Feroceon cores
346           for which the CPU ID is equal to the ARM926 ID.
347           Relevant for Feroceon-1850 and early Feroceon-2850.
348 
349 # Marvell PJ4
350 config CPU_PJ4
351         bool
352         select ARM_THUMBEE
353         select CPU_V7
354 
355 config CPU_PJ4B
356         bool
357         select CPU_V7
358 
359 # ARMv6
360 config CPU_V6
361         bool "Support ARM V6 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
362         select CPU_32v6
363         select CPU_ABRT_EV6
364         select CPU_CACHE_V6
365         select CPU_CACHE_VIPT
366         select CPU_COPY_V6 if MMU
367         select CPU_CP15_MMU
368         select CPU_HAS_ASID if MMU
369         select CPU_PABRT_V6
370         select CPU_TLB_V6 if MMU
371 
372 # ARMv6k
373 config CPU_V6K
374         bool "Support ARM V6K processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V6) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
375         select CPU_32v6
376         select CPU_32v6K
377         select CPU_ABRT_EV6
378         select CPU_CACHE_V6
379         select CPU_CACHE_VIPT
380         select CPU_COPY_V6 if MMU
381         select CPU_CP15_MMU
382         select CPU_HAS_ASID if MMU
383         select CPU_PABRT_V6
384         select CPU_TLB_V6 if MMU
385 
386 # ARMv7
387 config CPU_V7
388         bool "Support ARM V7 processor" if (!ARCH_MULTIPLATFORM || ARCH_MULTI_V7) && (ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX)
389         select CPU_32v6K
390         select CPU_32v7
391         select CPU_ABRT_EV7
392         select CPU_CACHE_V7
393         select CPU_CACHE_VIPT
394         select CPU_COPY_V6 if MMU
395         select CPU_CP15_MMU if MMU
396         select CPU_CP15_MPU if !MMU
397         select CPU_HAS_ASID if MMU
398         select CPU_PABRT_V7
399         select CPU_TLB_V7 if MMU
400 
401 # ARMv7M
402 config CPU_V7M
403         bool
404         select CPU_32v7M
405         select CPU_ABRT_NOMMU
406         select CPU_CACHE_NOP
407         select CPU_PABRT_LEGACY
408         select CPU_THUMBONLY
409 
410 config CPU_THUMBONLY
411         bool
412         # There are no CPUs available with MMU that don't implement an ARM ISA:
413         depends on !MMU
414         help
415           Select this if your CPU doesn't support the 32 bit ARM instructions.
416 
417 # Figure out what processor architecture version we should be using.
418 # This defines the compiler instruction set which depends on the machine type.
419 config CPU_32v3
420         bool
421         select CPU_USE_DOMAINS if MMU
422         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
423         select NEED_KUSER_HELPERS
424         select TLS_REG_EMUL if SMP || !MMU
425 
426 config CPU_32v4
427         bool
428         select CPU_USE_DOMAINS if MMU
429         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
430         select NEED_KUSER_HELPERS
431         select TLS_REG_EMUL if SMP || !MMU
432 
433 config CPU_32v4T
434         bool
435         select CPU_USE_DOMAINS if MMU
436         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
437         select NEED_KUSER_HELPERS
438         select TLS_REG_EMUL if SMP || !MMU
439 
440 config CPU_32v5
441         bool
442         select CPU_USE_DOMAINS if MMU
443         select NEEDS_SYSCALL_FOR_CMPXCHG if SMP
444         select NEED_KUSER_HELPERS
445         select TLS_REG_EMUL if SMP || !MMU
446 
447 config CPU_32v6
448         bool
449         select TLS_REG_EMUL if !CPU_32v6K && !MMU
450 
451 config CPU_32v6K
452         bool
453 
454 config CPU_32v7
455         bool
456 
457 config CPU_32v7M
458         bool
459 
460 # The abort model
461 config CPU_ABRT_NOMMU
462         bool
463 
464 config CPU_ABRT_EV4
465         bool
466 
467 config CPU_ABRT_EV4T
468         bool
469 
470 config CPU_ABRT_LV4T
471         bool
472 
473 config CPU_ABRT_EV5T
474         bool
475 
476 config CPU_ABRT_EV5TJ
477         bool
478 
479 config CPU_ABRT_EV6
480         bool
481 
482 config CPU_ABRT_EV7
483         bool
484 
485 config CPU_PABRT_LEGACY
486         bool
487 
488 config CPU_PABRT_V6
489         bool
490 
491 config CPU_PABRT_V7
492         bool
493 
494 # The cache model
495 config CPU_CACHE_V4
496         bool
497 
498 config CPU_CACHE_V4WT
499         bool
500 
501 config CPU_CACHE_V4WB
502         bool
503 
504 config CPU_CACHE_V6
505         bool
506 
507 config CPU_CACHE_V7
508         bool
509 
510 config CPU_CACHE_NOP
511         bool
512 
513 config CPU_CACHE_VIVT
514         bool
515 
516 config CPU_CACHE_VIPT
517         bool
518 
519 config CPU_CACHE_FA
520         bool
521 
522 if MMU
523 # The copy-page model
524 config CPU_COPY_V4WT
525         bool
526 
527 config CPU_COPY_V4WB
528         bool
529 
530 config CPU_COPY_FEROCEON
531         bool
532 
533 config CPU_COPY_FA
534         bool
535 
536 config CPU_COPY_V6
537         bool
538 
539 # This selects the TLB model
540 config CPU_TLB_V4WT
541         bool
542         help
543           ARM Architecture Version 4 TLB with writethrough cache.
544 
545 config CPU_TLB_V4WB
546         bool
547         help
548           ARM Architecture Version 4 TLB with writeback cache.
549 
550 config CPU_TLB_V4WBI
551         bool
552         help
553           ARM Architecture Version 4 TLB with writeback cache and invalidate
554           instruction cache entry.
555 
556 config CPU_TLB_FEROCEON
557         bool
558         help
559           Feroceon TLB (v4wbi with non-outer-cachable page table walks).
560 
561 config CPU_TLB_FA
562         bool
563         help
564           Faraday ARM FA526 architecture, unified TLB with writeback cache
565           and invalidate instruction cache entry. Branch target buffer is
566           also supported.
567 
568 config CPU_TLB_V6
569         bool
570 
571 config CPU_TLB_V7
572         bool
573 
574 config VERIFY_PERMISSION_FAULT
575         bool
576 endif
577 
578 config CPU_HAS_ASID
579         bool
580         help
581           This indicates whether the CPU has the ASID register; used to
582           tag TLB and possibly cache entries.
583 
584 config CPU_CP15
585         bool
586         help
587           Processor has the CP15 register.
588 
589 config CPU_CP15_MMU
590         bool
591         select CPU_CP15
592         help
593           Processor has the CP15 register, which has MMU related registers.
594 
595 config CPU_CP15_MPU
596         bool
597         select CPU_CP15
598         help
599           Processor has the CP15 register, which has MPU related registers.
600 
601 config CPU_USE_DOMAINS
602         bool
603         help
604           This option enables or disables the use of domain switching
605           via the set_fs() function.
606 
607 config CPU_V7M_NUM_IRQ
608         int "Number of external interrupts connected to the NVIC"
609         depends on CPU_V7M
610         default 90 if ARCH_STM32
611         default 38 if ARCH_EFM32
612         default 112 if SOC_VF610
613         default 240
614         help
615           This option indicates the number of interrupts connected to the NVIC.
616           The value can be larger than the real number of interrupts supported
617           by the system, but must not be lower.
618           The default value is 240, corresponding to the maximum number of
619           interrupts supported by the NVIC on Cortex-M family.
620 
621           If unsure, keep default value.
622 
623 #
624 # CPU supports 36-bit I/O
625 #
626 config IO_36
627         bool
628 
629 comment "Processor Features"
630 
631 config ARM_LPAE
632         bool "Support for the Large Physical Address Extension"
633         depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \
634                 !CPU_32v4 && !CPU_32v3
635         help
636           Say Y if you have an ARMv7 processor supporting the LPAE page
637           table format and you would like to access memory beyond the
638           4GB limit. The resulting kernel image will not run on
639           processors without the LPA extension.
640 
641           If unsure, say N.
642 
643 config ARM_PV_FIXUP
644         def_bool y
645         depends on ARM_LPAE && ARM_PATCH_PHYS_VIRT && ARCH_KEYSTONE
646 
647 config ARCH_PHYS_ADDR_T_64BIT
648         def_bool ARM_LPAE
649 
650 config ARCH_DMA_ADDR_T_64BIT
651         bool
652 
653 config ARM_THUMB
654         bool "Support Thumb user binaries" if !CPU_THUMBONLY
655         depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || \
656                 CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || \
657                 CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
658                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || \
659                 CPU_V7 || CPU_FEROCEON || CPU_V7M
660         default y
661         help
662           Say Y if you want to include kernel support for running user space
663           Thumb binaries.
664 
665           The Thumb instruction set is a compressed form of the standard ARM
666           instruction set resulting in smaller binaries at the expense of
667           slightly less efficient code.
668 
669           If you don't know what this all is, saying Y is a safe choice.
670 
671 config ARM_THUMBEE
672         bool "Enable ThumbEE CPU extension"
673         depends on CPU_V7
674         help
675           Say Y here if you have a CPU with the ThumbEE extension and code to
676           make use of it. Say N for code that can run on CPUs without ThumbEE.
677 
678 config ARM_VIRT_EXT
679         bool
680         depends on MMU
681         default y if CPU_V7
682         help
683           Enable the kernel to make use of the ARM Virtualization
684           Extensions to install hypervisors without run-time firmware
685           assistance.
686 
687           A compliant bootloader is required in order to make maximum
688           use of this feature.  Refer to Documentation/arm/Booting for
689           details.
690 
691 config SWP_EMULATE
692         bool "Emulate SWP/SWPB instructions" if !SMP
693         depends on CPU_V7
694         default y if SMP
695         select HAVE_PROC_CPU if PROC_FS
696         help
697           ARMv6 architecture deprecates use of the SWP/SWPB instructions.
698           ARMv7 multiprocessing extensions introduce the ability to disable
699           these instructions, triggering an undefined instruction exception
700           when executed. Say Y here to enable software emulation of these
701           instructions for userspace (not kernel) using LDREX/STREX.
702           Also creates /proc/cpu/swp_emulation for statistics.
703 
704           In some older versions of glibc [<=2.8] SWP is used during futex
705           trylock() operations with the assumption that the code will not
706           be preempted. This invalid assumption may be more likely to fail
707           with SWP emulation enabled, leading to deadlock of the user
708           application.
709 
710           NOTE: when accessing uncached shared regions, LDREX/STREX rely
711           on an external transaction monitoring block called a global
712           monitor to maintain update atomicity. If your system does not
713           implement a global monitor, this option can cause programs that
714           perform SWP operations to uncached memory to deadlock.
715 
716           If unsure, say Y.
717 
718 config CPU_BIG_ENDIAN
719         bool "Build big-endian kernel"
720         depends on ARCH_SUPPORTS_BIG_ENDIAN
721         help
722           Say Y if you plan on running a kernel in big-endian mode.
723           Note that your board must be properly built and your board
724           port must properly enable any big-endian related features
725           of your chipset/board/processor.
726 
727 config CPU_ENDIAN_BE8
728         bool
729         depends on CPU_BIG_ENDIAN
730         default CPU_V6 || CPU_V6K || CPU_V7
731         help
732           Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors.
733 
734 config CPU_ENDIAN_BE32
735         bool
736         depends on CPU_BIG_ENDIAN
737         default !CPU_ENDIAN_BE8
738         help
739           Support for the BE-32 (big-endian) mode on pre-ARMv6 processors.
740 
741 config CPU_HIGH_VECTOR
742         depends on !MMU && CPU_CP15 && !CPU_ARM740T
743         bool "Select the High exception vector"
744         help
745           Say Y here to select high exception vector(0xFFFF0000~).
746           The exception vector can vary depending on the platform
747           design in nommu mode. If your platform needs to select
748           high exception vector, say Y.
749           Otherwise or if you are unsure, say N, and the low exception
750           vector (0x00000000~) will be used.
751 
752 config CPU_ICACHE_DISABLE
753         bool "Disable I-Cache (I-bit)"
754         depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3)
755         help
756           Say Y here to disable the processor instruction cache. Unless
757           you have a reason not to or are unsure, say N.
758 
759 config CPU_DCACHE_DISABLE
760         bool "Disable D-Cache (C-bit)"
761         depends on CPU_CP15 && !SMP
762         help
763           Say Y here to disable the processor data cache. Unless
764           you have a reason not to or are unsure, say N.
765 
766 config CPU_DCACHE_SIZE
767         hex
768         depends on CPU_ARM740T || CPU_ARM946E
769         default 0x00001000 if CPU_ARM740T
770         default 0x00002000 # default size for ARM946E-S
771         help
772           Some cores are synthesizable to have various sized cache. For
773           ARM946E-S case, it can vary from 0KB to 1MB.
774           To support such cache operations, it is efficient to know the size
775           before compile time.
776           If your SoC is configured to have a different size, define the value
777           here with proper conditions.
778 
779 config CPU_DCACHE_WRITETHROUGH
780         bool "Force write through D-cache"
781         depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE
782         default y if CPU_ARM925T
783         help
784           Say Y here to use the data cache in writethrough mode. Unless you
785           specifically require this or are unsure, say N.
786 
787 config CPU_CACHE_ROUND_ROBIN
788         bool "Round robin I and D cache replacement algorithm"
789         depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE)
790         help
791           Say Y here to use the predictable round-robin cache replacement
792           policy.  Unless you specifically require this or are unsure, say N.
793 
794 config CPU_BPREDICT_DISABLE
795         bool "Disable branch prediction"
796         depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526
797         help
798           Say Y here to disable branch prediction.  If unsure, say N.
799 
800 config TLS_REG_EMUL
801         bool
802         select NEED_KUSER_HELPERS
803         help
804           An SMP system using a pre-ARMv6 processor (there are apparently
805           a few prototypes like that in existence) and therefore access to
806           that required register must be emulated.
807 
808 config NEEDS_SYSCALL_FOR_CMPXCHG
809         bool
810         select NEED_KUSER_HELPERS
811         help
812           SMP on a pre-ARMv6 processor?  Well OK then.
813           Forget about fast user space cmpxchg support.
814           It is just not possible.
815 
816 config NEED_KUSER_HELPERS
817         bool
818 
819 config KUSER_HELPERS
820         bool "Enable kuser helpers in vector page" if !NEED_KUSER_HELPERS
821         depends on MMU
822         default y
823         help
824           Warning: disabling this option may break user programs.
825 
826           Provide kuser helpers in the vector page.  The kernel provides
827           helper code to userspace in read only form at a fixed location
828           in the high vector page to allow userspace to be independent of
829           the CPU type fitted to the system.  This permits binaries to be
830           run on ARMv4 through to ARMv7 without modification.
831 
832           See Documentation/arm/kernel_user_helpers.txt for details.
833 
834           However, the fixed address nature of these helpers can be used
835           by ROP (return orientated programming) authors when creating
836           exploits.
837 
838           If all of the binaries and libraries which run on your platform
839           are built specifically for your platform, and make no use of
840           these helpers, then you can turn this option off to hinder
841           such exploits. However, in that case, if a binary or library
842           relying on those helpers is run, it will receive a SIGILL signal,
843           which will terminate the program.
844 
845           Say N here only if you are absolutely certain that you do not
846           need these helpers; otherwise, the safe option is to say Y.
847 
848 config VDSO
849         bool "Enable VDSO for acceleration of some system calls"
850         depends on AEABI && MMU && CPU_V7
851         default y if ARM_ARCH_TIMER
852         select GENERIC_TIME_VSYSCALL
853         help
854           Place in the process address space an ELF shared object
855           providing fast implementations of gettimeofday and
856           clock_gettime.  Systems that implement the ARM architected
857           timer will receive maximum benefit.
858 
859           You must have glibc 2.22 or later for programs to seamlessly
860           take advantage of this.
861 
862 config DMA_CACHE_RWFO
863         bool "Enable read/write for ownership DMA cache maintenance"
864         depends on CPU_V6K && SMP
865         default y
866         help
867           The Snoop Control Unit on ARM11MPCore does not detect the
868           cache maintenance operations and the dma_{map,unmap}_area()
869           functions may leave stale cache entries on other CPUs. By
870           enabling this option, Read or Write For Ownership in the ARMv6
871           DMA cache maintenance functions is performed. These LDR/STR
872           instructions change the cache line state to shared or modified
873           so that the cache operation has the desired effect.
874 
875           Note that the workaround is only valid on processors that do
876           not perform speculative loads into the D-cache. For such
877           processors, if cache maintenance operations are not broadcast
878           in hardware, other workarounds are needed (e.g. cache
879           maintenance broadcasting in software via FIQ).
880 
881 config OUTER_CACHE
882         bool
883 
884 config OUTER_CACHE_SYNC
885         bool
886         help
887           The outer cache has a outer_cache_fns.sync function pointer
888           that can be used to drain the write buffer of the outer cache.
889 
890 config CACHE_FEROCEON_L2
891         bool "Enable the Feroceon L2 cache controller"
892         depends on ARCH_MV78XX0 || ARCH_MVEBU
893         default y
894         select OUTER_CACHE
895         help
896           This option enables the Feroceon L2 cache controller.
897 
898 config CACHE_FEROCEON_L2_WRITETHROUGH
899         bool "Force Feroceon L2 cache write through"
900         depends on CACHE_FEROCEON_L2
901         help
902           Say Y here to use the Feroceon L2 cache in writethrough mode.
903           Unless you specifically require this, say N for writeback mode.
904 
905 config MIGHT_HAVE_CACHE_L2X0
906         bool
907         help
908           This option should be selected by machines which have a L2x0
909           or PL310 cache controller, but where its use is optional.
910 
911           The only effect of this option is to make CACHE_L2X0 and
912           related options available to the user for configuration.
913 
914           Boards or SoCs which always require the cache controller
915           support to be present should select CACHE_L2X0 directly
916           instead of this option, thus preventing the user from
917           inadvertently configuring a broken kernel.
918 
919 config CACHE_L2X0
920         bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0
921         default MIGHT_HAVE_CACHE_L2X0
922         select OUTER_CACHE
923         select OUTER_CACHE_SYNC
924         help
925           This option enables the L2x0 PrimeCell.
926 
927 if CACHE_L2X0
928 
929 config PL310_ERRATA_588369
930         bool "PL310 errata: Clean & Invalidate maintenance operations do not invalidate clean lines"
931         help
932            The PL310 L2 cache controller implements three types of Clean &
933            Invalidate maintenance operations: by Physical Address
934            (offset 0x7F0), by Index/Way (0x7F8) and by Way (0x7FC).
935            They are architecturally defined to behave as the execution of a
936            clean operation followed immediately by an invalidate operation,
937            both performing to the same memory location. This functionality
938            is not correctly implemented in PL310 prior to r2p0 (fixed in r2p0)
939            as clean lines are not invalidated as a result of these operations.
940 
941 config PL310_ERRATA_727915
942         bool "PL310 errata: Background Clean & Invalidate by Way operation can cause data corruption"
943         help
944           PL310 implements the Clean & Invalidate by Way L2 cache maintenance
945           operation (offset 0x7FC). This operation runs in background so that
946           PL310 can handle normal accesses while it is in progress. Under very
947           rare circumstances, due to this erratum, write data can be lost when
948           PL310 treats a cacheable write transaction during a Clean &
949           Invalidate by Way operation.  Revisions prior to r3p1 are affected by
950           this errata (fixed in r3p1).
951 
952 config PL310_ERRATA_753970
953         bool "PL310 errata: cache sync operation may be faulty"
954         help
955           This option enables the workaround for the 753970 PL310 (r3p0) erratum.
956 
957           Under some condition the effect of cache sync operation on
958           the store buffer still remains when the operation completes.
959           This means that the store buffer is always asked to drain and
960           this prevents it from merging any further writes. The workaround
961           is to replace the normal offset of cache sync operation (0x730)
962           by another offset targeting an unmapped PL310 register 0x740.
963           This has the same effect as the cache sync operation: store buffer
964           drain and waiting for all buffers empty.
965 
966 config PL310_ERRATA_769419
967         bool "PL310 errata: no automatic Store Buffer drain"
968         help
969           On revisions of the PL310 prior to r3p2, the Store Buffer does
970           not automatically drain. This can cause normal, non-cacheable
971           writes to be retained when the memory system is idle, leading
972           to suboptimal I/O performance for drivers using coherent DMA.
973           This option adds a write barrier to the cpu_idle loop so that,
974           on systems with an outer cache, the store buffer is drained
975           explicitly.
976 
977 endif
978 
979 config CACHE_TAUROS2
980         bool "Enable the Tauros2 L2 cache controller"
981         depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4)
982         default y
983         select OUTER_CACHE
984         help
985           This option enables the Tauros2 L2 cache controller (as
986           found on PJ1/PJ4).
987 
988 config CACHE_XSC3L2
989         bool "Enable the L2 cache on XScale3"
990         depends on CPU_XSC3
991         default y
992         select OUTER_CACHE
993         help
994           This option enables the L2 cache on XScale3.
995 
996 config ARM_L1_CACHE_SHIFT_6
997         bool
998         default y if CPU_V7
999         help
1000           Setting ARM L1 cache line size to 64 Bytes.
1001 
1002 config ARM_L1_CACHE_SHIFT
1003         int
1004         default 6 if ARM_L1_CACHE_SHIFT_6
1005         default 5
1006 
1007 config ARM_DMA_MEM_BUFFERABLE
1008         bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7
1009         depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \
1010                      MACH_REALVIEW_PB11MP)
1011         default y if CPU_V6 || CPU_V6K || CPU_V7
1012         help
1013           Historically, the kernel has used strongly ordered mappings to
1014           provide DMA coherent memory.  With the advent of ARMv7, mapping
1015           memory with differing types results in unpredictable behaviour,
1016           so on these CPUs, this option is forced on.
1017 
1018           Multiple mappings with differing attributes is also unpredictable
1019           on ARMv6 CPUs, but since they do not have aggressive speculative
1020           prefetch, no harm appears to occur.
1021 
1022           However, drivers may be missing the necessary barriers for ARMv6,
1023           and therefore turning this on may result in unpredictable driver
1024           behaviour.  Therefore, we offer this as an option.
1025 
1026           You are recommended say 'Y' here and debug any affected drivers.
1027 
1028 config ARCH_HAS_BARRIERS
1029         bool
1030         help
1031           This option allows the use of custom mandatory barriers
1032           included via the mach/barriers.h file.
1033 
1034 config ARCH_SUPPORTS_BIG_ENDIAN
1035         bool
1036         help
1037           This option specifies the architecture can support big endian
1038           operation.
1039 
1040 config ARM_KERNMEM_PERMS
1041         bool "Restrict kernel memory permissions"
1042         depends on MMU
1043         help
1044           If this is set, kernel memory other than kernel text (and rodata)
1045           will be made non-executable. The tradeoff is that each region is
1046           padded to section-size (1MiB) boundaries (because their permissions
1047           are different and splitting the 1M pages into 4K ones causes TLB
1048           performance problems), wasting memory.
1049 
1050 config DEBUG_RODATA
1051         bool "Make kernel text and rodata read-only"
1052         depends on ARM_KERNMEM_PERMS
1053         default y
1054         help
1055           If this is set, kernel text and rodata will be made read-only. This
1056           is to help catch accidental or malicious attempts to change the
1057           kernel's executable code. Additionally splits rodata from kernel
1058           text so it can be made explicitly non-executable. This creates
1059           another section-size padded region, so it can waste more memory
1060           space while gaining the read-only protections.

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