Version:  2.6.34 2.6.35 2.6.36 2.6.37 2.6.38 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14

Linux/arch/arm/mach-at91/gpio.c

  1 /*
  2  * linux/arch/arm/mach-at91/gpio.c
  3  *
  4  * Copyright (C) 2005 HP Labs
  5  *
  6  * This program is free software; you can redistribute it and/or modify
  7  * it under the terms of the GNU General Public License as published by
  8  * the Free Software Foundation; either version 2 of the License, or
  9  * (at your option) any later version.
 10  */
 11 
 12 #include <linux/clk.h>
 13 #include <linux/errno.h>
 14 #include <linux/device.h>
 15 #include <linux/gpio.h>
 16 #include <linux/interrupt.h>
 17 #include <linux/irq.h>
 18 #include <linux/debugfs.h>
 19 #include <linux/seq_file.h>
 20 #include <linux/kernel.h>
 21 #include <linux/list.h>
 22 #include <linux/module.h>
 23 #include <linux/io.h>
 24 #include <linux/irqdomain.h>
 25 #include <linux/irqchip/chained_irq.h>
 26 #include <linux/of_address.h>
 27 
 28 #include <mach/hardware.h>
 29 #include <mach/at91_pio.h>
 30 
 31 #include "generic.h"
 32 
 33 #define MAX_NB_GPIO_PER_BANK    32
 34 
 35 struct at91_gpio_chip {
 36         struct gpio_chip        chip;
 37         struct at91_gpio_chip   *next;          /* Bank sharing same clock */
 38         int                     pioc_hwirq;     /* PIO bank interrupt identifier on AIC */
 39         int                     pioc_virq;      /* PIO bank Linux virtual interrupt */
 40         int                     pioc_idx;       /* PIO bank index */
 41         void __iomem            *regbase;       /* PIO bank virtual address */
 42         struct clk              *clock;         /* associated clock */
 43         struct irq_domain       *domain;        /* associated irq domain */
 44 };
 45 
 46 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip)
 47 
 48 static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset);
 49 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip);
 50 static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val);
 51 static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset);
 52 static int at91_gpiolib_direction_output(struct gpio_chip *chip,
 53                                          unsigned offset, int val);
 54 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
 55                                         unsigned offset);
 56 static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset);
 57 
 58 #define AT91_GPIO_CHIP(name)                                            \
 59         {                                                               \
 60                 .chip = {                                               \
 61                         .label            = name,                       \
 62                         .request          = at91_gpiolib_request,       \
 63                         .direction_input  = at91_gpiolib_direction_input, \
 64                         .direction_output = at91_gpiolib_direction_output, \
 65                         .get              = at91_gpiolib_get,           \
 66                         .set              = at91_gpiolib_set,           \
 67                         .dbg_show         = at91_gpiolib_dbg_show,      \
 68                         .to_irq           = at91_gpiolib_to_irq,        \
 69                         .ngpio            = MAX_NB_GPIO_PER_BANK,       \
 70                 },                                                      \
 71         }
 72 
 73 static struct at91_gpio_chip gpio_chip[] = {
 74         AT91_GPIO_CHIP("pioA"),
 75         AT91_GPIO_CHIP("pioB"),
 76         AT91_GPIO_CHIP("pioC"),
 77         AT91_GPIO_CHIP("pioD"),
 78         AT91_GPIO_CHIP("pioE"),
 79 };
 80 
 81 static int gpio_banks;
 82 static unsigned long at91_gpio_caps;
 83 
 84 /* All PIO controllers support PIO3 features */
 85 #define AT91_GPIO_CAP_PIO3      (1 <<  0)
 86 
 87 #define has_pio3()      (at91_gpio_caps & AT91_GPIO_CAP_PIO3)
 88 
 89 /*--------------------------------------------------------------------------*/
 90 
 91 static inline void __iomem *pin_to_controller(unsigned pin)
 92 {
 93         pin /= MAX_NB_GPIO_PER_BANK;
 94         if (likely(pin < gpio_banks))
 95                 return gpio_chip[pin].regbase;
 96 
 97         return NULL;
 98 }
 99 
100 static inline unsigned pin_to_mask(unsigned pin)
101 {
102         return 1 << (pin % MAX_NB_GPIO_PER_BANK);
103 }
104 
105 
106 static char peripheral_function(void __iomem *pio, unsigned mask)
107 {
108         char    ret = 'X';
109         u8      select;
110 
111         if (pio) {
112                 if (has_pio3()) {
113                         select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask);
114                         select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1);
115                         ret = 'A' + select;
116                 } else {
117                         ret = __raw_readl(pio + PIO_ABSR) & mask ?
118                                                         'B' : 'A';
119                 }
120         }
121 
122         return ret;
123 }
124 
125 /*--------------------------------------------------------------------------*/
126 
127 /* Not all hardware capabilities are exposed through these calls; they
128  * only encapsulate the most common features and modes.  (So if you
129  * want to change signals in groups, do it directly.)
130  *
131  * Bootloaders will usually handle some of the pin multiplexing setup.
132  * The intent is certainly that by the time Linux is fully booted, all
133  * pins should have been fully initialized.  These setup calls should
134  * only be used by board setup routines, or possibly in driver probe().
135  *
136  * For bootloaders doing all that setup, these calls could be inlined
137  * as NOPs so Linux won't duplicate any setup code
138  */
139 
140 
141 /*
142  * mux the pin to the "GPIO" peripheral role.
143  */
144 int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup)
145 {
146         void __iomem    *pio = pin_to_controller(pin);
147         unsigned        mask = pin_to_mask(pin);
148 
149         if (!pio)
150                 return -EINVAL;
151         __raw_writel(mask, pio + PIO_IDR);
152         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
153         __raw_writel(mask, pio + PIO_PER);
154         return 0;
155 }
156 EXPORT_SYMBOL(at91_set_GPIO_periph);
157 
158 
159 /*
160  * mux the pin to the "A" internal peripheral role.
161  */
162 int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup)
163 {
164         void __iomem    *pio = pin_to_controller(pin);
165         unsigned        mask = pin_to_mask(pin);
166 
167         if (!pio)
168                 return -EINVAL;
169 
170         __raw_writel(mask, pio + PIO_IDR);
171         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
172         if (has_pio3()) {
173                 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask,
174                                                         pio + PIO_ABCDSR1);
175                 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
176                                                         pio + PIO_ABCDSR2);
177         } else {
178                 __raw_writel(mask, pio + PIO_ASR);
179         }
180         __raw_writel(mask, pio + PIO_PDR);
181         return 0;
182 }
183 EXPORT_SYMBOL(at91_set_A_periph);
184 
185 
186 /*
187  * mux the pin to the "B" internal peripheral role.
188  */
189 int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup)
190 {
191         void __iomem    *pio = pin_to_controller(pin);
192         unsigned        mask = pin_to_mask(pin);
193 
194         if (!pio)
195                 return -EINVAL;
196 
197         __raw_writel(mask, pio + PIO_IDR);
198         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
199         if (has_pio3()) {
200                 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask,
201                                                         pio + PIO_ABCDSR1);
202                 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask,
203                                                         pio + PIO_ABCDSR2);
204         } else {
205                 __raw_writel(mask, pio + PIO_BSR);
206         }
207         __raw_writel(mask, pio + PIO_PDR);
208         return 0;
209 }
210 EXPORT_SYMBOL(at91_set_B_periph);
211 
212 
213 /*
214  * mux the pin to the "C" internal peripheral role.
215  */
216 int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup)
217 {
218         void __iomem    *pio = pin_to_controller(pin);
219         unsigned        mask = pin_to_mask(pin);
220 
221         if (!pio || !has_pio3())
222                 return -EINVAL;
223 
224         __raw_writel(mask, pio + PIO_IDR);
225         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
226         __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1);
227         __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
228         __raw_writel(mask, pio + PIO_PDR);
229         return 0;
230 }
231 EXPORT_SYMBOL(at91_set_C_periph);
232 
233 
234 /*
235  * mux the pin to the "D" internal peripheral role.
236  */
237 int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup)
238 {
239         void __iomem    *pio = pin_to_controller(pin);
240         unsigned        mask = pin_to_mask(pin);
241 
242         if (!pio || !has_pio3())
243                 return -EINVAL;
244 
245         __raw_writel(mask, pio + PIO_IDR);
246         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
247         __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1);
248         __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2);
249         __raw_writel(mask, pio + PIO_PDR);
250         return 0;
251 }
252 EXPORT_SYMBOL(at91_set_D_periph);
253 
254 
255 /*
256  * mux the pin to the gpio controller (instead of "A", "B", "C"
257  * or "D" peripheral), and configure it for an input.
258  */
259 int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup)
260 {
261         void __iomem    *pio = pin_to_controller(pin);
262         unsigned        mask = pin_to_mask(pin);
263 
264         if (!pio)
265                 return -EINVAL;
266 
267         __raw_writel(mask, pio + PIO_IDR);
268         __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR));
269         __raw_writel(mask, pio + PIO_ODR);
270         __raw_writel(mask, pio + PIO_PER);
271         return 0;
272 }
273 EXPORT_SYMBOL(at91_set_gpio_input);
274 
275 
276 /*
277  * mux the pin to the gpio controller (instead of "A", "B", "C"
278  * or "D" peripheral), and configure it for an output.
279  */
280 int __init_or_module at91_set_gpio_output(unsigned pin, int value)
281 {
282         void __iomem    *pio = pin_to_controller(pin);
283         unsigned        mask = pin_to_mask(pin);
284 
285         if (!pio)
286                 return -EINVAL;
287 
288         __raw_writel(mask, pio + PIO_IDR);
289         __raw_writel(mask, pio + PIO_PUDR);
290         __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
291         __raw_writel(mask, pio + PIO_OER);
292         __raw_writel(mask, pio + PIO_PER);
293         return 0;
294 }
295 EXPORT_SYMBOL(at91_set_gpio_output);
296 
297 
298 /*
299  * enable/disable the glitch filter; mostly used with IRQ handling.
300  */
301 int __init_or_module at91_set_deglitch(unsigned pin, int is_on)
302 {
303         void __iomem    *pio = pin_to_controller(pin);
304         unsigned        mask = pin_to_mask(pin);
305 
306         if (!pio)
307                 return -EINVAL;
308 
309         if (has_pio3() && is_on)
310                 __raw_writel(mask, pio + PIO_IFSCDR);
311         __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
312         return 0;
313 }
314 EXPORT_SYMBOL(at91_set_deglitch);
315 
316 /*
317  * enable/disable the debounce filter;
318  */
319 int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div)
320 {
321         void __iomem    *pio = pin_to_controller(pin);
322         unsigned        mask = pin_to_mask(pin);
323 
324         if (!pio || !has_pio3())
325                 return -EINVAL;
326 
327         if (is_on) {
328                 __raw_writel(mask, pio + PIO_IFSCER);
329                 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
330                 __raw_writel(mask, pio + PIO_IFER);
331         } else {
332                 __raw_writel(mask, pio + PIO_IFDR);
333         }
334         return 0;
335 }
336 EXPORT_SYMBOL(at91_set_debounce);
337 
338 /*
339  * enable/disable the multi-driver; This is only valid for output and
340  * allows the output pin to run as an open collector output.
341  */
342 int __init_or_module at91_set_multi_drive(unsigned pin, int is_on)
343 {
344         void __iomem    *pio = pin_to_controller(pin);
345         unsigned        mask = pin_to_mask(pin);
346 
347         if (!pio)
348                 return -EINVAL;
349 
350         __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR));
351         return 0;
352 }
353 EXPORT_SYMBOL(at91_set_multi_drive);
354 
355 /*
356  * enable/disable the pull-down.
357  * If pull-up already enabled while calling the function, we disable it.
358  */
359 int __init_or_module at91_set_pulldown(unsigned pin, int is_on)
360 {
361         void __iomem    *pio = pin_to_controller(pin);
362         unsigned        mask = pin_to_mask(pin);
363 
364         if (!pio || !has_pio3())
365                 return -EINVAL;
366 
367         /* Disable pull-up anyway */
368         __raw_writel(mask, pio + PIO_PUDR);
369         __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR));
370         return 0;
371 }
372 EXPORT_SYMBOL(at91_set_pulldown);
373 
374 /*
375  * disable Schmitt trigger
376  */
377 int __init_or_module at91_disable_schmitt_trig(unsigned pin)
378 {
379         void __iomem    *pio = pin_to_controller(pin);
380         unsigned        mask = pin_to_mask(pin);
381 
382         if (!pio || !has_pio3())
383                 return -EINVAL;
384 
385         __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT);
386         return 0;
387 }
388 EXPORT_SYMBOL(at91_disable_schmitt_trig);
389 
390 /*
391  * assuming the pin is muxed as a gpio output, set its value.
392  */
393 int at91_set_gpio_value(unsigned pin, int value)
394 {
395         void __iomem    *pio = pin_to_controller(pin);
396         unsigned        mask = pin_to_mask(pin);
397 
398         if (!pio)
399                 return -EINVAL;
400         __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR));
401         return 0;
402 }
403 EXPORT_SYMBOL(at91_set_gpio_value);
404 
405 
406 /*
407  * read the pin's value (works even if it's not muxed as a gpio).
408  */
409 int at91_get_gpio_value(unsigned pin)
410 {
411         void __iomem    *pio = pin_to_controller(pin);
412         unsigned        mask = pin_to_mask(pin);
413         u32             pdsr;
414 
415         if (!pio)
416                 return -EINVAL;
417         pdsr = __raw_readl(pio + PIO_PDSR);
418         return (pdsr & mask) != 0;
419 }
420 EXPORT_SYMBOL(at91_get_gpio_value);
421 
422 /*--------------------------------------------------------------------------*/
423 
424 #ifdef CONFIG_PM
425 
426 static u32 wakeups[MAX_GPIO_BANKS];
427 static u32 backups[MAX_GPIO_BANKS];
428 
429 static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
430 {
431         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
432         unsigned        mask = 1 << d->hwirq;
433         unsigned        bank = at91_gpio->pioc_idx;
434 
435         if (unlikely(bank >= MAX_GPIO_BANKS))
436                 return -EINVAL;
437 
438         if (state)
439                 wakeups[bank] |= mask;
440         else
441                 wakeups[bank] &= ~mask;
442 
443         irq_set_irq_wake(at91_gpio->pioc_virq, state);
444 
445         return 0;
446 }
447 
448 void at91_gpio_suspend(void)
449 {
450         int i;
451 
452         for (i = 0; i < gpio_banks; i++) {
453                 void __iomem    *pio = gpio_chip[i].regbase;
454 
455                 backups[i] = __raw_readl(pio + PIO_IMR);
456                 __raw_writel(backups[i], pio + PIO_IDR);
457                 __raw_writel(wakeups[i], pio + PIO_IER);
458 
459                 if (!wakeups[i]) {
460                         clk_unprepare(gpio_chip[i].clock);
461                         clk_disable(gpio_chip[i].clock);
462                 } else {
463 #ifdef CONFIG_PM_DEBUG
464                         printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]);
465 #endif
466                 }
467         }
468 }
469 
470 void at91_gpio_resume(void)
471 {
472         int i;
473 
474         for (i = 0; i < gpio_banks; i++) {
475                 void __iomem    *pio = gpio_chip[i].regbase;
476 
477                 if (!wakeups[i]) {
478                         if (clk_prepare(gpio_chip[i].clock) == 0)
479                                 clk_enable(gpio_chip[i].clock);
480                 }
481 
482                 __raw_writel(wakeups[i], pio + PIO_IDR);
483                 __raw_writel(backups[i], pio + PIO_IER);
484         }
485 }
486 
487 #else
488 #define gpio_irq_set_wake       NULL
489 #endif
490 
491 
492 /* Several AIC controller irqs are dispatched through this GPIO handler.
493  * To use any AT91_PIN_* as an externally triggered IRQ, first call
494  * at91_set_gpio_input() then maybe enable its glitch filter.
495  * Then just request_irq() with the pin ID; it works like any ARM IRQ
496  * handler.
497  * First implementation always triggers on rising and falling edges
498  * whereas the newer PIO3 can be additionally configured to trigger on
499  * level, edge with any polarity.
500  *
501  * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after
502  * configuring them with at91_set_a_periph() or at91_set_b_periph().
503  * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering.
504  */
505 
506 static void gpio_irq_mask(struct irq_data *d)
507 {
508         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
509         void __iomem    *pio = at91_gpio->regbase;
510         unsigned        mask = 1 << d->hwirq;
511 
512         if (pio)
513                 __raw_writel(mask, pio + PIO_IDR);
514 }
515 
516 static void gpio_irq_unmask(struct irq_data *d)
517 {
518         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
519         void __iomem    *pio = at91_gpio->regbase;
520         unsigned        mask = 1 << d->hwirq;
521 
522         if (pio)
523                 __raw_writel(mask, pio + PIO_IER);
524 }
525 
526 static int gpio_irq_type(struct irq_data *d, unsigned type)
527 {
528         switch (type) {
529         case IRQ_TYPE_NONE:
530         case IRQ_TYPE_EDGE_BOTH:
531                 return 0;
532         default:
533                 return -EINVAL;
534         }
535 }
536 
537 /* Alternate irq type for PIO3 support */
538 static int alt_gpio_irq_type(struct irq_data *d, unsigned type)
539 {
540         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d);
541         void __iomem    *pio = at91_gpio->regbase;
542         unsigned        mask = 1 << d->hwirq;
543 
544         switch (type) {
545         case IRQ_TYPE_EDGE_RISING:
546                 __raw_writel(mask, pio + PIO_ESR);
547                 __raw_writel(mask, pio + PIO_REHLSR);
548                 break;
549         case IRQ_TYPE_EDGE_FALLING:
550                 __raw_writel(mask, pio + PIO_ESR);
551                 __raw_writel(mask, pio + PIO_FELLSR);
552                 break;
553         case IRQ_TYPE_LEVEL_LOW:
554                 __raw_writel(mask, pio + PIO_LSR);
555                 __raw_writel(mask, pio + PIO_FELLSR);
556                 break;
557         case IRQ_TYPE_LEVEL_HIGH:
558                 __raw_writel(mask, pio + PIO_LSR);
559                 __raw_writel(mask, pio + PIO_REHLSR);
560                 break;
561         case IRQ_TYPE_EDGE_BOTH:
562                 /*
563                  * disable additional interrupt modes:
564                  * fall back to default behavior
565                  */
566                 __raw_writel(mask, pio + PIO_AIMDR);
567                 return 0;
568         case IRQ_TYPE_NONE:
569         default:
570                 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq));
571                 return -EINVAL;
572         }
573 
574         /* enable additional interrupt modes */
575         __raw_writel(mask, pio + PIO_AIMER);
576 
577         return 0;
578 }
579 
580 static struct irq_chip gpio_irqchip = {
581         .name           = "GPIO",
582         .irq_disable    = gpio_irq_mask,
583         .irq_mask       = gpio_irq_mask,
584         .irq_unmask     = gpio_irq_unmask,
585         /* .irq_set_type is set dynamically */
586         .irq_set_wake   = gpio_irq_set_wake,
587 };
588 
589 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
590 {
591         struct irq_chip *chip = irq_desc_get_chip(desc);
592         struct irq_data *idata = irq_desc_get_irq_data(desc);
593         struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata);
594         void __iomem    *pio = at91_gpio->regbase;
595         unsigned long   isr;
596         int             n;
597 
598         chained_irq_enter(chip, desc);
599         for (;;) {
600                 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
601                  * When there none are pending, we're finished unless we need
602                  * to process multiple banks (like ID_PIOCDE on sam9263).
603                  */
604                 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR);
605                 if (!isr) {
606                         if (!at91_gpio->next)
607                                 break;
608                         at91_gpio = at91_gpio->next;
609                         pio = at91_gpio->regbase;
610                         continue;
611                 }
612 
613                 n = find_first_bit(&isr, BITS_PER_LONG);
614                 while (n < BITS_PER_LONG) {
615                         generic_handle_irq(irq_find_mapping(at91_gpio->domain, n));
616                         n = find_next_bit(&isr, BITS_PER_LONG, n + 1);
617                 }
618         }
619         chained_irq_exit(chip, desc);
620         /* now it may re-trigger */
621 }
622 
623 /*--------------------------------------------------------------------------*/
624 
625 #ifdef CONFIG_DEBUG_FS
626 
627 static void gpio_printf(struct seq_file *s, void __iomem *pio, unsigned mask)
628 {
629         char    *trigger = NULL;
630         char    *polarity = NULL;
631 
632         if (__raw_readl(pio + PIO_IMR) & mask) {
633                 if (!has_pio3() || !(__raw_readl(pio + PIO_AIMMR) & mask )) {
634                         trigger = "edge";
635                         polarity = "both";
636                 } else {
637                         if (__raw_readl(pio + PIO_ELSR) & mask) {
638                                 trigger = "level";
639                                 polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
640                                         "high" : "low";
641                         } else {
642                                 trigger = "edge";
643                                 polarity = __raw_readl(pio + PIO_FRLHSR) & mask ?
644                                                 "rising" : "falling";
645                         }
646                 }
647                 seq_printf(s, "IRQ:%s-%s\t", trigger, polarity);
648         } else {
649                 seq_printf(s, "GPIO:%s\t\t",
650                                 __raw_readl(pio + PIO_PDSR) & mask ? "1" : "");
651         }
652 }
653 
654 static int at91_gpio_show(struct seq_file *s, void *unused)
655 {
656         int bank, j;
657 
658         /* print heading */
659         seq_printf(s, "Pin\t");
660         for (bank = 0; bank < gpio_banks; bank++) {
661                 seq_printf(s, "PIO%c\t\t", 'A' + bank);
662         };
663         seq_printf(s, "\n\n");
664 
665         /* print pin status */
666         for (j = 0; j < 32; j++) {
667                 seq_printf(s, "%i:\t", j);
668 
669                 for (bank = 0; bank < gpio_banks; bank++) {
670                         unsigned        pin  = (32 * bank) + j;
671                         void __iomem    *pio = pin_to_controller(pin);
672                         unsigned        mask = pin_to_mask(pin);
673 
674                         if (__raw_readl(pio + PIO_PSR) & mask)
675                                 gpio_printf(s, pio, mask);
676                         else
677                                 seq_printf(s, "%c\t\t",
678                                                 peripheral_function(pio, mask));
679                 }
680 
681                 seq_printf(s, "\n");
682         }
683 
684         return 0;
685 }
686 
687 static int at91_gpio_open(struct inode *inode, struct file *file)
688 {
689         return single_open(file, at91_gpio_show, NULL);
690 }
691 
692 static const struct file_operations at91_gpio_operations = {
693         .open           = at91_gpio_open,
694         .read           = seq_read,
695         .llseek         = seq_lseek,
696         .release        = single_release,
697 };
698 
699 static int __init at91_gpio_debugfs_init(void)
700 {
701         /* /sys/kernel/debug/at91_gpio */
702         (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations);
703         return 0;
704 }
705 postcore_initcall(at91_gpio_debugfs_init);
706 
707 #endif
708 
709 /*--------------------------------------------------------------------------*/
710 
711 /*
712  * This lock class tells lockdep that GPIO irqs are in a different
713  * category than their parents, so it won't report false recursion.
714  */
715 static struct lock_class_key gpio_lock_class;
716 
717 /*
718  * irqdomain initialization: pile up irqdomains on top of AIC range
719  */
720 static void __init at91_gpio_irqdomain(struct at91_gpio_chip *at91_gpio)
721 {
722         int irq_base;
723 
724         irq_base = irq_alloc_descs(-1, 0, at91_gpio->chip.ngpio, 0);
725         if (irq_base < 0)
726                 panic("at91_gpio.%d: error %d: couldn't allocate IRQ numbers.\n",
727                         at91_gpio->pioc_idx, irq_base);
728         at91_gpio->domain = irq_domain_add_legacy(NULL, at91_gpio->chip.ngpio,
729                                                   irq_base, 0,
730                                                   &irq_domain_simple_ops, NULL);
731         if (!at91_gpio->domain)
732                 panic("at91_gpio.%d: couldn't allocate irq domain.\n",
733                         at91_gpio->pioc_idx);
734 }
735 
736 /*
737  * Called from the processor-specific init to enable GPIO interrupt support.
738  */
739 void __init at91_gpio_irq_setup(void)
740 {
741         unsigned                pioc;
742         int                     gpio_irqnbr = 0;
743         struct at91_gpio_chip   *this, *prev;
744 
745         /* Setup proper .irq_set_type function */
746         if (has_pio3())
747                 gpio_irqchip.irq_set_type = alt_gpio_irq_type;
748         else
749                 gpio_irqchip.irq_set_type = gpio_irq_type;
750 
751         for (pioc = 0, this = gpio_chip, prev = NULL;
752                         pioc++ < gpio_banks;
753                         prev = this, this++) {
754                 int offset;
755 
756                 __raw_writel(~0, this->regbase + PIO_IDR);
757 
758                 /* setup irq domain for this GPIO controller */
759                 at91_gpio_irqdomain(this);
760 
761                 for (offset = 0; offset < this->chip.ngpio; offset++) {
762                         unsigned int virq = irq_find_mapping(this->domain, offset);
763                         irq_set_lockdep_class(virq, &gpio_lock_class);
764 
765                         /*
766                          * Can use the "simple" and not "edge" handler since it's
767                          * shorter, and the AIC handles interrupts sanely.
768                          */
769                         irq_set_chip_and_handler(virq, &gpio_irqchip,
770                                                  handle_simple_irq);
771                         set_irq_flags(virq, IRQF_VALID);
772                         irq_set_chip_data(virq, this);
773 
774                         gpio_irqnbr++;
775                 }
776 
777                 /* The toplevel handler handles one bank of GPIOs, except
778                  * on some SoC it can handles up to three...
779                  * We only set up the handler for the first of the list.
780                  */
781                 if (prev && prev->next == this)
782                         continue;
783 
784                 this->pioc_virq = irq_create_mapping(NULL, this->pioc_hwirq);
785                 irq_set_chip_data(this->pioc_virq, this);
786                 irq_set_chained_handler(this->pioc_virq, gpio_irq_handler);
787         }
788         pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr, gpio_banks);
789 }
790 
791 /* gpiolib support */
792 static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset)
793 {
794         struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
795         void __iomem *pio = at91_gpio->regbase;
796         unsigned mask = 1 << offset;
797 
798         __raw_writel(mask, pio + PIO_PER);
799         return 0;
800 }
801 
802 static int at91_gpiolib_direction_input(struct gpio_chip *chip,
803                                         unsigned offset)
804 {
805         struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
806         void __iomem *pio = at91_gpio->regbase;
807         unsigned mask = 1 << offset;
808 
809         __raw_writel(mask, pio + PIO_ODR);
810         return 0;
811 }
812 
813 static int at91_gpiolib_direction_output(struct gpio_chip *chip,
814                                          unsigned offset, int val)
815 {
816         struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
817         void __iomem *pio = at91_gpio->regbase;
818         unsigned mask = 1 << offset;
819 
820         __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
821         __raw_writel(mask, pio + PIO_OER);
822         return 0;
823 }
824 
825 static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset)
826 {
827         struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
828         void __iomem *pio = at91_gpio->regbase;
829         unsigned mask = 1 << offset;
830         u32 pdsr;
831 
832         pdsr = __raw_readl(pio + PIO_PDSR);
833         return (pdsr & mask) != 0;
834 }
835 
836 static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val)
837 {
838         struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
839         void __iomem *pio = at91_gpio->regbase;
840         unsigned mask = 1 << offset;
841 
842         __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR));
843 }
844 
845 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip)
846 {
847         int i;
848 
849         for (i = 0; i < chip->ngpio; i++) {
850                 unsigned pin = chip->base + i;
851                 void __iomem *pio = pin_to_controller(pin);
852                 unsigned mask = pin_to_mask(pin);
853                 const char *gpio_label;
854 
855                 gpio_label = gpiochip_is_requested(chip, i);
856                 if (gpio_label) {
857                         seq_printf(s, "[%s] GPIO%s%d: ",
858                                    gpio_label, chip->label, i);
859                         if (__raw_readl(pio + PIO_PSR) & mask)
860                                 seq_printf(s, "[gpio] %s\n",
861                                            at91_get_gpio_value(pin) ?
862                                            "set" : "clear");
863                         else
864                                 seq_printf(s, "[periph %c]\n",
865                                            peripheral_function(pio, mask));
866                 }
867         }
868 }
869 
870 static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset)
871 {
872         struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip);
873         int virq;
874 
875         if (offset < chip->ngpio)
876                 virq = irq_create_mapping(at91_gpio->domain, offset);
877         else
878                 virq = -ENXIO;
879 
880         dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n",
881                                 chip->label, offset + chip->base, virq);
882         return virq;
883 }
884 
885 static int __init at91_gpio_setup_clk(int idx)
886 {
887         struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
888 
889         /* retreive PIO controller's clock */
890         at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label);
891         if (IS_ERR(at91_gpio->clock)) {
892                 pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", idx);
893                 goto err;
894         }
895 
896         if (clk_prepare(at91_gpio->clock))
897                 goto clk_prep_err;
898 
899         /* enable PIO controller's clock */
900         if (clk_enable(at91_gpio->clock)) {
901                 pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx);
902                 goto clk_err;
903         }
904 
905         return 0;
906 
907 clk_err:
908         clk_unprepare(at91_gpio->clock);
909 clk_prep_err:
910         clk_put(at91_gpio->clock);
911 err:
912         return -EINVAL;
913 }
914 
915 static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq)
916 {
917         struct at91_gpio_chip *at91_gpio = &gpio_chip[idx];
918 
919         at91_gpio->chip.base = idx * MAX_NB_GPIO_PER_BANK;
920         at91_gpio->pioc_hwirq = pioc_hwirq;
921         at91_gpio->pioc_idx = idx;
922 
923         at91_gpio->regbase = ioremap(regbase, 512);
924         if (!at91_gpio->regbase) {
925                 pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", idx);
926                 return;
927         }
928 
929         if (at91_gpio_setup_clk(idx))
930                 goto ioremap_err;
931 
932         gpio_banks = max(gpio_banks, idx + 1);
933         return;
934 
935 ioremap_err:
936         iounmap(at91_gpio->regbase);
937 }
938 
939 /*
940  * Called from the processor-specific init to enable GPIO pin support.
941  */
942 void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks)
943 {
944         unsigned i;
945         struct at91_gpio_chip *at91_gpio, *last = NULL;
946 
947         BUG_ON(nr_banks > MAX_GPIO_BANKS);
948 
949         if (of_have_populated_dt())
950                 return;
951 
952         for (i = 0; i < nr_banks; i++)
953                 at91_gpio_init_one(i, data[i].regbase, data[i].id);
954 
955         for (i = 0; i < gpio_banks; i++) {
956                 at91_gpio = &gpio_chip[i];
957 
958                 /*
959                  * GPIO controller are grouped on some SoC:
960                  * PIOC, PIOD and PIOE can share the same IRQ line
961                  */
962                 if (last && last->pioc_hwirq == at91_gpio->pioc_hwirq)
963                         last->next = at91_gpio;
964                 last = at91_gpio;
965 
966                 gpiochip_add(&at91_gpio->chip);
967         }
968 }
969 

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us