• source navigation • diff markup • identifier search • freetext search •
Version: 2.6.32 2.6.33 2.6.34 2.6.35 2.6.36 2.6.37 2.6.38 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9
Architecture: x86 arm avr32 blackfin m68k m68knommu microblaze mips powerpc sh
1 /* 2 * linux/arch/arm/mach-at91/gpio.c 3 * 4 * Copyright (C) 2005 HP Labs 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/errno.h> 14 #include <linux/device.h> 15 #include <linux/gpio.h> 16 #include <linux/interrupt.h> 17 #include <linux/irq.h> 18 #include <linux/debugfs.h> 19 #include <linux/seq_file.h> 20 #include <linux/kernel.h> 21 #include <linux/list.h> 22 #include <linux/module.h> 23 #include <linux/io.h> 24 #include <linux/irqdomain.h> 25 #include <linux/of_address.h> 26 27 #include <asm/mach/irq.h> 28 29 #include <mach/hardware.h> 30 #include <mach/at91_pio.h> 31 32 #include "generic.h" 33 34 #define MAX_NB_GPIO_PER_BANK 32 35 36 struct at91_gpio_chip { 37 struct gpio_chip chip; 38 struct at91_gpio_chip *next; /* Bank sharing same clock */ 39 int pioc_hwirq; /* PIO bank interrupt identifier on AIC */ 40 int pioc_virq; /* PIO bank Linux virtual interrupt */ 41 int pioc_idx; /* PIO bank index */ 42 void __iomem *regbase; /* PIO bank virtual address */ 43 struct clk *clock; /* associated clock */ 44 struct irq_domain *domain; /* associated irq domain */ 45 }; 46 47 #define to_at91_gpio_chip(c) container_of(c, struct at91_gpio_chip, chip) 48 49 static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset); 50 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip); 51 static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val); 52 static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset); 53 static int at91_gpiolib_direction_output(struct gpio_chip *chip, 54 unsigned offset, int val); 55 static int at91_gpiolib_direction_input(struct gpio_chip *chip, 56 unsigned offset); 57 static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset); 58 59 #define AT91_GPIO_CHIP(name) \ 60 { \ 61 .chip = { \ 62 .label = name, \ 63 .request = at91_gpiolib_request, \ 64 .direction_input = at91_gpiolib_direction_input, \ 65 .direction_output = at91_gpiolib_direction_output, \ 66 .get = at91_gpiolib_get, \ 67 .set = at91_gpiolib_set, \ 68 .dbg_show = at91_gpiolib_dbg_show, \ 69 .to_irq = at91_gpiolib_to_irq, \ 70 .ngpio = MAX_NB_GPIO_PER_BANK, \ 71 }, \ 72 } 73 74 static struct at91_gpio_chip gpio_chip[] = { 75 AT91_GPIO_CHIP("pioA"), 76 AT91_GPIO_CHIP("pioB"), 77 AT91_GPIO_CHIP("pioC"), 78 AT91_GPIO_CHIP("pioD"), 79 AT91_GPIO_CHIP("pioE"), 80 }; 81 82 static int gpio_banks; 83 static unsigned long at91_gpio_caps; 84 85 /* All PIO controllers support PIO3 features */ 86 #define AT91_GPIO_CAP_PIO3 (1 << 0) 87 88 #define has_pio3() (at91_gpio_caps & AT91_GPIO_CAP_PIO3) 89 90 /*--------------------------------------------------------------------------*/ 91 92 static inline void __iomem *pin_to_controller(unsigned pin) 93 { 94 pin /= MAX_NB_GPIO_PER_BANK; 95 if (likely(pin < gpio_banks)) 96 return gpio_chip[pin].regbase; 97 98 return NULL; 99 } 100 101 static inline unsigned pin_to_mask(unsigned pin) 102 { 103 return 1 << (pin % MAX_NB_GPIO_PER_BANK); 104 } 105 106 107 static char peripheral_function(void __iomem *pio, unsigned mask) 108 { 109 char ret = 'X'; 110 u8 select; 111 112 if (pio) { 113 if (has_pio3()) { 114 select = !!(__raw_readl(pio + PIO_ABCDSR1) & mask); 115 select |= (!!(__raw_readl(pio + PIO_ABCDSR2) & mask) << 1); 116 ret = 'A' + select; 117 } else { 118 ret = __raw_readl(pio + PIO_ABSR) & mask ? 119 'B' : 'A'; 120 } 121 } 122 123 return ret; 124 } 125 126 /*--------------------------------------------------------------------------*/ 127 128 /* Not all hardware capabilities are exposed through these calls; they 129 * only encapsulate the most common features and modes. (So if you 130 * want to change signals in groups, do it directly.) 131 * 132 * Bootloaders will usually handle some of the pin multiplexing setup. 133 * The intent is certainly that by the time Linux is fully booted, all 134 * pins should have been fully initialized. These setup calls should 135 * only be used by board setup routines, or possibly in driver probe(). 136 * 137 * For bootloaders doing all that setup, these calls could be inlined 138 * as NOPs so Linux won't duplicate any setup code 139 */ 140 141 142 /* 143 * mux the pin to the "GPIO" peripheral role. 144 */ 145 int __init_or_module at91_set_GPIO_periph(unsigned pin, int use_pullup) 146 { 147 void __iomem *pio = pin_to_controller(pin); 148 unsigned mask = pin_to_mask(pin); 149 150 if (!pio) 151 return -EINVAL; 152 __raw_writel(mask, pio + PIO_IDR); 153 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); 154 __raw_writel(mask, pio + PIO_PER); 155 return 0; 156 } 157 EXPORT_SYMBOL(at91_set_GPIO_periph); 158 159 160 /* 161 * mux the pin to the "A" internal peripheral role. 162 */ 163 int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup) 164 { 165 void __iomem *pio = pin_to_controller(pin); 166 unsigned mask = pin_to_mask(pin); 167 168 if (!pio) 169 return -EINVAL; 170 171 __raw_writel(mask, pio + PIO_IDR); 172 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); 173 if (has_pio3()) { 174 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, 175 pio + PIO_ABCDSR1); 176 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask, 177 pio + PIO_ABCDSR2); 178 } else { 179 __raw_writel(mask, pio + PIO_ASR); 180 } 181 __raw_writel(mask, pio + PIO_PDR); 182 return 0; 183 } 184 EXPORT_SYMBOL(at91_set_A_periph); 185 186 187 /* 188 * mux the pin to the "B" internal peripheral role. 189 */ 190 int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup) 191 { 192 void __iomem *pio = pin_to_controller(pin); 193 unsigned mask = pin_to_mask(pin); 194 195 if (!pio) 196 return -EINVAL; 197 198 __raw_writel(mask, pio + PIO_IDR); 199 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); 200 if (has_pio3()) { 201 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, 202 pio + PIO_ABCDSR1); 203 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) & ~mask, 204 pio + PIO_ABCDSR2); 205 } else { 206 __raw_writel(mask, pio + PIO_BSR); 207 } 208 __raw_writel(mask, pio + PIO_PDR); 209 return 0; 210 } 211 EXPORT_SYMBOL(at91_set_B_periph); 212 213 214 /* 215 * mux the pin to the "C" internal peripheral role. 216 */ 217 int __init_or_module at91_set_C_periph(unsigned pin, int use_pullup) 218 { 219 void __iomem *pio = pin_to_controller(pin); 220 unsigned mask = pin_to_mask(pin); 221 222 if (!pio || !has_pio3()) 223 return -EINVAL; 224 225 __raw_writel(mask, pio + PIO_IDR); 226 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); 227 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) & ~mask, pio + PIO_ABCDSR1); 228 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 229 __raw_writel(mask, pio + PIO_PDR); 230 return 0; 231 } 232 EXPORT_SYMBOL(at91_set_C_periph); 233 234 235 /* 236 * mux the pin to the "D" internal peripheral role. 237 */ 238 int __init_or_module at91_set_D_periph(unsigned pin, int use_pullup) 239 { 240 void __iomem *pio = pin_to_controller(pin); 241 unsigned mask = pin_to_mask(pin); 242 243 if (!pio || !has_pio3()) 244 return -EINVAL; 245 246 __raw_writel(mask, pio + PIO_IDR); 247 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); 248 __raw_writel(__raw_readl(pio + PIO_ABCDSR1) | mask, pio + PIO_ABCDSR1); 249 __raw_writel(__raw_readl(pio + PIO_ABCDSR2) | mask, pio + PIO_ABCDSR2); 250 __raw_writel(mask, pio + PIO_PDR); 251 return 0; 252 } 253 EXPORT_SYMBOL(at91_set_D_periph); 254 255 256 /* 257 * mux the pin to the gpio controller (instead of "A", "B", "C" 258 * or "D" peripheral), and configure it for an input. 259 */ 260 int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup) 261 { 262 void __iomem *pio = pin_to_controller(pin); 263 unsigned mask = pin_to_mask(pin); 264 265 if (!pio) 266 return -EINVAL; 267 268 __raw_writel(mask, pio + PIO_IDR); 269 __raw_writel(mask, pio + (use_pullup ? PIO_PUER : PIO_PUDR)); 270 __raw_writel(mask, pio + PIO_ODR); 271 __raw_writel(mask, pio + PIO_PER); 272 return 0; 273 } 274 EXPORT_SYMBOL(at91_set_gpio_input); 275 276 277 /* 278 * mux the pin to the gpio controller (instead of "A", "B", "C" 279 * or "D" peripheral), and configure it for an output. 280 */ 281 int __init_or_module at91_set_gpio_output(unsigned pin, int value) 282 { 283 void __iomem *pio = pin_to_controller(pin); 284 unsigned mask = pin_to_mask(pin); 285 286 if (!pio) 287 return -EINVAL; 288 289 __raw_writel(mask, pio + PIO_IDR); 290 __raw_writel(mask, pio + PIO_PUDR); 291 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); 292 __raw_writel(mask, pio + PIO_OER); 293 __raw_writel(mask, pio + PIO_PER); 294 return 0; 295 } 296 EXPORT_SYMBOL(at91_set_gpio_output); 297 298 299 /* 300 * enable/disable the glitch filter; mostly used with IRQ handling. 301 */ 302 int __init_or_module at91_set_deglitch(unsigned pin, int is_on) 303 { 304 void __iomem *pio = pin_to_controller(pin); 305 unsigned mask = pin_to_mask(pin); 306 307 if (!pio) 308 return -EINVAL; 309 310 if (has_pio3() && is_on) 311 __raw_writel(mask, pio + PIO_IFSCDR); 312 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); 313 return 0; 314 } 315 EXPORT_SYMBOL(at91_set_deglitch); 316 317 /* 318 * enable/disable the debounce filter; 319 */ 320 int __init_or_module at91_set_debounce(unsigned pin, int is_on, int div) 321 { 322 void __iomem *pio = pin_to_controller(pin); 323 unsigned mask = pin_to_mask(pin); 324 325 if (!pio || !has_pio3()) 326 return -EINVAL; 327 328 if (is_on) { 329 __raw_writel(mask, pio + PIO_IFSCER); 330 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); 331 __raw_writel(mask, pio + PIO_IFER); 332 } else { 333 __raw_writel(mask, pio + PIO_IFDR); 334 } 335 return 0; 336 } 337 EXPORT_SYMBOL(at91_set_debounce); 338 339 /* 340 * enable/disable the multi-driver; This is only valid for output and 341 * allows the output pin to run as an open collector output. 342 */ 343 int __init_or_module at91_set_multi_drive(unsigned pin, int is_on) 344 { 345 void __iomem *pio = pin_to_controller(pin); 346 unsigned mask = pin_to_mask(pin); 347 348 if (!pio) 349 return -EINVAL; 350 351 __raw_writel(mask, pio + (is_on ? PIO_MDER : PIO_MDDR)); 352 return 0; 353 } 354 EXPORT_SYMBOL(at91_set_multi_drive); 355 356 /* 357 * enable/disable the pull-down. 358 * If pull-up already enabled while calling the function, we disable it. 359 */ 360 int __init_or_module at91_set_pulldown(unsigned pin, int is_on) 361 { 362 void __iomem *pio = pin_to_controller(pin); 363 unsigned mask = pin_to_mask(pin); 364 365 if (!pio || !has_pio3()) 366 return -EINVAL; 367 368 /* Disable pull-up anyway */ 369 __raw_writel(mask, pio + PIO_PUDR); 370 __raw_writel(mask, pio + (is_on ? PIO_PPDER : PIO_PPDDR)); 371 return 0; 372 } 373 EXPORT_SYMBOL(at91_set_pulldown); 374 375 /* 376 * disable Schmitt trigger 377 */ 378 int __init_or_module at91_disable_schmitt_trig(unsigned pin) 379 { 380 void __iomem *pio = pin_to_controller(pin); 381 unsigned mask = pin_to_mask(pin); 382 383 if (!pio || !has_pio3()) 384 return -EINVAL; 385 386 __raw_writel(__raw_readl(pio + PIO_SCHMITT) | mask, pio + PIO_SCHMITT); 387 return 0; 388 } 389 EXPORT_SYMBOL(at91_disable_schmitt_trig); 390 391 /* 392 * assuming the pin is muxed as a gpio output, set its value. 393 */ 394 int at91_set_gpio_value(unsigned pin, int value) 395 { 396 void __iomem *pio = pin_to_controller(pin); 397 unsigned mask = pin_to_mask(pin); 398 399 if (!pio) 400 return -EINVAL; 401 __raw_writel(mask, pio + (value ? PIO_SODR : PIO_CODR)); 402 return 0; 403 } 404 EXPORT_SYMBOL(at91_set_gpio_value); 405 406 407 /* 408 * read the pin's value (works even if it's not muxed as a gpio). 409 */ 410 int at91_get_gpio_value(unsigned pin) 411 { 412 void __iomem *pio = pin_to_controller(pin); 413 unsigned mask = pin_to_mask(pin); 414 u32 pdsr; 415 416 if (!pio) 417 return -EINVAL; 418 pdsr = __raw_readl(pio + PIO_PDSR); 419 return (pdsr & mask) != 0; 420 } 421 EXPORT_SYMBOL(at91_get_gpio_value); 422 423 /*--------------------------------------------------------------------------*/ 424 425 #ifdef CONFIG_PM 426 427 static u32 wakeups[MAX_GPIO_BANKS]; 428 static u32 backups[MAX_GPIO_BANKS]; 429 430 static int gpio_irq_set_wake(struct irq_data *d, unsigned state) 431 { 432 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 433 unsigned mask = 1 << d->hwirq; 434 unsigned bank = at91_gpio->pioc_idx; 435 436 if (unlikely(bank >= MAX_GPIO_BANKS)) 437 return -EINVAL; 438 439 if (state) 440 wakeups[bank] |= mask; 441 else 442 wakeups[bank] &= ~mask; 443 444 irq_set_irq_wake(at91_gpio->pioc_virq, state); 445 446 return 0; 447 } 448 449 void at91_gpio_suspend(void) 450 { 451 int i; 452 453 for (i = 0; i < gpio_banks; i++) { 454 void __iomem *pio = gpio_chip[i].regbase; 455 456 backups[i] = __raw_readl(pio + PIO_IMR); 457 __raw_writel(backups[i], pio + PIO_IDR); 458 __raw_writel(wakeups[i], pio + PIO_IER); 459 460 if (!wakeups[i]) { 461 clk_unprepare(gpio_chip[i].clock); 462 clk_disable(gpio_chip[i].clock); 463 } else { 464 #ifdef CONFIG_PM_DEBUG 465 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 'A'+i, wakeups[i]); 466 #endif 467 } 468 } 469 } 470 471 void at91_gpio_resume(void) 472 { 473 int i; 474 475 for (i = 0; i < gpio_banks; i++) { 476 void __iomem *pio = gpio_chip[i].regbase; 477 478 if (!wakeups[i]) { 479 if (clk_prepare(gpio_chip[i].clock) == 0) 480 clk_enable(gpio_chip[i].clock); 481 } 482 483 __raw_writel(wakeups[i], pio + PIO_IDR); 484 __raw_writel(backups[i], pio + PIO_IER); 485 } 486 } 487 488 #else 489 #define gpio_irq_set_wake NULL 490 #endif 491 492 493 /* Several AIC controller irqs are dispatched through this GPIO handler. 494 * To use any AT91_PIN_* as an externally triggered IRQ, first call 495 * at91_set_gpio_input() then maybe enable its glitch filter. 496 * Then just request_irq() with the pin ID; it works like any ARM IRQ 497 * handler. 498 * First implementation always triggers on rising and falling edges 499 * whereas the newer PIO3 can be additionally configured to trigger on 500 * level, edge with any polarity. 501 * 502 * Alternatively, certain pins may be used directly as IRQ0..IRQ6 after 503 * configuring them with at91_set_a_periph() or at91_set_b_periph(). 504 * IRQ0..IRQ6 should be configurable, e.g. level vs edge triggering. 505 */ 506 507 static void gpio_irq_mask(struct irq_data *d) 508 { 509 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 510 void __iomem *pio = at91_gpio->regbase; 511 unsigned mask = 1 << d->hwirq; 512 513 if (pio) 514 __raw_writel(mask, pio + PIO_IDR); 515 } 516 517 static void gpio_irq_unmask(struct irq_data *d) 518 { 519 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 520 void __iomem *pio = at91_gpio->regbase; 521 unsigned mask = 1 << d->hwirq; 522 523 if (pio) 524 __raw_writel(mask, pio + PIO_IER); 525 } 526 527 static int gpio_irq_type(struct irq_data *d, unsigned type) 528 { 529 switch (type) { 530 case IRQ_TYPE_NONE: 531 case IRQ_TYPE_EDGE_BOTH: 532 return 0; 533 default: 534 return -EINVAL; 535 } 536 } 537 538 /* Alternate irq type for PIO3 support */ 539 static int alt_gpio_irq_type(struct irq_data *d, unsigned type) 540 { 541 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(d); 542 void __iomem *pio = at91_gpio->regbase; 543 unsigned mask = 1 << d->hwirq; 544 545 switch (type) { 546 case IRQ_TYPE_EDGE_RISING: 547 __raw_writel(mask, pio + PIO_ESR); 548 __raw_writel(mask, pio + PIO_REHLSR); 549 break; 550 case IRQ_TYPE_EDGE_FALLING: 551 __raw_writel(mask, pio + PIO_ESR); 552 __raw_writel(mask, pio + PIO_FELLSR); 553 break; 554 case IRQ_TYPE_LEVEL_LOW: 555 __raw_writel(mask, pio + PIO_LSR); 556 __raw_writel(mask, pio + PIO_FELLSR); 557 break; 558 case IRQ_TYPE_LEVEL_HIGH: 559 __raw_writel(mask, pio + PIO_LSR); 560 __raw_writel(mask, pio + PIO_REHLSR); 561 break; 562 case IRQ_TYPE_EDGE_BOTH: 563 /* 564 * disable additional interrupt modes: 565 * fall back to default behavior 566 */ 567 __raw_writel(mask, pio + PIO_AIMDR); 568 return 0; 569 case IRQ_TYPE_NONE: 570 default: 571 pr_warn("AT91: No type for irq %d\n", gpio_to_irq(d->irq)); 572 return -EINVAL; 573 } 574 575 /* enable additional interrupt modes */ 576 __raw_writel(mask, pio + PIO_AIMER); 577 578 return 0; 579 } 580 581 static struct irq_chip gpio_irqchip = { 582 .name = "GPIO", 583 .irq_disable = gpio_irq_mask, 584 .irq_mask = gpio_irq_mask, 585 .irq_unmask = gpio_irq_unmask, 586 /* .irq_set_type is set dynamically */ 587 .irq_set_wake = gpio_irq_set_wake, 588 }; 589 590 static void gpio_irq_handler(unsigned irq, struct irq_desc *desc) 591 { 592 struct irq_chip *chip = irq_desc_get_chip(desc); 593 struct irq_data *idata = irq_desc_get_irq_data(desc); 594 struct at91_gpio_chip *at91_gpio = irq_data_get_irq_chip_data(idata); 595 void __iomem *pio = at91_gpio->regbase; 596 unsigned long isr; 597 int n; 598 599 chained_irq_enter(chip, desc); 600 for (;;) { 601 /* Reading ISR acks pending (edge triggered) GPIO interrupts. 602 * When there none are pending, we're finished unless we need 603 * to process multiple banks (like ID_PIOCDE on sam9263). 604 */ 605 isr = __raw_readl(pio + PIO_ISR) & __raw_readl(pio + PIO_IMR); 606 if (!isr) { 607 if (!at91_gpio->next) 608 break; 609 at91_gpio = at91_gpio->next; 610 pio = at91_gpio->regbase; 611 continue; 612 } 613 614 n = find_first_bit(&isr, BITS_PER_LONG); 615 while (n < BITS_PER_LONG) { 616 generic_handle_irq(irq_find_mapping(at91_gpio->domain, n)); 617 n = find_next_bit(&isr, BITS_PER_LONG, n + 1); 618 } 619 } 620 chained_irq_exit(chip, desc); 621 /* now it may re-trigger */ 622 } 623 624 /*--------------------------------------------------------------------------*/ 625 626 #ifdef CONFIG_DEBUG_FS 627 628 static void gpio_printf(struct seq_file *s, void __iomem *pio, unsigned mask) 629 { 630 char *trigger = NULL; 631 char *polarity = NULL; 632 633 if (__raw_readl(pio + PIO_IMR) & mask) { 634 if (!has_pio3() || !(__raw_readl(pio + PIO_AIMMR) & mask )) { 635 trigger = "edge"; 636 polarity = "both"; 637 } else { 638 if (__raw_readl(pio + PIO_ELSR) & mask) { 639 trigger = "level"; 640 polarity = __raw_readl(pio + PIO_FRLHSR) & mask ? 641 "high" : "low"; 642 } else { 643 trigger = "edge"; 644 polarity = __raw_readl(pio + PIO_FRLHSR) & mask ? 645 "rising" : "falling"; 646 } 647 } 648 seq_printf(s, "IRQ:%s-%s\t", trigger, polarity); 649 } else { 650 seq_printf(s, "GPIO:%s\t\t", 651 __raw_readl(pio + PIO_PDSR) & mask ? "1" : ""); 652 } 653 } 654 655 static int at91_gpio_show(struct seq_file *s, void *unused) 656 { 657 int bank, j; 658 659 /* print heading */ 660 seq_printf(s, "Pin\t"); 661 for (bank = 0; bank < gpio_banks; bank++) { 662 seq_printf(s, "PIO%c\t\t", 'A' + bank); 663 }; 664 seq_printf(s, "\n\n"); 665 666 /* print pin status */ 667 for (j = 0; j < 32; j++) { 668 seq_printf(s, "%i:\t", j); 669 670 for (bank = 0; bank < gpio_banks; bank++) { 671 unsigned pin = (32 * bank) + j; 672 void __iomem *pio = pin_to_controller(pin); 673 unsigned mask = pin_to_mask(pin); 674 675 if (__raw_readl(pio + PIO_PSR) & mask) 676 gpio_printf(s, pio, mask); 677 else 678 seq_printf(s, "%c\t\t", 679 peripheral_function(pio, mask)); 680 } 681 682 seq_printf(s, "\n"); 683 } 684 685 return 0; 686 } 687 688 static int at91_gpio_open(struct inode *inode, struct file *file) 689 { 690 return single_open(file, at91_gpio_show, NULL); 691 } 692 693 static const struct file_operations at91_gpio_operations = { 694 .open = at91_gpio_open, 695 .read = seq_read, 696 .llseek = seq_lseek, 697 .release = single_release, 698 }; 699 700 static int __init at91_gpio_debugfs_init(void) 701 { 702 /* /sys/kernel/debug/at91_gpio */ 703 (void) debugfs_create_file("at91_gpio", S_IFREG | S_IRUGO, NULL, NULL, &at91_gpio_operations); 704 return 0; 705 } 706 postcore_initcall(at91_gpio_debugfs_init); 707 708 #endif 709 710 /*--------------------------------------------------------------------------*/ 711 712 /* 713 * This lock class tells lockdep that GPIO irqs are in a different 714 * category than their parents, so it won't report false recursion. 715 */ 716 static struct lock_class_key gpio_lock_class; 717 718 /* 719 * irqdomain initialization: pile up irqdomains on top of AIC range 720 */ 721 static void __init at91_gpio_irqdomain(struct at91_gpio_chip *at91_gpio) 722 { 723 int irq_base; 724 725 irq_base = irq_alloc_descs(-1, 0, at91_gpio->chip.ngpio, 0); 726 if (irq_base < 0) 727 panic("at91_gpio.%d: error %d: couldn't allocate IRQ numbers.\n", 728 at91_gpio->pioc_idx, irq_base); 729 at91_gpio->domain = irq_domain_add_legacy(NULL, at91_gpio->chip.ngpio, 730 irq_base, 0, 731 &irq_domain_simple_ops, NULL); 732 if (!at91_gpio->domain) 733 panic("at91_gpio.%d: couldn't allocate irq domain.\n", 734 at91_gpio->pioc_idx); 735 } 736 737 /* 738 * Called from the processor-specific init to enable GPIO interrupt support. 739 */ 740 void __init at91_gpio_irq_setup(void) 741 { 742 unsigned pioc; 743 int gpio_irqnbr = 0; 744 struct at91_gpio_chip *this, *prev; 745 746 /* Setup proper .irq_set_type function */ 747 if (has_pio3()) 748 gpio_irqchip.irq_set_type = alt_gpio_irq_type; 749 else 750 gpio_irqchip.irq_set_type = gpio_irq_type; 751 752 for (pioc = 0, this = gpio_chip, prev = NULL; 753 pioc++ < gpio_banks; 754 prev = this, this++) { 755 int offset; 756 757 __raw_writel(~0, this->regbase + PIO_IDR); 758 759 /* setup irq domain for this GPIO controller */ 760 at91_gpio_irqdomain(this); 761 762 for (offset = 0; offset < this->chip.ngpio; offset++) { 763 unsigned int virq = irq_find_mapping(this->domain, offset); 764 irq_set_lockdep_class(virq, &gpio_lock_class); 765 766 /* 767 * Can use the "simple" and not "edge" handler since it's 768 * shorter, and the AIC handles interrupts sanely. 769 */ 770 irq_set_chip_and_handler(virq, &gpio_irqchip, 771 handle_simple_irq); 772 set_irq_flags(virq, IRQF_VALID); 773 irq_set_chip_data(virq, this); 774 775 gpio_irqnbr++; 776 } 777 778 /* The toplevel handler handles one bank of GPIOs, except 779 * on some SoC it can handles up to three... 780 * We only set up the handler for the first of the list. 781 */ 782 if (prev && prev->next == this) 783 continue; 784 785 this->pioc_virq = irq_create_mapping(NULL, this->pioc_hwirq); 786 irq_set_chip_data(this->pioc_virq, this); 787 irq_set_chained_handler(this->pioc_virq, gpio_irq_handler); 788 } 789 pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr, gpio_banks); 790 } 791 792 /* gpiolib support */ 793 static int at91_gpiolib_request(struct gpio_chip *chip, unsigned offset) 794 { 795 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 796 void __iomem *pio = at91_gpio->regbase; 797 unsigned mask = 1 << offset; 798 799 __raw_writel(mask, pio + PIO_PER); 800 return 0; 801 } 802 803 static int at91_gpiolib_direction_input(struct gpio_chip *chip, 804 unsigned offset) 805 { 806 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 807 void __iomem *pio = at91_gpio->regbase; 808 unsigned mask = 1 << offset; 809 810 __raw_writel(mask, pio + PIO_ODR); 811 return 0; 812 } 813 814 static int at91_gpiolib_direction_output(struct gpio_chip *chip, 815 unsigned offset, int val) 816 { 817 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 818 void __iomem *pio = at91_gpio->regbase; 819 unsigned mask = 1 << offset; 820 821 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR)); 822 __raw_writel(mask, pio + PIO_OER); 823 return 0; 824 } 825 826 static int at91_gpiolib_get(struct gpio_chip *chip, unsigned offset) 827 { 828 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 829 void __iomem *pio = at91_gpio->regbase; 830 unsigned mask = 1 << offset; 831 u32 pdsr; 832 833 pdsr = __raw_readl(pio + PIO_PDSR); 834 return (pdsr & mask) != 0; 835 } 836 837 static void at91_gpiolib_set(struct gpio_chip *chip, unsigned offset, int val) 838 { 839 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 840 void __iomem *pio = at91_gpio->regbase; 841 unsigned mask = 1 << offset; 842 843 __raw_writel(mask, pio + (val ? PIO_SODR : PIO_CODR)); 844 } 845 846 static void at91_gpiolib_dbg_show(struct seq_file *s, struct gpio_chip *chip) 847 { 848 int i; 849 850 for (i = 0; i < chip->ngpio; i++) { 851 unsigned pin = chip->base + i; 852 void __iomem *pio = pin_to_controller(pin); 853 unsigned mask = pin_to_mask(pin); 854 const char *gpio_label; 855 856 gpio_label = gpiochip_is_requested(chip, i); 857 if (gpio_label) { 858 seq_printf(s, "[%s] GPIO%s%d: ", 859 gpio_label, chip->label, i); 860 if (__raw_readl(pio + PIO_PSR) & mask) 861 seq_printf(s, "[gpio] %s\n", 862 at91_get_gpio_value(pin) ? 863 "set" : "clear"); 864 else 865 seq_printf(s, "[periph %c]\n", 866 peripheral_function(pio, mask)); 867 } 868 } 869 } 870 871 static int at91_gpiolib_to_irq(struct gpio_chip *chip, unsigned offset) 872 { 873 struct at91_gpio_chip *at91_gpio = to_at91_gpio_chip(chip); 874 int virq; 875 876 if (offset < chip->ngpio) 877 virq = irq_create_mapping(at91_gpio->domain, offset); 878 else 879 virq = -ENXIO; 880 881 dev_dbg(chip->dev, "%s: request IRQ for GPIO %d, return %d\n", 882 chip->label, offset + chip->base, virq); 883 return virq; 884 } 885 886 static int __init at91_gpio_setup_clk(int idx) 887 { 888 struct at91_gpio_chip *at91_gpio = &gpio_chip[idx]; 889 890 /* retreive PIO controller's clock */ 891 at91_gpio->clock = clk_get_sys(NULL, at91_gpio->chip.label); 892 if (IS_ERR(at91_gpio->clock)) { 893 pr_err("at91_gpio.%d, failed to get clock, ignoring.\n", idx); 894 goto err; 895 } 896 897 if (clk_prepare(at91_gpio->clock)) 898 goto clk_prep_err; 899 900 /* enable PIO controller's clock */ 901 if (clk_enable(at91_gpio->clock)) { 902 pr_err("at91_gpio.%d, failed to enable clock, ignoring.\n", idx); 903 goto clk_err; 904 } 905 906 return 0; 907 908 clk_err: 909 clk_unprepare(at91_gpio->clock); 910 clk_prep_err: 911 clk_put(at91_gpio->clock); 912 err: 913 return -EINVAL; 914 } 915 916 static void __init at91_gpio_init_one(int idx, u32 regbase, int pioc_hwirq) 917 { 918 struct at91_gpio_chip *at91_gpio = &gpio_chip[idx]; 919 920 at91_gpio->chip.base = idx * MAX_NB_GPIO_PER_BANK; 921 at91_gpio->pioc_hwirq = pioc_hwirq; 922 at91_gpio->pioc_idx = idx; 923 924 at91_gpio->regbase = ioremap(regbase, 512); 925 if (!at91_gpio->regbase) { 926 pr_err("at91_gpio.%d, failed to map registers, ignoring.\n", idx); 927 return; 928 } 929 930 if (at91_gpio_setup_clk(idx)) 931 goto ioremap_err; 932 933 gpio_banks = max(gpio_banks, idx + 1); 934 return; 935 936 ioremap_err: 937 iounmap(at91_gpio->regbase); 938 } 939 940 /* 941 * Called from the processor-specific init to enable GPIO pin support. 942 */ 943 void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) 944 { 945 unsigned i; 946 struct at91_gpio_chip *at91_gpio, *last = NULL; 947 948 BUG_ON(nr_banks > MAX_GPIO_BANKS); 949 950 if (of_have_populated_dt()) 951 return; 952 953 for (i = 0; i < nr_banks; i++) 954 at91_gpio_init_one(i, data[i].regbase, data[i].id); 955 956 for (i = 0; i < gpio_banks; i++) { 957 at91_gpio = &gpio_chip[i]; 958 959 /* 960 * GPIO controller are grouped on some SoC: 961 * PIOC, PIOD and PIOE can share the same IRQ line 962 */ 963 if (last && last->pioc_hwirq == at91_gpio->pioc_hwirq) 964 last->next = at91_gpio; 965 last = at91_gpio; 966 967 gpiochip_add(&at91_gpio->chip); 968 } 969 } 970
This page was automatically generated by LXR 0.3.1 (source). • Linux is a registered trademark of Linus Torvalds