Version:  2.0.40 2.2.26 2.4.37 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17

Linux/arch/arm/Kconfig

  1 config ARM
  2         bool
  3         default y
  4         select ARCH_BINFMT_ELF_RANDOMIZE_PIE
  5         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
  6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  7         select ARCH_HAVE_CUSTOM_GPIO_H
  8         select ARCH_MIGHT_HAVE_PC_PARPORT
  9         select ARCH_SUPPORTS_ATOMIC_RMW
 10         select ARCH_USE_BUILTIN_BSWAP
 11         select ARCH_USE_CMPXCHG_LOCKREF
 12         select ARCH_WANT_IPC_PARSE_VERSION
 13         select BUILDTIME_EXTABLE_SORT if MMU
 14         select CLONE_BACKWARDS
 15         select CPU_PM if (SUSPEND || CPU_IDLE)
 16         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
 17         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
 18         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
 19         select GENERIC_IDLE_POLL_SETUP
 20         select GENERIC_IRQ_PROBE
 21         select GENERIC_IRQ_SHOW
 22         select GENERIC_PCI_IOMAP
 23         select GENERIC_SCHED_CLOCK
 24         select GENERIC_SMP_IDLE_THREAD
 25         select GENERIC_STRNCPY_FROM_USER
 26         select GENERIC_STRNLEN_USER
 27         select HARDIRQS_SW_RESEND
 28         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
 29         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
 30         select HAVE_ARCH_KGDB
 31         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
 32         select HAVE_ARCH_TRACEHOOK
 33         select HAVE_BPF_JIT
 34         select HAVE_CC_STACKPROTECTOR
 35         select HAVE_CONTEXT_TRACKING
 36         select HAVE_C_RECORDMCOUNT
 37         select HAVE_DEBUG_KMEMLEAK
 38         select HAVE_DMA_API_DEBUG
 39         select HAVE_DMA_ATTRS
 40         select HAVE_DMA_CONTIGUOUS if MMU
 41         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
 42         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
 43         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
 44         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
 45         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
 46         select HAVE_GENERIC_DMA_COHERENT
 47         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
 48         select HAVE_IDE if PCI || ISA || PCMCIA
 49         select HAVE_IRQ_TIME_ACCOUNTING
 50         select HAVE_KERNEL_GZIP
 51         select HAVE_KERNEL_LZ4
 52         select HAVE_KERNEL_LZMA
 53         select HAVE_KERNEL_LZO
 54         select HAVE_KERNEL_XZ
 55         select HAVE_KPROBES if !XIP_KERNEL
 56         select HAVE_KRETPROBES if (HAVE_KPROBES)
 57         select HAVE_MEMBLOCK
 58         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
 59         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
 60         select HAVE_PERF_EVENTS
 61         select HAVE_PERF_REGS
 62         select HAVE_PERF_USER_STACK_DUMP
 63         select HAVE_REGS_AND_STACK_ACCESS_API
 64         select HAVE_SYSCALL_TRACEPOINTS
 65         select HAVE_UID16
 66         select HAVE_VIRT_CPU_ACCOUNTING_GEN
 67         select IRQ_FORCED_THREADING
 68         select MODULES_USE_ELF_REL
 69         select NO_BOOTMEM
 70         select OLD_SIGACTION
 71         select OLD_SIGSUSPEND3
 72         select PERF_USE_VMALLOC
 73         select RTC_LIB
 74         select SYS_SUPPORTS_APM_EMULATION
 75         # Above selects are sorted alphabetically; please add new ones
 76         # according to that.  Thanks.
 77         help
 78           The ARM series is a line of low-power-consumption RISC chip designs
 79           licensed by ARM Ltd and targeted at embedded applications and
 80           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
 81           manufactured, but legacy ARM-based PC hardware remains popular in
 82           Europe.  There is an ARM Linux project with a web page at
 83           <http://www.arm.linux.org.uk/>.
 84 
 85 config ARM_HAS_SG_CHAIN
 86         select ARCH_HAS_SG_CHAIN
 87         bool
 88 
 89 config NEED_SG_DMA_LENGTH
 90         bool
 91 
 92 config ARM_DMA_USE_IOMMU
 93         bool
 94         select ARM_HAS_SG_CHAIN
 95         select NEED_SG_DMA_LENGTH
 96 
 97 if ARM_DMA_USE_IOMMU
 98 
 99 config ARM_DMA_IOMMU_ALIGNMENT
100         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
101         range 4 9
102         default 8
103         help
104           DMA mapping framework by default aligns all buffers to the smallest
105           PAGE_SIZE order which is greater than or equal to the requested buffer
106           size. This works well for buffers up to a few hundreds kilobytes, but
107           for larger buffers it just a waste of address space. Drivers which has
108           relatively small addressing window (like 64Mib) might run out of
109           virtual space with just a few allocations.
110 
111           With this parameter you can specify the maximum PAGE_SIZE order for
112           DMA IOMMU buffers. Larger buffers will be aligned only to this
113           specified order. The order is expressed as a power of two multiplied
114           by the PAGE_SIZE.
115 
116 endif
117 
118 config MIGHT_HAVE_PCI
119         bool
120 
121 config SYS_SUPPORTS_APM_EMULATION
122         bool
123 
124 config HAVE_TCM
125         bool
126         select GENERIC_ALLOCATOR
127 
128 config HAVE_PROC_CPU
129         bool
130 
131 config NO_IOPORT_MAP
132         bool
133 
134 config EISA
135         bool
136         ---help---
137           The Extended Industry Standard Architecture (EISA) bus was
138           developed as an open alternative to the IBM MicroChannel bus.
139 
140           The EISA bus provided some of the features of the IBM MicroChannel
141           bus while maintaining backward compatibility with cards made for
142           the older ISA bus.  The EISA bus saw limited use between 1988 and
143           1995 when it was made obsolete by the PCI bus.
144 
145           Say Y here if you are building a kernel for an EISA-based machine.
146 
147           Otherwise, say N.
148 
149 config SBUS
150         bool
151 
152 config STACKTRACE_SUPPORT
153         bool
154         default y
155 
156 config HAVE_LATENCYTOP_SUPPORT
157         bool
158         depends on !SMP
159         default y
160 
161 config LOCKDEP_SUPPORT
162         bool
163         default y
164 
165 config TRACE_IRQFLAGS_SUPPORT
166         bool
167         default y
168 
169 config RWSEM_XCHGADD_ALGORITHM
170         bool
171         default y
172 
173 config ARCH_HAS_ILOG2_U32
174         bool
175 
176 config ARCH_HAS_ILOG2_U64
177         bool
178 
179 config ARCH_HAS_BANDGAP
180         bool
181 
182 config GENERIC_HWEIGHT
183         bool
184         default y
185 
186 config GENERIC_CALIBRATE_DELAY
187         bool
188         default y
189 
190 config ARCH_MAY_HAVE_PC_FDC
191         bool
192 
193 config ZONE_DMA
194         bool
195 
196 config NEED_DMA_MAP_STATE
197        def_bool y
198 
199 config ARCH_SUPPORTS_UPROBES
200         def_bool y
201 
202 config ARCH_HAS_DMA_SET_COHERENT_MASK
203         bool
204 
205 config GENERIC_ISA_DMA
206         bool
207 
208 config FIQ
209         bool
210 
211 config NEED_RET_TO_USER
212         bool
213 
214 config ARCH_MTD_XIP
215         bool
216 
217 config VECTORS_BASE
218         hex
219         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
220         default DRAM_BASE if REMAP_VECTORS_TO_RAM
221         default 0x00000000
222         help
223           The base address of exception vectors.  This must be two pages
224           in size.
225 
226 config ARM_PATCH_PHYS_VIRT
227         bool "Patch physical to virtual translations at runtime" if EMBEDDED
228         default y
229         depends on !XIP_KERNEL && MMU
230         depends on !ARCH_REALVIEW || !SPARSEMEM
231         help
232           Patch phys-to-virt and virt-to-phys translation functions at
233           boot and module load time according to the position of the
234           kernel in system memory.
235 
236           This can only be used with non-XIP MMU kernels where the base
237           of physical memory is at a 16MB boundary.
238 
239           Only disable this option if you know that you do not require
240           this feature (eg, building a kernel for a single machine) and
241           you need to shrink the kernel to the minimal size.
242 
243 config NEED_MACH_IO_H
244         bool
245         help
246           Select this when mach/io.h is required to provide special
247           definitions for this platform.  The need for mach/io.h should
248           be avoided when possible.
249 
250 config NEED_MACH_MEMORY_H
251         bool
252         help
253           Select this when mach/memory.h is required to provide special
254           definitions for this platform.  The need for mach/memory.h should
255           be avoided when possible.
256 
257 config PHYS_OFFSET
258         hex "Physical address of main memory" if MMU
259         depends on !ARM_PATCH_PHYS_VIRT
260         default DRAM_BASE if !MMU
261         default 0x00000000 if ARCH_EBSA110 || \
262                         EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
263                         ARCH_FOOTBRIDGE || \
264                         ARCH_INTEGRATOR || \
265                         ARCH_IOP13XX || \
266                         ARCH_KS8695 || \
267                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
268         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
269         default 0x20000000 if ARCH_S5PV210
270         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
271         default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
272         default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
273         default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
274         default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
275         help
276           Please provide the physical address corresponding to the
277           location of main memory in your system.
278 
279 config GENERIC_BUG
280         def_bool y
281         depends on BUG
282 
283 source "init/Kconfig"
284 
285 source "kernel/Kconfig.freezer"
286 
287 menu "System Type"
288 
289 config MMU
290         bool "MMU-based Paged Memory Management Support"
291         default y
292         help
293           Select if you want MMU-based virtualised addressing space
294           support by paged memory management. If unsure, say 'Y'.
295 
296 #
297 # The "ARM system type" choice list is ordered alphabetically by option
298 # text.  Please add new entries in the option alphabetic order.
299 #
300 choice
301         prompt "ARM system type"
302         default ARCH_VERSATILE if !MMU
303         default ARCH_MULTIPLATFORM if MMU
304 
305 config ARCH_MULTIPLATFORM
306         bool "Allow multiple platforms to be selected"
307         depends on MMU
308         select ARCH_WANT_OPTIONAL_GPIOLIB
309         select ARM_HAS_SG_CHAIN
310         select ARM_PATCH_PHYS_VIRT
311         select AUTO_ZRELADDR
312         select CLKSRC_OF
313         select COMMON_CLK
314         select GENERIC_CLOCKEVENTS
315         select MIGHT_HAVE_PCI
316         select MULTI_IRQ_HANDLER
317         select SPARSE_IRQ
318         select USE_OF
319 
320 config ARCH_INTEGRATOR
321         bool "ARM Ltd. Integrator family"
322         select ARM_AMBA
323         select ARM_PATCH_PHYS_VIRT if MMU
324         select AUTO_ZRELADDR
325         select COMMON_CLK
326         select COMMON_CLK_VERSATILE
327         select GENERIC_CLOCKEVENTS
328         select HAVE_TCM
329         select ICST
330         select MULTI_IRQ_HANDLER
331         select PLAT_VERSATILE
332         select SPARSE_IRQ
333         select USE_OF
334         select VERSATILE_FPGA_IRQ
335         help
336           Support for ARM's Integrator platform.
337 
338 config ARCH_REALVIEW
339         bool "ARM Ltd. RealView family"
340         select ARCH_WANT_OPTIONAL_GPIOLIB
341         select ARM_AMBA
342         select ARM_TIMER_SP804
343         select COMMON_CLK
344         select COMMON_CLK_VERSATILE
345         select GENERIC_CLOCKEVENTS
346         select GPIO_PL061 if GPIOLIB
347         select ICST
348         select NEED_MACH_MEMORY_H
349         select PLAT_VERSATILE
350         help
351           This enables support for ARM Ltd RealView boards.
352 
353 config ARCH_VERSATILE
354         bool "ARM Ltd. Versatile family"
355         select ARCH_WANT_OPTIONAL_GPIOLIB
356         select ARM_AMBA
357         select ARM_TIMER_SP804
358         select ARM_VIC
359         select CLKDEV_LOOKUP
360         select GENERIC_CLOCKEVENTS
361         select HAVE_MACH_CLKDEV
362         select ICST
363         select PLAT_VERSATILE
364         select PLAT_VERSATILE_CLOCK
365         select VERSATILE_FPGA_IRQ
366         help
367           This enables support for ARM Ltd Versatile board.
368 
369 config ARCH_AT91
370         bool "Atmel AT91"
371         select ARCH_REQUIRE_GPIOLIB
372         select CLKDEV_LOOKUP
373         select IRQ_DOMAIN
374         select NEED_MACH_IO_H if PCCARD
375         select PINCTRL
376         select PINCTRL_AT91 if USE_OF
377         help
378           This enables support for systems based on Atmel
379           AT91RM9200 and AT91SAM9* processors.
380 
381 config ARCH_CLPS711X
382         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
383         select ARCH_REQUIRE_GPIOLIB
384         select AUTO_ZRELADDR
385         select CLKSRC_MMIO
386         select COMMON_CLK
387         select CPU_ARM720T
388         select GENERIC_CLOCKEVENTS
389         select MFD_SYSCON
390         help
391           Support for Cirrus Logic 711x/721x/731x based boards.
392 
393 config ARCH_GEMINI
394         bool "Cortina Systems Gemini"
395         select ARCH_REQUIRE_GPIOLIB
396         select CLKSRC_MMIO
397         select CPU_FA526
398         select GENERIC_CLOCKEVENTS
399         help
400           Support for the Cortina Systems Gemini family SoCs
401 
402 config ARCH_EBSA110
403         bool "EBSA-110"
404         select ARCH_USES_GETTIMEOFFSET
405         select CPU_SA110
406         select ISA
407         select NEED_MACH_IO_H
408         select NEED_MACH_MEMORY_H
409         select NO_IOPORT_MAP
410         help
411           This is an evaluation board for the StrongARM processor available
412           from Digital. It has limited hardware on-board, including an
413           Ethernet interface, two PCMCIA sockets, two serial ports and a
414           parallel port.
415 
416 config ARCH_EFM32
417         bool "Energy Micro efm32"
418         depends on !MMU
419         select ARCH_REQUIRE_GPIOLIB
420         select ARM_NVIC
421         select AUTO_ZRELADDR
422         select CLKSRC_OF
423         select COMMON_CLK
424         select CPU_V7M
425         select GENERIC_CLOCKEVENTS
426         select NO_DMA
427         select NO_IOPORT_MAP
428         select SPARSE_IRQ
429         select USE_OF
430         help
431           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
432           processors.
433 
434 config ARCH_EP93XX
435         bool "EP93xx-based"
436         select ARCH_HAS_HOLES_MEMORYMODEL
437         select ARCH_REQUIRE_GPIOLIB
438         select ARCH_USES_GETTIMEOFFSET
439         select ARM_AMBA
440         select ARM_VIC
441         select CLKDEV_LOOKUP
442         select CPU_ARM920T
443         help
444           This enables support for the Cirrus EP93xx series of CPUs.
445 
446 config ARCH_FOOTBRIDGE
447         bool "FootBridge"
448         select CPU_SA110
449         select FOOTBRIDGE
450         select GENERIC_CLOCKEVENTS
451         select HAVE_IDE
452         select NEED_MACH_IO_H if !MMU
453         select NEED_MACH_MEMORY_H
454         help
455           Support for systems based on the DC21285 companion chip
456           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
457 
458 config ARCH_NETX
459         bool "Hilscher NetX based"
460         select ARM_VIC
461         select CLKSRC_MMIO
462         select CPU_ARM926T
463         select GENERIC_CLOCKEVENTS
464         help
465           This enables support for systems based on the Hilscher NetX Soc
466 
467 config ARCH_IOP13XX
468         bool "IOP13xx-based"
469         depends on MMU
470         select CPU_XSC3
471         select NEED_MACH_MEMORY_H
472         select NEED_RET_TO_USER
473         select PCI
474         select PLAT_IOP
475         select VMSPLIT_1G
476         select SPARSE_IRQ
477         help
478           Support for Intel's IOP13XX (XScale) family of processors.
479 
480 config ARCH_IOP32X
481         bool "IOP32x-based"
482         depends on MMU
483         select ARCH_REQUIRE_GPIOLIB
484         select CPU_XSCALE
485         select GPIO_IOP
486         select NEED_RET_TO_USER
487         select PCI
488         select PLAT_IOP
489         help
490           Support for Intel's 80219 and IOP32X (XScale) family of
491           processors.
492 
493 config ARCH_IOP33X
494         bool "IOP33x-based"
495         depends on MMU
496         select ARCH_REQUIRE_GPIOLIB
497         select CPU_XSCALE
498         select GPIO_IOP
499         select NEED_RET_TO_USER
500         select PCI
501         select PLAT_IOP
502         help
503           Support for Intel's IOP33X (XScale) family of processors.
504 
505 config ARCH_IXP4XX
506         bool "IXP4xx-based"
507         depends on MMU
508         select ARCH_HAS_DMA_SET_COHERENT_MASK
509         select ARCH_REQUIRE_GPIOLIB
510         select ARCH_SUPPORTS_BIG_ENDIAN
511         select CLKSRC_MMIO
512         select CPU_XSCALE
513         select DMABOUNCE if PCI
514         select GENERIC_CLOCKEVENTS
515         select MIGHT_HAVE_PCI
516         select NEED_MACH_IO_H
517         select USB_EHCI_BIG_ENDIAN_DESC
518         select USB_EHCI_BIG_ENDIAN_MMIO
519         help
520           Support for Intel's IXP4XX (XScale) family of processors.
521 
522 config ARCH_DOVE
523         bool "Marvell Dove"
524         select ARCH_REQUIRE_GPIOLIB
525         select CPU_PJ4
526         select GENERIC_CLOCKEVENTS
527         select MIGHT_HAVE_PCI
528         select MVEBU_MBUS
529         select PINCTRL
530         select PINCTRL_DOVE
531         select PLAT_ORION_LEGACY
532         help
533           Support for the Marvell Dove SoC 88AP510
534 
535 config ARCH_MV78XX0
536         bool "Marvell MV78xx0"
537         select ARCH_REQUIRE_GPIOLIB
538         select CPU_FEROCEON
539         select GENERIC_CLOCKEVENTS
540         select MVEBU_MBUS
541         select PCI
542         select PLAT_ORION_LEGACY
543         help
544           Support for the following Marvell MV78xx0 series SoCs:
545           MV781x0, MV782x0.
546 
547 config ARCH_ORION5X
548         bool "Marvell Orion"
549         depends on MMU
550         select ARCH_REQUIRE_GPIOLIB
551         select CPU_FEROCEON
552         select GENERIC_CLOCKEVENTS
553         select MVEBU_MBUS
554         select PCI
555         select PLAT_ORION_LEGACY
556         help
557           Support for the following Marvell Orion 5x series SoCs:
558           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
559           Orion-2 (5281), Orion-1-90 (6183).
560 
561 config ARCH_MMP
562         bool "Marvell PXA168/910/MMP2"
563         depends on MMU
564         select ARCH_REQUIRE_GPIOLIB
565         select CLKDEV_LOOKUP
566         select GENERIC_ALLOCATOR
567         select GENERIC_CLOCKEVENTS
568         select GPIO_PXA
569         select IRQ_DOMAIN
570         select MULTI_IRQ_HANDLER
571         select PINCTRL
572         select PLAT_PXA
573         select SPARSE_IRQ
574         help
575           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
576 
577 config ARCH_KS8695
578         bool "Micrel/Kendin KS8695"
579         select ARCH_REQUIRE_GPIOLIB
580         select CLKSRC_MMIO
581         select CPU_ARM922T
582         select GENERIC_CLOCKEVENTS
583         select NEED_MACH_MEMORY_H
584         help
585           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
586           System-on-Chip devices.
587 
588 config ARCH_W90X900
589         bool "Nuvoton W90X900 CPU"
590         select ARCH_REQUIRE_GPIOLIB
591         select CLKDEV_LOOKUP
592         select CLKSRC_MMIO
593         select CPU_ARM926T
594         select GENERIC_CLOCKEVENTS
595         help
596           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
597           At present, the w90x900 has been renamed nuc900, regarding
598           the ARM series product line, you can login the following
599           link address to know more.
600 
601           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
602                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
603 
604 config ARCH_LPC32XX
605         bool "NXP LPC32XX"
606         select ARCH_REQUIRE_GPIOLIB
607         select ARM_AMBA
608         select CLKDEV_LOOKUP
609         select CLKSRC_MMIO
610         select CPU_ARM926T
611         select GENERIC_CLOCKEVENTS
612         select HAVE_IDE
613         select USE_OF
614         help
615           Support for the NXP LPC32XX family of processors
616 
617 config ARCH_PXA
618         bool "PXA2xx/PXA3xx-based"
619         depends on MMU
620         select ARCH_MTD_XIP
621         select ARCH_REQUIRE_GPIOLIB
622         select ARM_CPU_SUSPEND if PM
623         select AUTO_ZRELADDR
624         select CLKDEV_LOOKUP
625         select CLKSRC_MMIO
626         select CLKSRC_OF
627         select GENERIC_CLOCKEVENTS
628         select GPIO_PXA
629         select HAVE_IDE
630         select MULTI_IRQ_HANDLER
631         select PLAT_PXA
632         select SPARSE_IRQ
633         help
634           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
635 
636 config ARCH_MSM
637         bool "Qualcomm MSM (non-multiplatform)"
638         select ARCH_REQUIRE_GPIOLIB
639         select COMMON_CLK
640         select GENERIC_CLOCKEVENTS
641         help
642           Support for Qualcomm MSM/QSD based systems.  This runs on the
643           apps processor of the MSM/QSD and depends on a shared memory
644           interface to the modem processor which runs the baseband
645           stack and controls some vital subsystems
646           (clock and power control, etc).
647 
648 config ARCH_SHMOBILE_LEGACY
649         bool "Renesas ARM SoCs (non-multiplatform)"
650         select ARCH_SHMOBILE
651         select ARM_PATCH_PHYS_VIRT if MMU
652         select CLKDEV_LOOKUP
653         select GENERIC_CLOCKEVENTS
654         select HAVE_ARM_SCU if SMP
655         select HAVE_ARM_TWD if SMP
656         select HAVE_MACH_CLKDEV
657         select HAVE_SMP
658         select MIGHT_HAVE_CACHE_L2X0
659         select MULTI_IRQ_HANDLER
660         select NO_IOPORT_MAP
661         select PINCTRL
662         select PM_GENERIC_DOMAINS if PM
663         select SPARSE_IRQ
664         help
665           Support for Renesas ARM SoC platforms using a non-multiplatform
666           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
667           and RZ families.
668 
669 config ARCH_RPC
670         bool "RiscPC"
671         select ARCH_ACORN
672         select ARCH_MAY_HAVE_PC_FDC
673         select ARCH_SPARSEMEM_ENABLE
674         select ARCH_USES_GETTIMEOFFSET
675         select CPU_SA110
676         select FIQ
677         select HAVE_IDE
678         select HAVE_PATA_PLATFORM
679         select ISA_DMA_API
680         select NEED_MACH_IO_H
681         select NEED_MACH_MEMORY_H
682         select NO_IOPORT_MAP
683         select VIRT_TO_BUS
684         help
685           On the Acorn Risc-PC, Linux can support the internal IDE disk and
686           CD-ROM interface, serial and parallel port, and the floppy drive.
687 
688 config ARCH_SA1100
689         bool "SA1100-based"
690         select ARCH_MTD_XIP
691         select ARCH_REQUIRE_GPIOLIB
692         select ARCH_SPARSEMEM_ENABLE
693         select CLKDEV_LOOKUP
694         select CLKSRC_MMIO
695         select CPU_FREQ
696         select CPU_SA1100
697         select GENERIC_CLOCKEVENTS
698         select HAVE_IDE
699         select ISA
700         select NEED_MACH_MEMORY_H
701         select SPARSE_IRQ
702         help
703           Support for StrongARM 11x0 based boards.
704 
705 config ARCH_S3C24XX
706         bool "Samsung S3C24XX SoCs"
707         select ARCH_REQUIRE_GPIOLIB
708         select ATAGS
709         select CLKDEV_LOOKUP
710         select CLKSRC_SAMSUNG_PWM
711         select GENERIC_CLOCKEVENTS
712         select GPIO_SAMSUNG
713         select HAVE_S3C2410_I2C if I2C
714         select HAVE_S3C2410_WATCHDOG if WATCHDOG
715         select HAVE_S3C_RTC if RTC_CLASS
716         select MULTI_IRQ_HANDLER
717         select NEED_MACH_IO_H
718         select SAMSUNG_ATAGS
719         help
720           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
721           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
722           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
723           Samsung SMDK2410 development board (and derivatives).
724 
725 config ARCH_S3C64XX
726         bool "Samsung S3C64XX"
727         select ARCH_REQUIRE_GPIOLIB
728         select ARM_AMBA
729         select ARM_VIC
730         select ATAGS
731         select CLKDEV_LOOKUP
732         select CLKSRC_SAMSUNG_PWM
733         select COMMON_CLK_SAMSUNG
734         select CPU_V6K
735         select GENERIC_CLOCKEVENTS
736         select GPIO_SAMSUNG
737         select HAVE_S3C2410_I2C if I2C
738         select HAVE_S3C2410_WATCHDOG if WATCHDOG
739         select HAVE_TCM
740         select NO_IOPORT_MAP
741         select PLAT_SAMSUNG
742         select PM_GENERIC_DOMAINS if PM
743         select S3C_DEV_NAND
744         select S3C_GPIO_TRACK
745         select SAMSUNG_ATAGS
746         select SAMSUNG_WAKEMASK
747         select SAMSUNG_WDT_RESET
748         help
749           Samsung S3C64XX series based systems
750 
751 config ARCH_DAVINCI
752         bool "TI DaVinci"
753         select ARCH_HAS_HOLES_MEMORYMODEL
754         select ARCH_REQUIRE_GPIOLIB
755         select CLKDEV_LOOKUP
756         select GENERIC_ALLOCATOR
757         select GENERIC_CLOCKEVENTS
758         select GENERIC_IRQ_CHIP
759         select HAVE_IDE
760         select TI_PRIV_EDMA
761         select USE_OF
762         select ZONE_DMA
763         help
764           Support for TI's DaVinci platform.
765 
766 config ARCH_OMAP1
767         bool "TI OMAP1"
768         depends on MMU
769         select ARCH_HAS_HOLES_MEMORYMODEL
770         select ARCH_OMAP
771         select ARCH_REQUIRE_GPIOLIB
772         select CLKDEV_LOOKUP
773         select CLKSRC_MMIO
774         select GENERIC_CLOCKEVENTS
775         select GENERIC_IRQ_CHIP
776         select HAVE_IDE
777         select IRQ_DOMAIN
778         select NEED_MACH_IO_H if PCCARD
779         select NEED_MACH_MEMORY_H
780         help
781           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
782 
783 endchoice
784 
785 menu "Multiple platform selection"
786         depends on ARCH_MULTIPLATFORM
787 
788 comment "CPU Core family selection"
789 
790 config ARCH_MULTI_V4
791         bool "ARMv4 based platforms (FA526)"
792         depends on !ARCH_MULTI_V6_V7
793         select ARCH_MULTI_V4_V5
794         select CPU_FA526
795 
796 config ARCH_MULTI_V4T
797         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
798         depends on !ARCH_MULTI_V6_V7
799         select ARCH_MULTI_V4_V5
800         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
801                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
802                 CPU_ARM925T || CPU_ARM940T)
803 
804 config ARCH_MULTI_V5
805         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
806         depends on !ARCH_MULTI_V6_V7
807         select ARCH_MULTI_V4_V5
808         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
809                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
810                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
811 
812 config ARCH_MULTI_V4_V5
813         bool
814 
815 config ARCH_MULTI_V6
816         bool "ARMv6 based platforms (ARM11)"
817         select ARCH_MULTI_V6_V7
818         select CPU_V6K
819 
820 config ARCH_MULTI_V7
821         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
822         default y
823         select ARCH_MULTI_V6_V7
824         select CPU_V7
825         select HAVE_SMP
826 
827 config ARCH_MULTI_V6_V7
828         bool
829         select MIGHT_HAVE_CACHE_L2X0
830 
831 config ARCH_MULTI_CPU_AUTO
832         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
833         select ARCH_MULTI_V5
834 
835 endmenu
836 
837 config ARCH_VIRT
838         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
839         select ARM_AMBA
840         select ARM_GIC
841         select ARM_PSCI
842         select HAVE_ARM_ARCH_TIMER
843 
844 #
845 # This is sorted alphabetically by mach-* pathname.  However, plat-*
846 # Kconfigs may be included either alphabetically (according to the
847 # plat- suffix) or along side the corresponding mach-* source.
848 #
849 source "arch/arm/mach-mvebu/Kconfig"
850 
851 source "arch/arm/mach-at91/Kconfig"
852 
853 source "arch/arm/mach-axxia/Kconfig"
854 
855 source "arch/arm/mach-bcm/Kconfig"
856 
857 source "arch/arm/mach-berlin/Kconfig"
858 
859 source "arch/arm/mach-clps711x/Kconfig"
860 
861 source "arch/arm/mach-cns3xxx/Kconfig"
862 
863 source "arch/arm/mach-davinci/Kconfig"
864 
865 source "arch/arm/mach-dove/Kconfig"
866 
867 source "arch/arm/mach-ep93xx/Kconfig"
868 
869 source "arch/arm/mach-footbridge/Kconfig"
870 
871 source "arch/arm/mach-gemini/Kconfig"
872 
873 source "arch/arm/mach-highbank/Kconfig"
874 
875 source "arch/arm/mach-hisi/Kconfig"
876 
877 source "arch/arm/mach-integrator/Kconfig"
878 
879 source "arch/arm/mach-iop32x/Kconfig"
880 
881 source "arch/arm/mach-iop33x/Kconfig"
882 
883 source "arch/arm/mach-iop13xx/Kconfig"
884 
885 source "arch/arm/mach-ixp4xx/Kconfig"
886 
887 source "arch/arm/mach-keystone/Kconfig"
888 
889 source "arch/arm/mach-ks8695/Kconfig"
890 
891 source "arch/arm/mach-msm/Kconfig"
892 
893 source "arch/arm/mach-moxart/Kconfig"
894 
895 source "arch/arm/mach-mv78xx0/Kconfig"
896 
897 source "arch/arm/mach-imx/Kconfig"
898 
899 source "arch/arm/mach-mediatek/Kconfig"
900 
901 source "arch/arm/mach-mxs/Kconfig"
902 
903 source "arch/arm/mach-netx/Kconfig"
904 
905 source "arch/arm/mach-nomadik/Kconfig"
906 
907 source "arch/arm/mach-nspire/Kconfig"
908 
909 source "arch/arm/plat-omap/Kconfig"
910 
911 source "arch/arm/mach-omap1/Kconfig"
912 
913 source "arch/arm/mach-omap2/Kconfig"
914 
915 source "arch/arm/mach-orion5x/Kconfig"
916 
917 source "arch/arm/mach-picoxcell/Kconfig"
918 
919 source "arch/arm/mach-pxa/Kconfig"
920 source "arch/arm/plat-pxa/Kconfig"
921 
922 source "arch/arm/mach-mmp/Kconfig"
923 
924 source "arch/arm/mach-qcom/Kconfig"
925 
926 source "arch/arm/mach-realview/Kconfig"
927 
928 source "arch/arm/mach-rockchip/Kconfig"
929 
930 source "arch/arm/mach-sa1100/Kconfig"
931 
932 source "arch/arm/mach-socfpga/Kconfig"
933 
934 source "arch/arm/mach-spear/Kconfig"
935 
936 source "arch/arm/mach-sti/Kconfig"
937 
938 source "arch/arm/mach-s3c24xx/Kconfig"
939 
940 source "arch/arm/mach-s3c64xx/Kconfig"
941 
942 source "arch/arm/mach-s5pv210/Kconfig"
943 
944 source "arch/arm/mach-exynos/Kconfig"
945 source "arch/arm/plat-samsung/Kconfig"
946 
947 source "arch/arm/mach-shmobile/Kconfig"
948 
949 source "arch/arm/mach-sunxi/Kconfig"
950 
951 source "arch/arm/mach-prima2/Kconfig"
952 
953 source "arch/arm/mach-tegra/Kconfig"
954 
955 source "arch/arm/mach-u300/Kconfig"
956 
957 source "arch/arm/mach-ux500/Kconfig"
958 
959 source "arch/arm/mach-versatile/Kconfig"
960 
961 source "arch/arm/mach-vexpress/Kconfig"
962 source "arch/arm/plat-versatile/Kconfig"
963 
964 source "arch/arm/mach-vt8500/Kconfig"
965 
966 source "arch/arm/mach-w90x900/Kconfig"
967 
968 source "arch/arm/mach-zynq/Kconfig"
969 
970 # Definitions to make life easier
971 config ARCH_ACORN
972         bool
973 
974 config PLAT_IOP
975         bool
976         select GENERIC_CLOCKEVENTS
977 
978 config PLAT_ORION
979         bool
980         select CLKSRC_MMIO
981         select COMMON_CLK
982         select GENERIC_IRQ_CHIP
983         select IRQ_DOMAIN
984 
985 config PLAT_ORION_LEGACY
986         bool
987         select PLAT_ORION
988 
989 config PLAT_PXA
990         bool
991 
992 config PLAT_VERSATILE
993         bool
994 
995 config ARM_TIMER_SP804
996         bool
997         select CLKSRC_MMIO
998         select CLKSRC_OF if OF
999 
1000 source "arch/arm/firmware/Kconfig"
1001 
1002 source arch/arm/mm/Kconfig
1003 
1004 config IWMMXT
1005         bool "Enable iWMMXt support"
1006         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
1007         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
1008         help
1009           Enable support for iWMMXt context switching at run time if
1010           running on a CPU that supports it.
1011 
1012 config MULTI_IRQ_HANDLER
1013         bool
1014         help
1015           Allow each machine to specify it's own IRQ handler at run time.
1016 
1017 if !MMU
1018 source "arch/arm/Kconfig-nommu"
1019 endif
1020 
1021 config PJ4B_ERRATA_4742
1022         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1023         depends on CPU_PJ4B && MACH_ARMADA_370
1024         default y
1025         help
1026           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1027           Event (WFE) IDLE states, a specific timing sensitivity exists between
1028           the retiring WFI/WFE instructions and the newly issued subsequent
1029           instructions.  This sensitivity can result in a CPU hang scenario.
1030           Workaround:
1031           The software must insert either a Data Synchronization Barrier (DSB)
1032           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1033           instruction
1034 
1035 config ARM_ERRATA_326103
1036         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1037         depends on CPU_V6
1038         help
1039           Executing a SWP instruction to read-only memory does not set bit 11
1040           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1041           treat the access as a read, preventing a COW from occurring and
1042           causing the faulting task to livelock.
1043 
1044 config ARM_ERRATA_411920
1045         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1046         depends on CPU_V6 || CPU_V6K
1047         help
1048           Invalidation of the Instruction Cache operation can
1049           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1050           It does not affect the MPCore. This option enables the ARM Ltd.
1051           recommended workaround.
1052 
1053 config ARM_ERRATA_430973
1054         bool "ARM errata: Stale prediction on replaced interworking branch"
1055         depends on CPU_V7
1056         help
1057           This option enables the workaround for the 430973 Cortex-A8
1058           (r1p0..r1p2) erratum. If a code sequence containing an ARM/Thumb
1059           interworking branch is replaced with another code sequence at the
1060           same virtual address, whether due to self-modifying code or virtual
1061           to physical address re-mapping, Cortex-A8 does not recover from the
1062           stale interworking branch prediction. This results in Cortex-A8
1063           executing the new code sequence in the incorrect ARM or Thumb state.
1064           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1065           and also flushes the branch target cache at every context switch.
1066           Note that setting specific bits in the ACTLR register may not be
1067           available in non-secure mode.
1068 
1069 config ARM_ERRATA_458693
1070         bool "ARM errata: Processor deadlock when a false hazard is created"
1071         depends on CPU_V7
1072         depends on !ARCH_MULTIPLATFORM
1073         help
1074           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1075           erratum. For very specific sequences of memory operations, it is
1076           possible for a hazard condition intended for a cache line to instead
1077           be incorrectly associated with a different cache line. This false
1078           hazard might then cause a processor deadlock. The workaround enables
1079           the L1 caching of the NEON accesses and disables the PLD instruction
1080           in the ACTLR register. Note that setting specific bits in the ACTLR
1081           register may not be available in non-secure mode.
1082 
1083 config ARM_ERRATA_460075
1084         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1085         depends on CPU_V7
1086         depends on !ARCH_MULTIPLATFORM
1087         help
1088           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1089           erratum. Any asynchronous access to the L2 cache may encounter a
1090           situation in which recent store transactions to the L2 cache are lost
1091           and overwritten with stale memory contents from external memory. The
1092           workaround disables the write-allocate mode for the L2 cache via the
1093           ACTLR register. Note that setting specific bits in the ACTLR register
1094           may not be available in non-secure mode.
1095 
1096 config ARM_ERRATA_742230
1097         bool "ARM errata: DMB operation may be faulty"
1098         depends on CPU_V7 && SMP
1099         depends on !ARCH_MULTIPLATFORM
1100         help
1101           This option enables the workaround for the 742230 Cortex-A9
1102           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1103           between two write operations may not ensure the correct visibility
1104           ordering of the two writes. This workaround sets a specific bit in
1105           the diagnostic register of the Cortex-A9 which causes the DMB
1106           instruction to behave as a DSB, ensuring the correct behaviour of
1107           the two writes.
1108 
1109 config ARM_ERRATA_742231
1110         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1111         depends on CPU_V7 && SMP
1112         depends on !ARCH_MULTIPLATFORM
1113         help
1114           This option enables the workaround for the 742231 Cortex-A9
1115           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1116           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1117           accessing some data located in the same cache line, may get corrupted
1118           data due to bad handling of the address hazard when the line gets
1119           replaced from one of the CPUs at the same time as another CPU is
1120           accessing it. This workaround sets specific bits in the diagnostic
1121           register of the Cortex-A9 which reduces the linefill issuing
1122           capabilities of the processor.
1123 
1124 config ARM_ERRATA_643719
1125         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1126         depends on CPU_V7 && SMP
1127         help
1128           This option enables the workaround for the 643719 Cortex-A9 (prior to
1129           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1130           register returns zero when it should return one. The workaround
1131           corrects this value, ensuring cache maintenance operations which use
1132           it behave as intended and avoiding data corruption.
1133 
1134 config ARM_ERRATA_720789
1135         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1136         depends on CPU_V7
1137         help
1138           This option enables the workaround for the 720789 Cortex-A9 (prior to
1139           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1140           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1141           As a consequence of this erratum, some TLB entries which should be
1142           invalidated are not, resulting in an incoherency in the system page
1143           tables. The workaround changes the TLB flushing routines to invalidate
1144           entries regardless of the ASID.
1145 
1146 config ARM_ERRATA_743622
1147         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1148         depends on CPU_V7
1149         depends on !ARCH_MULTIPLATFORM
1150         help
1151           This option enables the workaround for the 743622 Cortex-A9
1152           (r2p*) erratum. Under very rare conditions, a faulty
1153           optimisation in the Cortex-A9 Store Buffer may lead to data
1154           corruption. This workaround sets a specific bit in the diagnostic
1155           register of the Cortex-A9 which disables the Store Buffer
1156           optimisation, preventing the defect from occurring. This has no
1157           visible impact on the overall performance or power consumption of the
1158           processor.
1159 
1160 config ARM_ERRATA_751472
1161         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1162         depends on CPU_V7
1163         depends on !ARCH_MULTIPLATFORM
1164         help
1165           This option enables the workaround for the 751472 Cortex-A9 (prior
1166           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1167           completion of a following broadcasted operation if the second
1168           operation is received by a CPU before the ICIALLUIS has completed,
1169           potentially leading to corrupted entries in the cache or TLB.
1170 
1171 config ARM_ERRATA_754322
1172         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1173         depends on CPU_V7
1174         help
1175           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1176           r3p*) erratum. A speculative memory access may cause a page table walk
1177           which starts prior to an ASID switch but completes afterwards. This
1178           can populate the micro-TLB with a stale entry which may be hit with
1179           the new ASID. This workaround places two dsb instructions in the mm
1180           switching code so that no page table walks can cross the ASID switch.
1181 
1182 config ARM_ERRATA_754327
1183         bool "ARM errata: no automatic Store Buffer drain"
1184         depends on CPU_V7 && SMP
1185         help
1186           This option enables the workaround for the 754327 Cortex-A9 (prior to
1187           r2p0) erratum. The Store Buffer does not have any automatic draining
1188           mechanism and therefore a livelock may occur if an external agent
1189           continuously polls a memory location waiting to observe an update.
1190           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1191           written polling loops from denying visibility of updates to memory.
1192 
1193 config ARM_ERRATA_364296
1194         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1195         depends on CPU_V6
1196         help
1197           This options enables the workaround for the 364296 ARM1136
1198           r0p2 erratum (possible cache data corruption with
1199           hit-under-miss enabled). It sets the undocumented bit 31 in
1200           the auxiliary control register and the FI bit in the control
1201           register, thus disabling hit-under-miss without putting the
1202           processor into full low interrupt latency mode. ARM11MPCore
1203           is not affected.
1204 
1205 config ARM_ERRATA_764369
1206         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1207         depends on CPU_V7 && SMP
1208         help
1209           This option enables the workaround for erratum 764369
1210           affecting Cortex-A9 MPCore with two or more processors (all
1211           current revisions). Under certain timing circumstances, a data
1212           cache line maintenance operation by MVA targeting an Inner
1213           Shareable memory region may fail to proceed up to either the
1214           Point of Coherency or to the Point of Unification of the
1215           system. This workaround adds a DSB instruction before the
1216           relevant cache maintenance functions and sets a specific bit
1217           in the diagnostic control register of the SCU.
1218 
1219 config ARM_ERRATA_775420
1220        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1221        depends on CPU_V7
1222        help
1223          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1224          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1225          operation aborts with MMU exception, it might cause the processor
1226          to deadlock. This workaround puts DSB before executing ISB if
1227          an abort may occur on cache maintenance.
1228 
1229 config ARM_ERRATA_798181
1230         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1231         depends on CPU_V7 && SMP
1232         help
1233           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1234           adequately shooting down all use of the old entries. This
1235           option enables the Linux kernel workaround for this erratum
1236           which sends an IPI to the CPUs that are running the same ASID
1237           as the one being invalidated.
1238 
1239 config ARM_ERRATA_773022
1240         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1241         depends on CPU_V7
1242         help
1243           This option enables the workaround for the 773022 Cortex-A15
1244           (up to r0p4) erratum. In certain rare sequences of code, the
1245           loop buffer may deliver incorrect instructions. This
1246           workaround disables the loop buffer to avoid the erratum.
1247 
1248 endmenu
1249 
1250 source "arch/arm/common/Kconfig"
1251 
1252 menu "Bus support"
1253 
1254 config ARM_AMBA
1255         bool
1256 
1257 config ISA
1258         bool
1259         help
1260           Find out whether you have ISA slots on your motherboard.  ISA is the
1261           name of a bus system, i.e. the way the CPU talks to the other stuff
1262           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1263           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1264           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1265 
1266 # Select ISA DMA controller support
1267 config ISA_DMA
1268         bool
1269         select ISA_DMA_API
1270 
1271 # Select ISA DMA interface
1272 config ISA_DMA_API
1273         bool
1274 
1275 config PCI
1276         bool "PCI support" if MIGHT_HAVE_PCI
1277         help
1278           Find out whether you have a PCI motherboard. PCI is the name of a
1279           bus system, i.e. the way the CPU talks to the other stuff inside
1280           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1281           VESA. If you have PCI, say Y, otherwise N.
1282 
1283 config PCI_DOMAINS
1284         bool
1285         depends on PCI
1286 
1287 config PCI_NANOENGINE
1288         bool "BSE nanoEngine PCI support"
1289         depends on SA1100_NANOENGINE
1290         help
1291           Enable PCI on the BSE nanoEngine board.
1292 
1293 config PCI_SYSCALL
1294         def_bool PCI
1295 
1296 config PCI_HOST_ITE8152
1297         bool
1298         depends on PCI && MACH_ARMCORE
1299         default y
1300         select DMABOUNCE
1301 
1302 source "drivers/pci/Kconfig"
1303 source "drivers/pci/pcie/Kconfig"
1304 
1305 source "drivers/pcmcia/Kconfig"
1306 
1307 endmenu
1308 
1309 menu "Kernel Features"
1310 
1311 config HAVE_SMP
1312         bool
1313         help
1314           This option should be selected by machines which have an SMP-
1315           capable CPU.
1316 
1317           The only effect of this option is to make the SMP-related
1318           options available to the user for configuration.
1319 
1320 config SMP
1321         bool "Symmetric Multi-Processing"
1322         depends on CPU_V6K || CPU_V7
1323         depends on GENERIC_CLOCKEVENTS
1324         depends on HAVE_SMP
1325         depends on MMU || ARM_MPU
1326         help
1327           This enables support for systems with more than one CPU. If you have
1328           a system with only one CPU, say N. If you have a system with more
1329           than one CPU, say Y.
1330 
1331           If you say N here, the kernel will run on uni- and multiprocessor
1332           machines, but will use only one CPU of a multiprocessor machine. If
1333           you say Y here, the kernel will run on many, but not all,
1334           uniprocessor machines. On a uniprocessor machine, the kernel
1335           will run faster if you say N here.
1336 
1337           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1338           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1339           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1340 
1341           If you don't know what to do here, say N.
1342 
1343 config SMP_ON_UP
1344         bool "Allow booting SMP kernel on uniprocessor systems (EXPERIMENTAL)"
1345         depends on SMP && !XIP_KERNEL && MMU
1346         default y
1347         help
1348           SMP kernels contain instructions which fail on non-SMP processors.
1349           Enabling this option allows the kernel to modify itself to make
1350           these instructions safe.  Disabling it allows about 1K of space
1351           savings.
1352 
1353           If you don't know what to do here, say Y.
1354 
1355 config ARM_CPU_TOPOLOGY
1356         bool "Support cpu topology definition"
1357         depends on SMP && CPU_V7
1358         default y
1359         help
1360           Support ARM cpu topology definition. The MPIDR register defines
1361           affinity between processors which is then used to describe the cpu
1362           topology of an ARM System.
1363 
1364 config SCHED_MC
1365         bool "Multi-core scheduler support"
1366         depends on ARM_CPU_TOPOLOGY
1367         help
1368           Multi-core scheduler support improves the CPU scheduler's decision
1369           making when dealing with multi-core CPU chips at a cost of slightly
1370           increased overhead in some places. If unsure say N here.
1371 
1372 config SCHED_SMT
1373         bool "SMT scheduler support"
1374         depends on ARM_CPU_TOPOLOGY
1375         help
1376           Improves the CPU scheduler's decision making when dealing with
1377           MultiThreading at a cost of slightly increased overhead in some
1378           places. If unsure say N here.
1379 
1380 config HAVE_ARM_SCU
1381         bool
1382         help
1383           This option enables support for the ARM system coherency unit
1384 
1385 config HAVE_ARM_ARCH_TIMER
1386         bool "Architected timer support"
1387         depends on CPU_V7
1388         select ARM_ARCH_TIMER
1389         select GENERIC_CLOCKEVENTS
1390         help
1391           This option enables support for the ARM architected timer
1392 
1393 config HAVE_ARM_TWD
1394         bool
1395         depends on SMP
1396         select CLKSRC_OF if OF
1397         help
1398           This options enables support for the ARM timer and watchdog unit
1399 
1400 config MCPM
1401         bool "Multi-Cluster Power Management"
1402         depends on CPU_V7 && SMP
1403         help
1404           This option provides the common power management infrastructure
1405           for (multi-)cluster based systems, such as big.LITTLE based
1406           systems.
1407 
1408 config BIG_LITTLE
1409         bool "big.LITTLE support (Experimental)"
1410         depends on CPU_V7 && SMP
1411         select MCPM
1412         help
1413           This option enables support selections for the big.LITTLE
1414           system architecture.
1415 
1416 config BL_SWITCHER
1417         bool "big.LITTLE switcher support"
1418         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1419         select ARM_CPU_SUSPEND
1420         select CPU_PM
1421         help
1422           The big.LITTLE "switcher" provides the core functionality to
1423           transparently handle transition between a cluster of A15's
1424           and a cluster of A7's in a big.LITTLE system.
1425 
1426 config BL_SWITCHER_DUMMY_IF
1427         tristate "Simple big.LITTLE switcher user interface"
1428         depends on BL_SWITCHER && DEBUG_KERNEL
1429         help
1430           This is a simple and dummy char dev interface to control
1431           the big.LITTLE switcher core code.  It is meant for
1432           debugging purposes only.
1433 
1434 choice
1435         prompt "Memory split"
1436         depends on MMU
1437         default VMSPLIT_3G
1438         help
1439           Select the desired split between kernel and user memory.
1440 
1441           If you are not absolutely sure what you are doing, leave this
1442           option alone!
1443 
1444         config VMSPLIT_3G
1445                 bool "3G/1G user/kernel split"
1446         config VMSPLIT_2G
1447                 bool "2G/2G user/kernel split"
1448         config VMSPLIT_1G
1449                 bool "1G/3G user/kernel split"
1450 endchoice
1451 
1452 config PAGE_OFFSET
1453         hex
1454         default PHYS_OFFSET if !MMU
1455         default 0x40000000 if VMSPLIT_1G
1456         default 0x80000000 if VMSPLIT_2G
1457         default 0xC0000000
1458 
1459 config NR_CPUS
1460         int "Maximum number of CPUs (2-32)"
1461         range 2 32
1462         depends on SMP
1463         default "4"
1464 
1465 config HOTPLUG_CPU
1466         bool "Support for hot-pluggable CPUs"
1467         depends on SMP
1468         help
1469           Say Y here to experiment with turning CPUs off and on.  CPUs
1470           can be controlled through /sys/devices/system/cpu.
1471 
1472 config ARM_PSCI
1473         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1474         depends on CPU_V7
1475         help
1476           Say Y here if you want Linux to communicate with system firmware
1477           implementing the PSCI specification for CPU-centric power
1478           management operations described in ARM document number ARM DEN
1479           0022A ("Power State Coordination Interface System Software on
1480           ARM processors").
1481 
1482 # The GPIO number here must be sorted by descending number. In case of
1483 # a multiplatform kernel, we just want the highest value required by the
1484 # selected platforms.
1485 config ARCH_NR_GPIO
1486         int
1487         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA
1488         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1489                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1490         default 416 if ARCH_SUNXI
1491         default 392 if ARCH_U8500
1492         default 352 if ARCH_VT8500
1493         default 288 if ARCH_ROCKCHIP
1494         default 264 if MACH_H4700
1495         default 0
1496         help
1497           Maximum number of GPIOs in the system.
1498 
1499           If unsure, leave the default value.
1500 
1501 source kernel/Kconfig.preempt
1502 
1503 config HZ_FIXED
1504         int
1505         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1506                 ARCH_S5PV210 || ARCH_EXYNOS4
1507         default AT91_TIMER_HZ if ARCH_AT91
1508         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1509         default 0
1510 
1511 choice
1512         depends on HZ_FIXED = 0
1513         prompt "Timer frequency"
1514 
1515 config HZ_100
1516         bool "100 Hz"
1517 
1518 config HZ_200
1519         bool "200 Hz"
1520 
1521 config HZ_250
1522         bool "250 Hz"
1523 
1524 config HZ_300
1525         bool "300 Hz"
1526 
1527 config HZ_500
1528         bool "500 Hz"
1529 
1530 config HZ_1000
1531         bool "1000 Hz"
1532 
1533 endchoice
1534 
1535 config HZ
1536         int
1537         default HZ_FIXED if HZ_FIXED != 0
1538         default 100 if HZ_100
1539         default 200 if HZ_200
1540         default 250 if HZ_250
1541         default 300 if HZ_300
1542         default 500 if HZ_500
1543         default 1000
1544 
1545 config SCHED_HRTICK
1546         def_bool HIGH_RES_TIMERS
1547 
1548 config THUMB2_KERNEL
1549         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1550         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1551         default y if CPU_THUMBONLY
1552         select AEABI
1553         select ARM_ASM_UNIFIED
1554         select ARM_UNWIND
1555         help
1556           By enabling this option, the kernel will be compiled in
1557           Thumb-2 mode. A compiler/assembler that understand the unified
1558           ARM-Thumb syntax is needed.
1559 
1560           If unsure, say N.
1561 
1562 config THUMB2_AVOID_R_ARM_THM_JUMP11
1563         bool "Work around buggy Thumb-2 short branch relocations in gas"
1564         depends on THUMB2_KERNEL && MODULES
1565         default y
1566         help
1567           Various binutils versions can resolve Thumb-2 branches to
1568           locally-defined, preemptible global symbols as short-range "b.n"
1569           branch instructions.
1570 
1571           This is a problem, because there's no guarantee the final
1572           destination of the symbol, or any candidate locations for a
1573           trampoline, are within range of the branch.  For this reason, the
1574           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1575           relocation in modules at all, and it makes little sense to add
1576           support.
1577 
1578           The symptom is that the kernel fails with an "unsupported
1579           relocation" error when loading some modules.
1580 
1581           Until fixed tools are available, passing
1582           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1583           code which hits this problem, at the cost of a bit of extra runtime
1584           stack usage in some cases.
1585 
1586           The problem is described in more detail at:
1587               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1588 
1589           Only Thumb-2 kernels are affected.
1590 
1591           Unless you are sure your tools don't have this problem, say Y.
1592 
1593 config ARM_ASM_UNIFIED
1594         bool
1595 
1596 config AEABI
1597         bool "Use the ARM EABI to compile the kernel"
1598         help
1599           This option allows for the kernel to be compiled using the latest
1600           ARM ABI (aka EABI).  This is only useful if you are using a user
1601           space environment that is also compiled with EABI.
1602 
1603           Since there are major incompatibilities between the legacy ABI and
1604           EABI, especially with regard to structure member alignment, this
1605           option also changes the kernel syscall calling convention to
1606           disambiguate both ABIs and allow for backward compatibility support
1607           (selected with CONFIG_OABI_COMPAT).
1608 
1609           To use this you need GCC version 4.0.0 or later.
1610 
1611 config OABI_COMPAT
1612         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1613         depends on AEABI && !THUMB2_KERNEL
1614         help
1615           This option preserves the old syscall interface along with the
1616           new (ARM EABI) one. It also provides a compatibility layer to
1617           intercept syscalls that have structure arguments which layout
1618           in memory differs between the legacy ABI and the new ARM EABI
1619           (only for non "thumb" binaries). This option adds a tiny
1620           overhead to all syscalls and produces a slightly larger kernel.
1621 
1622           The seccomp filter system will not be available when this is
1623           selected, since there is no way yet to sensibly distinguish
1624           between calling conventions during filtering.
1625 
1626           If you know you'll be using only pure EABI user space then you
1627           can say N here. If this option is not selected and you attempt
1628           to execute a legacy ABI binary then the result will be
1629           UNPREDICTABLE (in fact it can be predicted that it won't work
1630           at all). If in doubt say N.
1631 
1632 config ARCH_HAS_HOLES_MEMORYMODEL
1633         bool
1634 
1635 config ARCH_SPARSEMEM_ENABLE
1636         bool
1637 
1638 config ARCH_SPARSEMEM_DEFAULT
1639         def_bool ARCH_SPARSEMEM_ENABLE
1640 
1641 config ARCH_SELECT_MEMORY_MODEL
1642         def_bool ARCH_SPARSEMEM_ENABLE
1643 
1644 config HAVE_ARCH_PFN_VALID
1645         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1646 
1647 config HIGHMEM
1648         bool "High Memory Support"
1649         depends on MMU
1650         help
1651           The address space of ARM processors is only 4 Gigabytes large
1652           and it has to accommodate user address space, kernel address
1653           space as well as some memory mapped IO. That means that, if you
1654           have a large amount of physical memory and/or IO, not all of the
1655           memory can be "permanently mapped" by the kernel. The physical
1656           memory that is not permanently mapped is called "high memory".
1657 
1658           Depending on the selected kernel/user memory split, minimum
1659           vmalloc space and actual amount of RAM, you may not need this
1660           option which should result in a slightly faster kernel.
1661 
1662           If unsure, say n.
1663 
1664 config HIGHPTE
1665         bool "Allocate 2nd-level pagetables from highmem"
1666         depends on HIGHMEM
1667 
1668 config HW_PERF_EVENTS
1669         bool "Enable hardware performance counter support for perf events"
1670         depends on PERF_EVENTS
1671         default y
1672         help
1673           Enable hardware performance counter support for perf events. If
1674           disabled, perf events will use software events only.
1675 
1676 config SYS_SUPPORTS_HUGETLBFS
1677        def_bool y
1678        depends on ARM_LPAE
1679 
1680 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1681        def_bool y
1682        depends on ARM_LPAE
1683 
1684 config ARCH_WANT_GENERAL_HUGETLB
1685         def_bool y
1686 
1687 source "mm/Kconfig"
1688 
1689 config FORCE_MAX_ZONEORDER
1690         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1691         range 11 64 if ARCH_SHMOBILE_LEGACY
1692         default "12" if SOC_AM33XX
1693         default "9" if SA1111 || ARCH_EFM32
1694         default "11"
1695         help
1696           The kernel memory allocator divides physically contiguous memory
1697           blocks into "zones", where each zone is a power of two number of
1698           pages.  This option selects the largest power of two that the kernel
1699           keeps in the memory allocator.  If you need to allocate very large
1700           blocks of physically contiguous memory, then you may need to
1701           increase this value.
1702 
1703           This config option is actually maximum order plus one. For example,
1704           a value of 11 means that the largest free memory block is 2^10 pages.
1705 
1706 config ALIGNMENT_TRAP
1707         bool
1708         depends on CPU_CP15_MMU
1709         default y if !ARCH_EBSA110
1710         select HAVE_PROC_CPU if PROC_FS
1711         help
1712           ARM processors cannot fetch/store information which is not
1713           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1714           address divisible by 4. On 32-bit ARM processors, these non-aligned
1715           fetch/store instructions will be emulated in software if you say
1716           here, which has a severe performance impact. This is necessary for
1717           correct operation of some network protocols. With an IP-only
1718           configuration it is safe to say N, otherwise say Y.
1719 
1720 config UACCESS_WITH_MEMCPY
1721         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1722         depends on MMU
1723         default y if CPU_FEROCEON
1724         help
1725           Implement faster copy_to_user and clear_user methods for CPU
1726           cores where a 8-word STM instruction give significantly higher
1727           memory write throughput than a sequence of individual 32bit stores.
1728 
1729           A possible side effect is a slight increase in scheduling latency
1730           between threads sharing the same address space if they invoke
1731           such copy operations with large buffers.
1732 
1733           However, if the CPU data cache is using a write-allocate mode,
1734           this option is unlikely to provide any performance gain.
1735 
1736 config SECCOMP
1737         bool
1738         prompt "Enable seccomp to safely compute untrusted bytecode"
1739         ---help---
1740           This kernel feature is useful for number crunching applications
1741           that may need to compute untrusted bytecode during their
1742           execution. By using pipes or other transports made available to
1743           the process as file descriptors supporting the read/write
1744           syscalls, it's possible to isolate those applications in
1745           their own address space using seccomp. Once seccomp is
1746           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1747           and the task is only allowed to execute a few safe syscalls
1748           defined by each seccomp mode.
1749 
1750 config SWIOTLB
1751         def_bool y
1752 
1753 config IOMMU_HELPER
1754         def_bool SWIOTLB
1755 
1756 config XEN_DOM0
1757         def_bool y
1758         depends on XEN
1759 
1760 config XEN
1761         bool "Xen guest support on ARM (EXPERIMENTAL)"
1762         depends on ARM && AEABI && OF
1763         depends on CPU_V7 && !CPU_V6
1764         depends on !GENERIC_ATOMIC64
1765         depends on MMU
1766         select ARCH_DMA_ADDR_T_64BIT
1767         select ARM_PSCI
1768         select SWIOTLB_XEN
1769         help
1770           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1771 
1772 endmenu
1773 
1774 menu "Boot options"
1775 
1776 config USE_OF
1777         bool "Flattened Device Tree support"
1778         select IRQ_DOMAIN
1779         select OF
1780         select OF_EARLY_FLATTREE
1781         select OF_RESERVED_MEM
1782         help
1783           Include support for flattened device tree machine descriptions.
1784 
1785 config ATAGS
1786         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1787         default y
1788         help
1789           This is the traditional way of passing data to the kernel at boot
1790           time. If you are solely relying on the flattened device tree (or
1791           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1792           to remove ATAGS support from your kernel binary.  If unsure,
1793           leave this to y.
1794 
1795 config DEPRECATED_PARAM_STRUCT
1796         bool "Provide old way to pass kernel parameters"
1797         depends on ATAGS
1798         help
1799           This was deprecated in 2001 and announced to live on for 5 years.
1800           Some old boot loaders still use this way.
1801 
1802 # Compressed boot loader in ROM.  Yes, we really want to ask about
1803 # TEXT and BSS so we preserve their values in the config files.
1804 config ZBOOT_ROM_TEXT
1805         hex "Compressed ROM boot loader base address"
1806         default "0"
1807         help
1808           The physical address at which the ROM-able zImage is to be
1809           placed in the target.  Platforms which normally make use of
1810           ROM-able zImage formats normally set this to a suitable
1811           value in their defconfig file.
1812 
1813           If ZBOOT_ROM is not enabled, this has no effect.
1814 
1815 config ZBOOT_ROM_BSS
1816         hex "Compressed ROM boot loader BSS address"
1817         default "0"
1818         help
1819           The base address of an area of read/write memory in the target
1820           for the ROM-able zImage which must be available while the
1821           decompressor is running. It must be large enough to hold the
1822           entire decompressed kernel plus an additional 128 KiB.
1823           Platforms which normally make use of ROM-able zImage formats
1824           normally set this to a suitable value in their defconfig file.
1825 
1826           If ZBOOT_ROM is not enabled, this has no effect.
1827 
1828 config ZBOOT_ROM
1829         bool "Compressed boot loader in ROM/flash"
1830         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1831         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1832         help
1833           Say Y here if you intend to execute your compressed kernel image
1834           (zImage) directly from ROM or flash.  If unsure, say N.
1835 
1836 choice
1837         prompt "Include SD/MMC loader in zImage (EXPERIMENTAL)"
1838         depends on ZBOOT_ROM && ARCH_SH7372
1839         default ZBOOT_ROM_NONE
1840         help
1841           Include experimental SD/MMC loading code in the ROM-able zImage.
1842           With this enabled it is possible to write the ROM-able zImage
1843           kernel image to an MMC or SD card and boot the kernel straight
1844           from the reset vector. At reset the processor Mask ROM will load
1845           the first part of the ROM-able zImage which in turn loads the
1846           rest the kernel image to RAM.
1847 
1848 config ZBOOT_ROM_NONE
1849         bool "No SD/MMC loader in zImage (EXPERIMENTAL)"
1850         help
1851           Do not load image from SD or MMC
1852 
1853 config ZBOOT_ROM_MMCIF
1854         bool "Include MMCIF loader in zImage (EXPERIMENTAL)"
1855         help
1856           Load image from MMCIF hardware block.
1857 
1858 config ZBOOT_ROM_SH_MOBILE_SDHI
1859         bool "Include SuperH Mobile SDHI loader in zImage (EXPERIMENTAL)"
1860         help
1861           Load image from SDHI hardware block
1862 
1863 endchoice
1864 
1865 config ARM_APPENDED_DTB
1866         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1867         depends on OF
1868         help
1869           With this option, the boot code will look for a device tree binary
1870           (DTB) appended to zImage
1871           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1872 
1873           This is meant as a backward compatibility convenience for those
1874           systems with a bootloader that can't be upgraded to accommodate
1875           the documented boot protocol using a device tree.
1876 
1877           Beware that there is very little in terms of protection against
1878           this option being confused by leftover garbage in memory that might
1879           look like a DTB header after a reboot if no actual DTB is appended
1880           to zImage.  Do not leave this option active in a production kernel
1881           if you don't intend to always append a DTB.  Proper passing of the
1882           location into r2 of a bootloader provided DTB is always preferable
1883           to this option.
1884 
1885 config ARM_ATAG_DTB_COMPAT
1886         bool "Supplement the appended DTB with traditional ATAG information"
1887         depends on ARM_APPENDED_DTB
1888         help
1889           Some old bootloaders can't be updated to a DTB capable one, yet
1890           they provide ATAGs with memory configuration, the ramdisk address,
1891           the kernel cmdline string, etc.  Such information is dynamically
1892           provided by the bootloader and can't always be stored in a static
1893           DTB.  To allow a device tree enabled kernel to be used with such
1894           bootloaders, this option allows zImage to extract the information
1895           from the ATAG list and store it at run time into the appended DTB.
1896 
1897 choice
1898         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1899         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1900 
1901 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1902         bool "Use bootloader kernel arguments if available"
1903         help
1904           Uses the command-line options passed by the boot loader instead of
1905           the device tree bootargs property. If the boot loader doesn't provide
1906           any, the device tree bootargs property will be used.
1907 
1908 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1909         bool "Extend with bootloader kernel arguments"
1910         help
1911           The command-line arguments provided by the boot loader will be
1912           appended to the the device tree bootargs property.
1913 
1914 endchoice
1915 
1916 config CMDLINE
1917         string "Default kernel command string"
1918         default ""
1919         help
1920           On some architectures (EBSA110 and CATS), there is currently no way
1921           for the boot loader to pass arguments to the kernel. For these
1922           architectures, you should supply some command-line options at build
1923           time by entering them here. As a minimum, you should specify the
1924           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1925 
1926 choice
1927         prompt "Kernel command line type" if CMDLINE != ""
1928         default CMDLINE_FROM_BOOTLOADER
1929         depends on ATAGS
1930 
1931 config CMDLINE_FROM_BOOTLOADER
1932         bool "Use bootloader kernel arguments if available"
1933         help
1934           Uses the command-line options passed by the boot loader. If
1935           the boot loader doesn't provide any, the default kernel command
1936           string provided in CMDLINE will be used.
1937 
1938 config CMDLINE_EXTEND
1939         bool "Extend bootloader kernel arguments"
1940         help
1941           The command-line arguments provided by the boot loader will be
1942           appended to the default kernel command string.
1943 
1944 config CMDLINE_FORCE
1945         bool "Always use the default kernel command string"
1946         help
1947           Always use the default kernel command string, even if the boot
1948           loader passes other arguments to the kernel.
1949           This is useful if you cannot or don't want to change the
1950           command-line options your boot loader passes to the kernel.
1951 endchoice
1952 
1953 config XIP_KERNEL
1954         bool "Kernel Execute-In-Place from ROM"
1955         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1956         help
1957           Execute-In-Place allows the kernel to run from non-volatile storage
1958           directly addressable by the CPU, such as NOR flash. This saves RAM
1959           space since the text section of the kernel is not loaded from flash
1960           to RAM.  Read-write sections, such as the data section and stack,
1961           are still copied to RAM.  The XIP kernel is not compressed since
1962           it has to run directly from flash, so it will take more space to
1963           store it.  The flash address used to link the kernel object files,
1964           and for storing it, is configuration dependent. Therefore, if you
1965           say Y here, you must know the proper physical address where to
1966           store the kernel image depending on your own flash memory usage.
1967 
1968           Also note that the make target becomes "make xipImage" rather than
1969           "make zImage" or "make Image".  The final kernel binary to put in
1970           ROM memory will be arch/arm/boot/xipImage.
1971 
1972           If unsure, say N.
1973 
1974 config XIP_PHYS_ADDR
1975         hex "XIP Kernel Physical Location"
1976         depends on XIP_KERNEL
1977         default "0x00080000"
1978         help
1979           This is the physical address in your flash memory the kernel will
1980           be linked for and stored to.  This address is dependent on your
1981           own flash usage.
1982 
1983 config KEXEC
1984         bool "Kexec system call (EXPERIMENTAL)"
1985         depends on (!SMP || PM_SLEEP_SMP)
1986         help
1987           kexec is a system call that implements the ability to shutdown your
1988           current kernel, and to start another kernel.  It is like a reboot
1989           but it is independent of the system firmware.   And like a reboot
1990           you can start any kernel with it, not just Linux.
1991 
1992           It is an ongoing process to be certain the hardware in a machine
1993           is properly shutdown, so do not be surprised if this code does not
1994           initially work for you.
1995 
1996 config ATAGS_PROC
1997         bool "Export atags in procfs"
1998         depends on ATAGS && KEXEC
1999         default y
2000         help
2001           Should the atags used to boot the kernel be exported in an "atags"
2002           file in procfs. Useful with kexec.
2003 
2004 config CRASH_DUMP
2005         bool "Build kdump crash kernel (EXPERIMENTAL)"
2006         help
2007           Generate crash dump after being started by kexec. This should
2008           be normally only set in special crash dump kernels which are
2009           loaded in the main kernel with kexec-tools into a specially
2010           reserved region and then later executed after a crash by
2011           kdump/kexec. The crash dump kernel must be compiled to a
2012           memory address not used by the main kernel
2013 
2014           For more details see Documentation/kdump/kdump.txt
2015 
2016 config AUTO_ZRELADDR
2017         bool "Auto calculation of the decompressed kernel image address"
2018         help
2019           ZRELADDR is the physical address where the decompressed kernel
2020           image will be placed. If AUTO_ZRELADDR is selected, the address
2021           will be determined at run-time by masking the current IP with
2022           0xf8000000. This assumes the zImage being placed in the first 128MB
2023           from start of memory.
2024 
2025 endmenu
2026 
2027 menu "CPU Power Management"
2028 
2029 source "drivers/cpufreq/Kconfig"
2030 
2031 source "drivers/cpuidle/Kconfig"
2032 
2033 endmenu
2034 
2035 menu "Floating point emulation"
2036 
2037 comment "At least one emulation must be selected"
2038 
2039 config FPE_NWFPE
2040         bool "NWFPE math emulation"
2041         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2042         ---help---
2043           Say Y to include the NWFPE floating point emulator in the kernel.
2044           This is necessary to run most binaries. Linux does not currently
2045           support floating point hardware so you need to say Y here even if
2046           your machine has an FPA or floating point co-processor podule.
2047 
2048           You may say N here if you are going to load the Acorn FPEmulator
2049           early in the bootup.
2050 
2051 config FPE_NWFPE_XP
2052         bool "Support extended precision"
2053         depends on FPE_NWFPE
2054         help
2055           Say Y to include 80-bit support in the kernel floating-point
2056           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2057           Note that gcc does not generate 80-bit operations by default,
2058           so in most cases this option only enlarges the size of the
2059           floating point emulator without any good reason.
2060 
2061           You almost surely want to say N here.
2062 
2063 config FPE_FASTFPE
2064         bool "FastFPE math emulation (EXPERIMENTAL)"
2065         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2066         ---help---
2067           Say Y here to include the FAST floating point emulator in the kernel.
2068           This is an experimental much faster emulator which now also has full
2069           precision for the mantissa.  It does not support any exceptions.
2070           It is very simple, and approximately 3-6 times faster than NWFPE.
2071 
2072           It should be sufficient for most programs.  It may be not suitable
2073           for scientific calculations, but you have to check this for yourself.
2074           If you do not feel you need a faster FP emulation you should better
2075           choose NWFPE.
2076 
2077 config VFP
2078         bool "VFP-format floating point maths"
2079         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2080         help
2081           Say Y to include VFP support code in the kernel. This is needed
2082           if your hardware includes a VFP unit.
2083 
2084           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2085           release notes and additional status information.
2086 
2087           Say N if your target does not have VFP hardware.
2088 
2089 config VFPv3
2090         bool
2091         depends on VFP
2092         default y if CPU_V7
2093 
2094 config NEON
2095         bool "Advanced SIMD (NEON) Extension support"
2096         depends on VFPv3 && CPU_V7
2097         help
2098           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2099           Extension.
2100 
2101 config KERNEL_MODE_NEON
2102         bool "Support for NEON in kernel mode"
2103         depends on NEON && AEABI
2104         help
2105           Say Y to include support for NEON in kernel mode.
2106 
2107 endmenu
2108 
2109 menu "Userspace binary formats"
2110 
2111 source "fs/Kconfig.binfmt"
2112 
2113 config ARTHUR
2114         tristate "RISC OS personality"
2115         depends on !AEABI
2116         help
2117           Say Y here to include the kernel code necessary if you want to run
2118           Acorn RISC OS/Arthur binaries under Linux. This code is still very
2119           experimental; if this sounds frightening, say N and sleep in peace.
2120           You can also say M here to compile this support as a module (which
2121           will be called arthur).
2122 
2123 endmenu
2124 
2125 menu "Power management options"
2126 
2127 source "kernel/power/Kconfig"
2128 
2129 config ARCH_SUSPEND_POSSIBLE
2130         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2131                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2132         def_bool y
2133 
2134 config ARM_CPU_SUSPEND
2135         def_bool PM_SLEEP
2136 
2137 config ARCH_HIBERNATION_POSSIBLE
2138         bool
2139         depends on MMU
2140         default y if ARCH_SUSPEND_POSSIBLE
2141 
2142 endmenu
2143 
2144 source "net/Kconfig"
2145 
2146 source "drivers/Kconfig"
2147 
2148 source "fs/Kconfig"
2149 
2150 source "arch/arm/Kconfig.debug"
2151 
2152 source "security/Kconfig"
2153 
2154 source "crypto/Kconfig"
2155 
2156 source "lib/Kconfig"
2157 
2158 source "arch/arm/kvm/Kconfig"

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