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Linux/arch/arm/Kconfig

  1 config ARM
  2         bool
  3         default y
  4         select ARCH_CLOCKSOURCE_DATA
  5         select ARCH_HAS_DEVMEM_IS_ALLOWED
  6         select ARCH_HAS_ELF_RANDOMIZE
  7         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  8         select ARCH_HAVE_CUSTOM_GPIO_H
  9         select ARCH_HAS_GCOV_PROFILE_ALL
 10         select ARCH_MIGHT_HAVE_PC_PARPORT
 11         select ARCH_SUPPORTS_ATOMIC_RMW
 12         select ARCH_USE_BUILTIN_BSWAP
 13         select ARCH_USE_CMPXCHG_LOCKREF
 14         select ARCH_WANT_IPC_PARSE_VERSION
 15         select BUILDTIME_EXTABLE_SORT if MMU
 16         select CLONE_BACKWARDS
 17         select CPU_PM if (SUSPEND || CPU_IDLE)
 18         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
 19         select EDAC_SUPPORT
 20         select EDAC_ATOMIC_SCRUB
 21         select GENERIC_ALLOCATOR
 22         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
 23         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
 24         select GENERIC_EARLY_IOREMAP
 25         select GENERIC_IDLE_POLL_SETUP
 26         select GENERIC_IRQ_PROBE
 27         select GENERIC_IRQ_SHOW
 28         select GENERIC_IRQ_SHOW_LEVEL
 29         select GENERIC_PCI_IOMAP
 30         select GENERIC_SCHED_CLOCK
 31         select GENERIC_SMP_IDLE_THREAD
 32         select GENERIC_STRNCPY_FROM_USER
 33         select GENERIC_STRNLEN_USER
 34         select HANDLE_DOMAIN_IRQ
 35         select HARDIRQS_SW_RESEND
 36         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
 37         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
 38         select HAVE_ARCH_HARDENED_USERCOPY
 39         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
 40         select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
 41         select HAVE_ARCH_MMAP_RND_BITS if MMU
 42         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
 43         select HAVE_ARCH_TRACEHOOK
 44         select HAVE_ARM_SMCCC if CPU_V7
 45         select HAVE_CBPF_JIT
 46         select HAVE_CC_STACKPROTECTOR
 47         select HAVE_CONTEXT_TRACKING
 48         select HAVE_C_RECORDMCOUNT
 49         select HAVE_DEBUG_KMEMLEAK
 50         select HAVE_DMA_API_DEBUG
 51         select HAVE_DMA_CONTIGUOUS if MMU
 52         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL) && !CPU_ENDIAN_BE32 && MMU
 53         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
 54         select HAVE_EXIT_THREAD
 55         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
 56         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
 57         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
 58         select HAVE_GCC_PLUGINS
 59         select HAVE_GENERIC_DMA_COHERENT
 60         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
 61         select HAVE_IDE if PCI || ISA || PCMCIA
 62         select HAVE_IRQ_TIME_ACCOUNTING
 63         select HAVE_KERNEL_GZIP
 64         select HAVE_KERNEL_LZ4
 65         select HAVE_KERNEL_LZMA
 66         select HAVE_KERNEL_LZO
 67         select HAVE_KERNEL_XZ
 68         select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
 69         select HAVE_KRETPROBES if (HAVE_KPROBES)
 70         select HAVE_MEMBLOCK
 71         select HAVE_MOD_ARCH_SPECIFIC
 72         select HAVE_NMI
 73         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
 74         select HAVE_OPTPROBES if !THUMB2_KERNEL
 75         select HAVE_PERF_EVENTS
 76         select HAVE_PERF_REGS
 77         select HAVE_PERF_USER_STACK_DUMP
 78         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
 79         select HAVE_REGS_AND_STACK_ACCESS_API
 80         select HAVE_SYSCALL_TRACEPOINTS
 81         select HAVE_UID16
 82         select HAVE_VIRT_CPU_ACCOUNTING_GEN
 83         select IRQ_FORCED_THREADING
 84         select MODULES_USE_ELF_REL
 85         select NO_BOOTMEM
 86         select OF_EARLY_FLATTREE if OF
 87         select OF_RESERVED_MEM if OF
 88         select OLD_SIGACTION
 89         select OLD_SIGSUSPEND3
 90         select PERF_USE_VMALLOC
 91         select RTC_LIB
 92         select SYS_SUPPORTS_APM_EMULATION
 93         # Above selects are sorted alphabetically; please add new ones
 94         # according to that.  Thanks.
 95         help
 96           The ARM series is a line of low-power-consumption RISC chip designs
 97           licensed by ARM Ltd and targeted at embedded applications and
 98           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
 99           manufactured, but legacy ARM-based PC hardware remains popular in
100           Europe.  There is an ARM Linux project with a web page at
101           <http://www.arm.linux.org.uk/>.
102 
103 config ARM_HAS_SG_CHAIN
104         select ARCH_HAS_SG_CHAIN
105         bool
106 
107 config NEED_SG_DMA_LENGTH
108         bool
109 
110 config ARM_DMA_USE_IOMMU
111         bool
112         select ARM_HAS_SG_CHAIN
113         select NEED_SG_DMA_LENGTH
114 
115 if ARM_DMA_USE_IOMMU
116 
117 config ARM_DMA_IOMMU_ALIGNMENT
118         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
119         range 4 9
120         default 8
121         help
122           DMA mapping framework by default aligns all buffers to the smallest
123           PAGE_SIZE order which is greater than or equal to the requested buffer
124           size. This works well for buffers up to a few hundreds kilobytes, but
125           for larger buffers it just a waste of address space. Drivers which has
126           relatively small addressing window (like 64Mib) might run out of
127           virtual space with just a few allocations.
128 
129           With this parameter you can specify the maximum PAGE_SIZE order for
130           DMA IOMMU buffers. Larger buffers will be aligned only to this
131           specified order. The order is expressed as a power of two multiplied
132           by the PAGE_SIZE.
133 
134 endif
135 
136 config MIGHT_HAVE_PCI
137         bool
138 
139 config SYS_SUPPORTS_APM_EMULATION
140         bool
141 
142 config HAVE_TCM
143         bool
144         select GENERIC_ALLOCATOR
145 
146 config HAVE_PROC_CPU
147         bool
148 
149 config NO_IOPORT_MAP
150         bool
151 
152 config EISA
153         bool
154         ---help---
155           The Extended Industry Standard Architecture (EISA) bus was
156           developed as an open alternative to the IBM MicroChannel bus.
157 
158           The EISA bus provided some of the features of the IBM MicroChannel
159           bus while maintaining backward compatibility with cards made for
160           the older ISA bus.  The EISA bus saw limited use between 1988 and
161           1995 when it was made obsolete by the PCI bus.
162 
163           Say Y here if you are building a kernel for an EISA-based machine.
164 
165           Otherwise, say N.
166 
167 config SBUS
168         bool
169 
170 config STACKTRACE_SUPPORT
171         bool
172         default y
173 
174 config LOCKDEP_SUPPORT
175         bool
176         default y
177 
178 config TRACE_IRQFLAGS_SUPPORT
179         bool
180         default !CPU_V7M
181 
182 config RWSEM_XCHGADD_ALGORITHM
183         bool
184         default y
185 
186 config ARCH_HAS_ILOG2_U32
187         bool
188 
189 config ARCH_HAS_ILOG2_U64
190         bool
191 
192 config ARCH_HAS_BANDGAP
193         bool
194 
195 config FIX_EARLYCON_MEM
196         def_bool y if MMU
197 
198 config GENERIC_HWEIGHT
199         bool
200         default y
201 
202 config GENERIC_CALIBRATE_DELAY
203         bool
204         default y
205 
206 config ARCH_MAY_HAVE_PC_FDC
207         bool
208 
209 config ZONE_DMA
210         bool
211 
212 config NEED_DMA_MAP_STATE
213        def_bool y
214 
215 config ARCH_SUPPORTS_UPROBES
216         def_bool y
217 
218 config ARCH_HAS_DMA_SET_COHERENT_MASK
219         bool
220 
221 config GENERIC_ISA_DMA
222         bool
223 
224 config FIQ
225         bool
226 
227 config NEED_RET_TO_USER
228         bool
229 
230 config ARCH_MTD_XIP
231         bool
232 
233 config VECTORS_BASE
234         hex
235         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
236         default DRAM_BASE if REMAP_VECTORS_TO_RAM
237         default 0x00000000
238         help
239           The base address of exception vectors.  This must be two pages
240           in size.
241 
242 config ARM_PATCH_PHYS_VIRT
243         bool "Patch physical to virtual translations at runtime" if EMBEDDED
244         default y
245         depends on !XIP_KERNEL && MMU
246         help
247           Patch phys-to-virt and virt-to-phys translation functions at
248           boot and module load time according to the position of the
249           kernel in system memory.
250 
251           This can only be used with non-XIP MMU kernels where the base
252           of physical memory is at a 16MB boundary.
253 
254           Only disable this option if you know that you do not require
255           this feature (eg, building a kernel for a single machine) and
256           you need to shrink the kernel to the minimal size.
257 
258 config NEED_MACH_IO_H
259         bool
260         help
261           Select this when mach/io.h is required to provide special
262           definitions for this platform.  The need for mach/io.h should
263           be avoided when possible.
264 
265 config NEED_MACH_MEMORY_H
266         bool
267         help
268           Select this when mach/memory.h is required to provide special
269           definitions for this platform.  The need for mach/memory.h should
270           be avoided when possible.
271 
272 config PHYS_OFFSET
273         hex "Physical address of main memory" if MMU
274         depends on !ARM_PATCH_PHYS_VIRT
275         default DRAM_BASE if !MMU
276         default 0x00000000 if ARCH_EBSA110 || \
277                         ARCH_FOOTBRIDGE || \
278                         ARCH_INTEGRATOR || \
279                         ARCH_IOP13XX || \
280                         ARCH_KS8695 || \
281                         ARCH_REALVIEW
282         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
283         default 0x20000000 if ARCH_S5PV210
284         default 0xc0000000 if ARCH_SA1100
285         help
286           Please provide the physical address corresponding to the
287           location of main memory in your system.
288 
289 config GENERIC_BUG
290         def_bool y
291         depends on BUG
292 
293 config PGTABLE_LEVELS
294         int
295         default 3 if ARM_LPAE
296         default 2
297 
298 source "init/Kconfig"
299 
300 source "kernel/Kconfig.freezer"
301 
302 menu "System Type"
303 
304 config MMU
305         bool "MMU-based Paged Memory Management Support"
306         default y
307         help
308           Select if you want MMU-based virtualised addressing space
309           support by paged memory management. If unsure, say 'Y'.
310 
311 config ARCH_MMAP_RND_BITS_MIN
312         default 8
313 
314 config ARCH_MMAP_RND_BITS_MAX
315         default 14 if PAGE_OFFSET=0x40000000
316         default 15 if PAGE_OFFSET=0x80000000
317         default 16
318 
319 #
320 # The "ARM system type" choice list is ordered alphabetically by option
321 # text.  Please add new entries in the option alphabetic order.
322 #
323 choice
324         prompt "ARM system type"
325         default ARM_SINGLE_ARMV7M if !MMU
326         default ARCH_MULTIPLATFORM if MMU
327 
328 config ARCH_MULTIPLATFORM
329         bool "Allow multiple platforms to be selected"
330         depends on MMU
331         select ARM_HAS_SG_CHAIN
332         select ARM_PATCH_PHYS_VIRT
333         select AUTO_ZRELADDR
334         select CLKSRC_OF
335         select COMMON_CLK
336         select GENERIC_CLOCKEVENTS
337         select MIGHT_HAVE_PCI
338         select MULTI_IRQ_HANDLER
339         select PCI_DOMAINS if PCI
340         select SPARSE_IRQ
341         select USE_OF
342 
343 config ARM_SINGLE_ARMV7M
344         bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
345         depends on !MMU
346         select ARM_NVIC
347         select AUTO_ZRELADDR
348         select CLKSRC_OF
349         select COMMON_CLK
350         select CPU_V7M
351         select GENERIC_CLOCKEVENTS
352         select NO_IOPORT_MAP
353         select SPARSE_IRQ
354         select USE_OF
355 
356 config ARCH_GEMINI
357         bool "Cortina Systems Gemini"
358         select CLKSRC_MMIO
359         select CPU_FA526
360         select GENERIC_CLOCKEVENTS
361         select GPIOLIB
362         help
363           Support for the Cortina Systems Gemini family SoCs
364 
365 config ARCH_EBSA110
366         bool "EBSA-110"
367         select ARCH_USES_GETTIMEOFFSET
368         select CPU_SA110
369         select ISA
370         select NEED_MACH_IO_H
371         select NEED_MACH_MEMORY_H
372         select NO_IOPORT_MAP
373         help
374           This is an evaluation board for the StrongARM processor available
375           from Digital. It has limited hardware on-board, including an
376           Ethernet interface, two PCMCIA sockets, two serial ports and a
377           parallel port.
378 
379 config ARCH_EP93XX
380         bool "EP93xx-based"
381         select ARCH_HAS_HOLES_MEMORYMODEL
382         select ARM_AMBA
383         select ARM_PATCH_PHYS_VIRT
384         select ARM_VIC
385         select AUTO_ZRELADDR
386         select CLKDEV_LOOKUP
387         select CLKSRC_MMIO
388         select CPU_ARM920T
389         select GENERIC_CLOCKEVENTS
390         select GPIOLIB
391         help
392           This enables support for the Cirrus EP93xx series of CPUs.
393 
394 config ARCH_FOOTBRIDGE
395         bool "FootBridge"
396         select CPU_SA110
397         select FOOTBRIDGE
398         select GENERIC_CLOCKEVENTS
399         select HAVE_IDE
400         select NEED_MACH_IO_H if !MMU
401         select NEED_MACH_MEMORY_H
402         help
403           Support for systems based on the DC21285 companion chip
404           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
405 
406 config ARCH_NETX
407         bool "Hilscher NetX based"
408         select ARM_VIC
409         select CLKSRC_MMIO
410         select CPU_ARM926T
411         select GENERIC_CLOCKEVENTS
412         help
413           This enables support for systems based on the Hilscher NetX Soc
414 
415 config ARCH_IOP13XX
416         bool "IOP13xx-based"
417         depends on MMU
418         select CPU_XSC3
419         select NEED_MACH_MEMORY_H
420         select NEED_RET_TO_USER
421         select PCI
422         select PLAT_IOP
423         select VMSPLIT_1G
424         select SPARSE_IRQ
425         help
426           Support for Intel's IOP13XX (XScale) family of processors.
427 
428 config ARCH_IOP32X
429         bool "IOP32x-based"
430         depends on MMU
431         select CPU_XSCALE
432         select GPIO_IOP
433         select GPIOLIB
434         select NEED_RET_TO_USER
435         select PCI
436         select PLAT_IOP
437         help
438           Support for Intel's 80219 and IOP32X (XScale) family of
439           processors.
440 
441 config ARCH_IOP33X
442         bool "IOP33x-based"
443         depends on MMU
444         select CPU_XSCALE
445         select GPIO_IOP
446         select GPIOLIB
447         select NEED_RET_TO_USER
448         select PCI
449         select PLAT_IOP
450         help
451           Support for Intel's IOP33X (XScale) family of processors.
452 
453 config ARCH_IXP4XX
454         bool "IXP4xx-based"
455         depends on MMU
456         select ARCH_HAS_DMA_SET_COHERENT_MASK
457         select ARCH_SUPPORTS_BIG_ENDIAN
458         select CLKSRC_MMIO
459         select CPU_XSCALE
460         select DMABOUNCE if PCI
461         select GENERIC_CLOCKEVENTS
462         select GPIOLIB
463         select MIGHT_HAVE_PCI
464         select NEED_MACH_IO_H
465         select USB_EHCI_BIG_ENDIAN_DESC
466         select USB_EHCI_BIG_ENDIAN_MMIO
467         help
468           Support for Intel's IXP4XX (XScale) family of processors.
469 
470 config ARCH_DOVE
471         bool "Marvell Dove"
472         select CPU_PJ4
473         select GENERIC_CLOCKEVENTS
474         select GPIOLIB
475         select MIGHT_HAVE_PCI
476         select MULTI_IRQ_HANDLER
477         select MVEBU_MBUS
478         select PINCTRL
479         select PINCTRL_DOVE
480         select PLAT_ORION_LEGACY
481         select SPARSE_IRQ
482         select PM_GENERIC_DOMAINS if PM
483         help
484           Support for the Marvell Dove SoC 88AP510
485 
486 config ARCH_KS8695
487         bool "Micrel/Kendin KS8695"
488         select CLKSRC_MMIO
489         select CPU_ARM922T
490         select GENERIC_CLOCKEVENTS
491         select GPIOLIB
492         select NEED_MACH_MEMORY_H
493         help
494           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
495           System-on-Chip devices.
496 
497 config ARCH_W90X900
498         bool "Nuvoton W90X900 CPU"
499         select CLKDEV_LOOKUP
500         select CLKSRC_MMIO
501         select CPU_ARM926T
502         select GENERIC_CLOCKEVENTS
503         select GPIOLIB
504         help
505           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
506           At present, the w90x900 has been renamed nuc900, regarding
507           the ARM series product line, you can login the following
508           link address to know more.
509 
510           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
511                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
512 
513 config ARCH_LPC32XX
514         bool "NXP LPC32XX"
515         select ARM_AMBA
516         select CLKDEV_LOOKUP
517         select CLKSRC_LPC32XX
518         select COMMON_CLK
519         select CPU_ARM926T
520         select GENERIC_CLOCKEVENTS
521         select GPIOLIB
522         select MULTI_IRQ_HANDLER
523         select SPARSE_IRQ
524         select USE_OF
525         help
526           Support for the NXP LPC32XX family of processors
527 
528 config ARCH_PXA
529         bool "PXA2xx/PXA3xx-based"
530         depends on MMU
531         select ARCH_MTD_XIP
532         select ARM_CPU_SUSPEND if PM
533         select AUTO_ZRELADDR
534         select COMMON_CLK
535         select CLKDEV_LOOKUP
536         select CLKSRC_PXA
537         select CLKSRC_MMIO
538         select CLKSRC_OF
539         select CPU_XSCALE if !CPU_XSC3
540         select GENERIC_CLOCKEVENTS
541         select GPIO_PXA
542         select GPIOLIB
543         select HAVE_IDE
544         select IRQ_DOMAIN
545         select MULTI_IRQ_HANDLER
546         select PLAT_PXA
547         select SPARSE_IRQ
548         help
549           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
550 
551 config ARCH_RPC
552         bool "RiscPC"
553         depends on MMU
554         select ARCH_ACORN
555         select ARCH_MAY_HAVE_PC_FDC
556         select ARCH_SPARSEMEM_ENABLE
557         select ARCH_USES_GETTIMEOFFSET
558         select CPU_SA110
559         select FIQ
560         select HAVE_IDE
561         select HAVE_PATA_PLATFORM
562         select ISA_DMA_API
563         select NEED_MACH_IO_H
564         select NEED_MACH_MEMORY_H
565         select NO_IOPORT_MAP
566         help
567           On the Acorn Risc-PC, Linux can support the internal IDE disk and
568           CD-ROM interface, serial and parallel port, and the floppy drive.
569 
570 config ARCH_SA1100
571         bool "SA1100-based"
572         select ARCH_MTD_XIP
573         select ARCH_SPARSEMEM_ENABLE
574         select CLKDEV_LOOKUP
575         select CLKSRC_MMIO
576         select CLKSRC_PXA
577         select CLKSRC_OF if OF
578         select CPU_FREQ
579         select CPU_SA1100
580         select GENERIC_CLOCKEVENTS
581         select GPIOLIB
582         select HAVE_IDE
583         select IRQ_DOMAIN
584         select ISA
585         select MULTI_IRQ_HANDLER
586         select NEED_MACH_MEMORY_H
587         select SPARSE_IRQ
588         help
589           Support for StrongARM 11x0 based boards.
590 
591 config ARCH_S3C24XX
592         bool "Samsung S3C24XX SoCs"
593         select ATAGS
594         select CLKDEV_LOOKUP
595         select CLKSRC_SAMSUNG_PWM
596         select GENERIC_CLOCKEVENTS
597         select GPIO_SAMSUNG
598         select GPIOLIB
599         select HAVE_S3C2410_I2C if I2C
600         select HAVE_S3C2410_WATCHDOG if WATCHDOG
601         select HAVE_S3C_RTC if RTC_CLASS
602         select MULTI_IRQ_HANDLER
603         select NEED_MACH_IO_H
604         select SAMSUNG_ATAGS
605         help
606           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
607           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
608           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
609           Samsung SMDK2410 development board (and derivatives).
610 
611 config ARCH_DAVINCI
612         bool "TI DaVinci"
613         select ARCH_HAS_HOLES_MEMORYMODEL
614         select CLKDEV_LOOKUP
615         select CPU_ARM926T
616         select GENERIC_ALLOCATOR
617         select GENERIC_CLOCKEVENTS
618         select GENERIC_IRQ_CHIP
619         select GPIOLIB
620         select HAVE_IDE
621         select USE_OF
622         select ZONE_DMA
623         help
624           Support for TI's DaVinci platform.
625 
626 config ARCH_OMAP1
627         bool "TI OMAP1"
628         depends on MMU
629         select ARCH_HAS_HOLES_MEMORYMODEL
630         select ARCH_OMAP
631         select CLKDEV_LOOKUP
632         select CLKSRC_MMIO
633         select GENERIC_CLOCKEVENTS
634         select GENERIC_IRQ_CHIP
635         select GPIOLIB
636         select HAVE_IDE
637         select IRQ_DOMAIN
638         select MULTI_IRQ_HANDLER
639         select NEED_MACH_IO_H if PCCARD
640         select NEED_MACH_MEMORY_H
641         select SPARSE_IRQ
642         help
643           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
644 
645 endchoice
646 
647 menu "Multiple platform selection"
648         depends on ARCH_MULTIPLATFORM
649 
650 comment "CPU Core family selection"
651 
652 config ARCH_MULTI_V4
653         bool "ARMv4 based platforms (FA526)"
654         depends on !ARCH_MULTI_V6_V7
655         select ARCH_MULTI_V4_V5
656         select CPU_FA526
657 
658 config ARCH_MULTI_V4T
659         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
660         depends on !ARCH_MULTI_V6_V7
661         select ARCH_MULTI_V4_V5
662         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
663                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
664                 CPU_ARM925T || CPU_ARM940T)
665 
666 config ARCH_MULTI_V5
667         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
668         depends on !ARCH_MULTI_V6_V7
669         select ARCH_MULTI_V4_V5
670         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
671                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
672                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
673 
674 config ARCH_MULTI_V4_V5
675         bool
676 
677 config ARCH_MULTI_V6
678         bool "ARMv6 based platforms (ARM11)"
679         select ARCH_MULTI_V6_V7
680         select CPU_V6K
681 
682 config ARCH_MULTI_V7
683         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
684         default y
685         select ARCH_MULTI_V6_V7
686         select CPU_V7
687         select HAVE_SMP
688 
689 config ARCH_MULTI_V6_V7
690         bool
691         select MIGHT_HAVE_CACHE_L2X0
692 
693 config ARCH_MULTI_CPU_AUTO
694         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
695         select ARCH_MULTI_V5
696 
697 endmenu
698 
699 config ARCH_VIRT
700         bool "Dummy Virtual Machine"
701         depends on ARCH_MULTI_V7
702         select ARM_AMBA
703         select ARM_GIC
704         select ARM_GIC_V2M if PCI
705         select ARM_GIC_V3
706         select ARM_PSCI
707         select HAVE_ARM_ARCH_TIMER
708 
709 #
710 # This is sorted alphabetically by mach-* pathname.  However, plat-*
711 # Kconfigs may be included either alphabetically (according to the
712 # plat- suffix) or along side the corresponding mach-* source.
713 #
714 source "arch/arm/mach-mvebu/Kconfig"
715 
716 source "arch/arm/mach-alpine/Kconfig"
717 
718 source "arch/arm/mach-artpec/Kconfig"
719 
720 source "arch/arm/mach-asm9260/Kconfig"
721 
722 source "arch/arm/mach-at91/Kconfig"
723 
724 source "arch/arm/mach-axxia/Kconfig"
725 
726 source "arch/arm/mach-bcm/Kconfig"
727 
728 source "arch/arm/mach-berlin/Kconfig"
729 
730 source "arch/arm/mach-clps711x/Kconfig"
731 
732 source "arch/arm/mach-cns3xxx/Kconfig"
733 
734 source "arch/arm/mach-davinci/Kconfig"
735 
736 source "arch/arm/mach-digicolor/Kconfig"
737 
738 source "arch/arm/mach-dove/Kconfig"
739 
740 source "arch/arm/mach-ep93xx/Kconfig"
741 
742 source "arch/arm/mach-footbridge/Kconfig"
743 
744 source "arch/arm/mach-gemini/Kconfig"
745 
746 source "arch/arm/mach-highbank/Kconfig"
747 
748 source "arch/arm/mach-hisi/Kconfig"
749 
750 source "arch/arm/mach-integrator/Kconfig"
751 
752 source "arch/arm/mach-iop32x/Kconfig"
753 
754 source "arch/arm/mach-iop33x/Kconfig"
755 
756 source "arch/arm/mach-iop13xx/Kconfig"
757 
758 source "arch/arm/mach-ixp4xx/Kconfig"
759 
760 source "arch/arm/mach-keystone/Kconfig"
761 
762 source "arch/arm/mach-ks8695/Kconfig"
763 
764 source "arch/arm/mach-meson/Kconfig"
765 
766 source "arch/arm/mach-moxart/Kconfig"
767 
768 source "arch/arm/mach-aspeed/Kconfig"
769 
770 source "arch/arm/mach-mv78xx0/Kconfig"
771 
772 source "arch/arm/mach-imx/Kconfig"
773 
774 source "arch/arm/mach-mediatek/Kconfig"
775 
776 source "arch/arm/mach-mxs/Kconfig"
777 
778 source "arch/arm/mach-netx/Kconfig"
779 
780 source "arch/arm/mach-nomadik/Kconfig"
781 
782 source "arch/arm/mach-nspire/Kconfig"
783 
784 source "arch/arm/plat-omap/Kconfig"
785 
786 source "arch/arm/mach-omap1/Kconfig"
787 
788 source "arch/arm/mach-omap2/Kconfig"
789 
790 source "arch/arm/mach-orion5x/Kconfig"
791 
792 source "arch/arm/mach-picoxcell/Kconfig"
793 
794 source "arch/arm/mach-pxa/Kconfig"
795 source "arch/arm/plat-pxa/Kconfig"
796 
797 source "arch/arm/mach-mmp/Kconfig"
798 
799 source "arch/arm/mach-oxnas/Kconfig"
800 
801 source "arch/arm/mach-qcom/Kconfig"
802 
803 source "arch/arm/mach-realview/Kconfig"
804 
805 source "arch/arm/mach-rockchip/Kconfig"
806 
807 source "arch/arm/mach-sa1100/Kconfig"
808 
809 source "arch/arm/mach-socfpga/Kconfig"
810 
811 source "arch/arm/mach-spear/Kconfig"
812 
813 source "arch/arm/mach-sti/Kconfig"
814 
815 source "arch/arm/mach-s3c24xx/Kconfig"
816 
817 source "arch/arm/mach-s3c64xx/Kconfig"
818 
819 source "arch/arm/mach-s5pv210/Kconfig"
820 
821 source "arch/arm/mach-exynos/Kconfig"
822 source "arch/arm/plat-samsung/Kconfig"
823 
824 source "arch/arm/mach-shmobile/Kconfig"
825 
826 source "arch/arm/mach-sunxi/Kconfig"
827 
828 source "arch/arm/mach-prima2/Kconfig"
829 
830 source "arch/arm/mach-tango/Kconfig"
831 
832 source "arch/arm/mach-tegra/Kconfig"
833 
834 source "arch/arm/mach-u300/Kconfig"
835 
836 source "arch/arm/mach-uniphier/Kconfig"
837 
838 source "arch/arm/mach-ux500/Kconfig"
839 
840 source "arch/arm/mach-versatile/Kconfig"
841 
842 source "arch/arm/mach-vexpress/Kconfig"
843 source "arch/arm/plat-versatile/Kconfig"
844 
845 source "arch/arm/mach-vt8500/Kconfig"
846 
847 source "arch/arm/mach-w90x900/Kconfig"
848 
849 source "arch/arm/mach-zx/Kconfig"
850 
851 source "arch/arm/mach-zynq/Kconfig"
852 
853 # ARMv7-M architecture
854 config ARCH_EFM32
855         bool "Energy Micro efm32"
856         depends on ARM_SINGLE_ARMV7M
857         select GPIOLIB
858         help
859           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
860           processors.
861 
862 config ARCH_LPC18XX
863         bool "NXP LPC18xx/LPC43xx"
864         depends on ARM_SINGLE_ARMV7M
865         select ARCH_HAS_RESET_CONTROLLER
866         select ARM_AMBA
867         select CLKSRC_LPC32XX
868         select PINCTRL
869         help
870           Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
871           high performance microcontrollers.
872 
873 config ARCH_STM32
874         bool "STMicrolectronics STM32"
875         depends on ARM_SINGLE_ARMV7M
876         select ARCH_HAS_RESET_CONTROLLER
877         select ARMV7M_SYSTICK
878         select CLKSRC_STM32
879         select PINCTRL
880         select RESET_CONTROLLER
881         select STM32_EXTI
882         help
883           Support for STMicroelectronics STM32 processors.
884 
885 config MACH_STM32F429
886         bool "STMicrolectronics STM32F429"
887         depends on ARCH_STM32
888         default y
889 
890 config ARCH_MPS2
891         bool "ARM MPS2 platform"
892         depends on ARM_SINGLE_ARMV7M
893         select ARM_AMBA
894         select CLKSRC_MPS2
895         help
896           Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
897           with a range of available cores like Cortex-M3/M4/M7.
898 
899           Please, note that depends which Application Note is used memory map
900           for the platform may vary, so adjustment of RAM base might be needed.
901 
902 # Definitions to make life easier
903 config ARCH_ACORN
904         bool
905 
906 config PLAT_IOP
907         bool
908         select GENERIC_CLOCKEVENTS
909 
910 config PLAT_ORION
911         bool
912         select CLKSRC_MMIO
913         select COMMON_CLK
914         select GENERIC_IRQ_CHIP
915         select IRQ_DOMAIN
916 
917 config PLAT_ORION_LEGACY
918         bool
919         select PLAT_ORION
920 
921 config PLAT_PXA
922         bool
923 
924 config PLAT_VERSATILE
925         bool
926 
927 source "arch/arm/firmware/Kconfig"
928 
929 source arch/arm/mm/Kconfig
930 
931 config IWMMXT
932         bool "Enable iWMMXt support"
933         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
934         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
935         help
936           Enable support for iWMMXt context switching at run time if
937           running on a CPU that supports it.
938 
939 config MULTI_IRQ_HANDLER
940         bool
941         help
942           Allow each machine to specify it's own IRQ handler at run time.
943 
944 if !MMU
945 source "arch/arm/Kconfig-nommu"
946 endif
947 
948 config PJ4B_ERRATA_4742
949         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
950         depends on CPU_PJ4B && MACH_ARMADA_370
951         default y
952         help
953           When coming out of either a Wait for Interrupt (WFI) or a Wait for
954           Event (WFE) IDLE states, a specific timing sensitivity exists between
955           the retiring WFI/WFE instructions and the newly issued subsequent
956           instructions.  This sensitivity can result in a CPU hang scenario.
957           Workaround:
958           The software must insert either a Data Synchronization Barrier (DSB)
959           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
960           instruction
961 
962 config ARM_ERRATA_326103
963         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
964         depends on CPU_V6
965         help
966           Executing a SWP instruction to read-only memory does not set bit 11
967           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
968           treat the access as a read, preventing a COW from occurring and
969           causing the faulting task to livelock.
970 
971 config ARM_ERRATA_411920
972         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
973         depends on CPU_V6 || CPU_V6K
974         help
975           Invalidation of the Instruction Cache operation can
976           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
977           It does not affect the MPCore. This option enables the ARM Ltd.
978           recommended workaround.
979 
980 config ARM_ERRATA_430973
981         bool "ARM errata: Stale prediction on replaced interworking branch"
982         depends on CPU_V7
983         help
984           This option enables the workaround for the 430973 Cortex-A8
985           r1p* erratum. If a code sequence containing an ARM/Thumb
986           interworking branch is replaced with another code sequence at the
987           same virtual address, whether due to self-modifying code or virtual
988           to physical address re-mapping, Cortex-A8 does not recover from the
989           stale interworking branch prediction. This results in Cortex-A8
990           executing the new code sequence in the incorrect ARM or Thumb state.
991           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
992           and also flushes the branch target cache at every context switch.
993           Note that setting specific bits in the ACTLR register may not be
994           available in non-secure mode.
995 
996 config ARM_ERRATA_458693
997         bool "ARM errata: Processor deadlock when a false hazard is created"
998         depends on CPU_V7
999         depends on !ARCH_MULTIPLATFORM
1000         help
1001           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1002           erratum. For very specific sequences of memory operations, it is
1003           possible for a hazard condition intended for a cache line to instead
1004           be incorrectly associated with a different cache line. This false
1005           hazard might then cause a processor deadlock. The workaround enables
1006           the L1 caching of the NEON accesses and disables the PLD instruction
1007           in the ACTLR register. Note that setting specific bits in the ACTLR
1008           register may not be available in non-secure mode.
1009 
1010 config ARM_ERRATA_460075
1011         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1012         depends on CPU_V7
1013         depends on !ARCH_MULTIPLATFORM
1014         help
1015           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1016           erratum. Any asynchronous access to the L2 cache may encounter a
1017           situation in which recent store transactions to the L2 cache are lost
1018           and overwritten with stale memory contents from external memory. The
1019           workaround disables the write-allocate mode for the L2 cache via the
1020           ACTLR register. Note that setting specific bits in the ACTLR register
1021           may not be available in non-secure mode.
1022 
1023 config ARM_ERRATA_742230
1024         bool "ARM errata: DMB operation may be faulty"
1025         depends on CPU_V7 && SMP
1026         depends on !ARCH_MULTIPLATFORM
1027         help
1028           This option enables the workaround for the 742230 Cortex-A9
1029           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1030           between two write operations may not ensure the correct visibility
1031           ordering of the two writes. This workaround sets a specific bit in
1032           the diagnostic register of the Cortex-A9 which causes the DMB
1033           instruction to behave as a DSB, ensuring the correct behaviour of
1034           the two writes.
1035 
1036 config ARM_ERRATA_742231
1037         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1038         depends on CPU_V7 && SMP
1039         depends on !ARCH_MULTIPLATFORM
1040         help
1041           This option enables the workaround for the 742231 Cortex-A9
1042           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1043           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1044           accessing some data located in the same cache line, may get corrupted
1045           data due to bad handling of the address hazard when the line gets
1046           replaced from one of the CPUs at the same time as another CPU is
1047           accessing it. This workaround sets specific bits in the diagnostic
1048           register of the Cortex-A9 which reduces the linefill issuing
1049           capabilities of the processor.
1050 
1051 config ARM_ERRATA_643719
1052         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1053         depends on CPU_V7 && SMP
1054         default y
1055         help
1056           This option enables the workaround for the 643719 Cortex-A9 (prior to
1057           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1058           register returns zero when it should return one. The workaround
1059           corrects this value, ensuring cache maintenance operations which use
1060           it behave as intended and avoiding data corruption.
1061 
1062 config ARM_ERRATA_720789
1063         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1064         depends on CPU_V7
1065         help
1066           This option enables the workaround for the 720789 Cortex-A9 (prior to
1067           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1068           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1069           As a consequence of this erratum, some TLB entries which should be
1070           invalidated are not, resulting in an incoherency in the system page
1071           tables. The workaround changes the TLB flushing routines to invalidate
1072           entries regardless of the ASID.
1073 
1074 config ARM_ERRATA_743622
1075         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1076         depends on CPU_V7
1077         depends on !ARCH_MULTIPLATFORM
1078         help
1079           This option enables the workaround for the 743622 Cortex-A9
1080           (r2p*) erratum. Under very rare conditions, a faulty
1081           optimisation in the Cortex-A9 Store Buffer may lead to data
1082           corruption. This workaround sets a specific bit in the diagnostic
1083           register of the Cortex-A9 which disables the Store Buffer
1084           optimisation, preventing the defect from occurring. This has no
1085           visible impact on the overall performance or power consumption of the
1086           processor.
1087 
1088 config ARM_ERRATA_751472
1089         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1090         depends on CPU_V7
1091         depends on !ARCH_MULTIPLATFORM
1092         help
1093           This option enables the workaround for the 751472 Cortex-A9 (prior
1094           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1095           completion of a following broadcasted operation if the second
1096           operation is received by a CPU before the ICIALLUIS has completed,
1097           potentially leading to corrupted entries in the cache or TLB.
1098 
1099 config ARM_ERRATA_754322
1100         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1101         depends on CPU_V7
1102         help
1103           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1104           r3p*) erratum. A speculative memory access may cause a page table walk
1105           which starts prior to an ASID switch but completes afterwards. This
1106           can populate the micro-TLB with a stale entry which may be hit with
1107           the new ASID. This workaround places two dsb instructions in the mm
1108           switching code so that no page table walks can cross the ASID switch.
1109 
1110 config ARM_ERRATA_754327
1111         bool "ARM errata: no automatic Store Buffer drain"
1112         depends on CPU_V7 && SMP
1113         help
1114           This option enables the workaround for the 754327 Cortex-A9 (prior to
1115           r2p0) erratum. The Store Buffer does not have any automatic draining
1116           mechanism and therefore a livelock may occur if an external agent
1117           continuously polls a memory location waiting to observe an update.
1118           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1119           written polling loops from denying visibility of updates to memory.
1120 
1121 config ARM_ERRATA_364296
1122         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1123         depends on CPU_V6
1124         help
1125           This options enables the workaround for the 364296 ARM1136
1126           r0p2 erratum (possible cache data corruption with
1127           hit-under-miss enabled). It sets the undocumented bit 31 in
1128           the auxiliary control register and the FI bit in the control
1129           register, thus disabling hit-under-miss without putting the
1130           processor into full low interrupt latency mode. ARM11MPCore
1131           is not affected.
1132 
1133 config ARM_ERRATA_764369
1134         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1135         depends on CPU_V7 && SMP
1136         help
1137           This option enables the workaround for erratum 764369
1138           affecting Cortex-A9 MPCore with two or more processors (all
1139           current revisions). Under certain timing circumstances, a data
1140           cache line maintenance operation by MVA targeting an Inner
1141           Shareable memory region may fail to proceed up to either the
1142           Point of Coherency or to the Point of Unification of the
1143           system. This workaround adds a DSB instruction before the
1144           relevant cache maintenance functions and sets a specific bit
1145           in the diagnostic control register of the SCU.
1146 
1147 config ARM_ERRATA_775420
1148        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1149        depends on CPU_V7
1150        help
1151          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1152          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1153          operation aborts with MMU exception, it might cause the processor
1154          to deadlock. This workaround puts DSB before executing ISB if
1155          an abort may occur on cache maintenance.
1156 
1157 config ARM_ERRATA_798181
1158         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1159         depends on CPU_V7 && SMP
1160         help
1161           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1162           adequately shooting down all use of the old entries. This
1163           option enables the Linux kernel workaround for this erratum
1164           which sends an IPI to the CPUs that are running the same ASID
1165           as the one being invalidated.
1166 
1167 config ARM_ERRATA_773022
1168         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1169         depends on CPU_V7
1170         help
1171           This option enables the workaround for the 773022 Cortex-A15
1172           (up to r0p4) erratum. In certain rare sequences of code, the
1173           loop buffer may deliver incorrect instructions. This
1174           workaround disables the loop buffer to avoid the erratum.
1175 
1176 config ARM_ERRATA_818325_852422
1177         bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1178         depends on CPU_V7
1179         help
1180           This option enables the workaround for:
1181           - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1182             instruction might deadlock.  Fixed in r0p1.
1183           - Cortex-A12 852422: Execution of a sequence of instructions might
1184             lead to either a data corruption or a CPU deadlock.  Not fixed in
1185             any Cortex-A12 cores yet.
1186           This workaround for all both errata involves setting bit[12] of the
1187           Feature Register. This bit disables an optimisation applied to a
1188           sequence of 2 instructions that use opposing condition codes.
1189 
1190 config ARM_ERRATA_821420
1191         bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1192         depends on CPU_V7
1193         help
1194           This option enables the workaround for the 821420 Cortex-A12
1195           (all revs) erratum. In very rare timing conditions, a sequence
1196           of VMOV to Core registers instructions, for which the second
1197           one is in the shadow of a branch or abort, can lead to a
1198           deadlock when the VMOV instructions are issued out-of-order.
1199 
1200 config ARM_ERRATA_825619
1201         bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1202         depends on CPU_V7
1203         help
1204           This option enables the workaround for the 825619 Cortex-A12
1205           (all revs) erratum. Within rare timing constraints, executing a
1206           DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1207           and Device/Strongly-Ordered loads and stores might cause deadlock
1208 
1209 config ARM_ERRATA_852421
1210         bool "ARM errata: A17: DMB ST might fail to create order between stores"
1211         depends on CPU_V7
1212         help
1213           This option enables the workaround for the 852421 Cortex-A17
1214           (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1215           execution of a DMB ST instruction might fail to properly order
1216           stores from GroupA and stores from GroupB.
1217 
1218 config ARM_ERRATA_852423
1219         bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1220         depends on CPU_V7
1221         help
1222           This option enables the workaround for:
1223           - Cortex-A17 852423: Execution of a sequence of instructions might
1224             lead to either a data corruption or a CPU deadlock.  Not fixed in
1225             any Cortex-A17 cores yet.
1226           This is identical to Cortex-A12 erratum 852422.  It is a separate
1227           config option from the A12 erratum due to the way errata are checked
1228           for and handled.
1229 
1230 endmenu
1231 
1232 source "arch/arm/common/Kconfig"
1233 
1234 menu "Bus support"
1235 
1236 config ISA
1237         bool
1238         help
1239           Find out whether you have ISA slots on your motherboard.  ISA is the
1240           name of a bus system, i.e. the way the CPU talks to the other stuff
1241           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1242           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1243           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1244 
1245 # Select ISA DMA controller support
1246 config ISA_DMA
1247         bool
1248         select ISA_DMA_API
1249 
1250 # Select ISA DMA interface
1251 config ISA_DMA_API
1252         bool
1253 
1254 config PCI
1255         bool "PCI support" if MIGHT_HAVE_PCI
1256         help
1257           Find out whether you have a PCI motherboard. PCI is the name of a
1258           bus system, i.e. the way the CPU talks to the other stuff inside
1259           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1260           VESA. If you have PCI, say Y, otherwise N.
1261 
1262 config PCI_DOMAINS
1263         bool
1264         depends on PCI
1265 
1266 config PCI_DOMAINS_GENERIC
1267         def_bool PCI_DOMAINS
1268 
1269 config PCI_NANOENGINE
1270         bool "BSE nanoEngine PCI support"
1271         depends on SA1100_NANOENGINE
1272         help
1273           Enable PCI on the BSE nanoEngine board.
1274 
1275 config PCI_SYSCALL
1276         def_bool PCI
1277 
1278 config PCI_HOST_ITE8152
1279         bool
1280         depends on PCI && MACH_ARMCORE
1281         default y
1282         select DMABOUNCE
1283 
1284 source "drivers/pci/Kconfig"
1285 
1286 source "drivers/pcmcia/Kconfig"
1287 
1288 endmenu
1289 
1290 menu "Kernel Features"
1291 
1292 config HAVE_SMP
1293         bool
1294         help
1295           This option should be selected by machines which have an SMP-
1296           capable CPU.
1297 
1298           The only effect of this option is to make the SMP-related
1299           options available to the user for configuration.
1300 
1301 config SMP
1302         bool "Symmetric Multi-Processing"
1303         depends on CPU_V6K || CPU_V7
1304         depends on GENERIC_CLOCKEVENTS
1305         depends on HAVE_SMP
1306         depends on MMU || ARM_MPU
1307         select IRQ_WORK
1308         help
1309           This enables support for systems with more than one CPU. If you have
1310           a system with only one CPU, say N. If you have a system with more
1311           than one CPU, say Y.
1312 
1313           If you say N here, the kernel will run on uni- and multiprocessor
1314           machines, but will use only one CPU of a multiprocessor machine. If
1315           you say Y here, the kernel will run on many, but not all,
1316           uniprocessor machines. On a uniprocessor machine, the kernel
1317           will run faster if you say N here.
1318 
1319           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1320           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1321           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1322 
1323           If you don't know what to do here, say N.
1324 
1325 config SMP_ON_UP
1326         bool "Allow booting SMP kernel on uniprocessor systems"
1327         depends on SMP && !XIP_KERNEL && MMU
1328         default y
1329         help
1330           SMP kernels contain instructions which fail on non-SMP processors.
1331           Enabling this option allows the kernel to modify itself to make
1332           these instructions safe.  Disabling it allows about 1K of space
1333           savings.
1334 
1335           If you don't know what to do here, say Y.
1336 
1337 config ARM_CPU_TOPOLOGY
1338         bool "Support cpu topology definition"
1339         depends on SMP && CPU_V7
1340         default y
1341         help
1342           Support ARM cpu topology definition. The MPIDR register defines
1343           affinity between processors which is then used to describe the cpu
1344           topology of an ARM System.
1345 
1346 config SCHED_MC
1347         bool "Multi-core scheduler support"
1348         depends on ARM_CPU_TOPOLOGY
1349         help
1350           Multi-core scheduler support improves the CPU scheduler's decision
1351           making when dealing with multi-core CPU chips at a cost of slightly
1352           increased overhead in some places. If unsure say N here.
1353 
1354 config SCHED_SMT
1355         bool "SMT scheduler support"
1356         depends on ARM_CPU_TOPOLOGY
1357         help
1358           Improves the CPU scheduler's decision making when dealing with
1359           MultiThreading at a cost of slightly increased overhead in some
1360           places. If unsure say N here.
1361 
1362 config HAVE_ARM_SCU
1363         bool
1364         help
1365           This option enables support for the ARM system coherency unit
1366 
1367 config HAVE_ARM_ARCH_TIMER
1368         bool "Architected timer support"
1369         depends on CPU_V7
1370         select ARM_ARCH_TIMER
1371         select GENERIC_CLOCKEVENTS
1372         help
1373           This option enables support for the ARM architected timer
1374 
1375 config HAVE_ARM_TWD
1376         bool
1377         select CLKSRC_OF if OF
1378         help
1379           This options enables support for the ARM timer and watchdog unit
1380 
1381 config MCPM
1382         bool "Multi-Cluster Power Management"
1383         depends on CPU_V7 && SMP
1384         help
1385           This option provides the common power management infrastructure
1386           for (multi-)cluster based systems, such as big.LITTLE based
1387           systems.
1388 
1389 config MCPM_QUAD_CLUSTER
1390         bool
1391         depends on MCPM
1392         help
1393           To avoid wasting resources unnecessarily, MCPM only supports up
1394           to 2 clusters by default.
1395           Platforms with 3 or 4 clusters that use MCPM must select this
1396           option to allow the additional clusters to be managed.
1397 
1398 config BIG_LITTLE
1399         bool "big.LITTLE support (Experimental)"
1400         depends on CPU_V7 && SMP
1401         select MCPM
1402         help
1403           This option enables support selections for the big.LITTLE
1404           system architecture.
1405 
1406 config BL_SWITCHER
1407         bool "big.LITTLE switcher support"
1408         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1409         select CPU_PM
1410         help
1411           The big.LITTLE "switcher" provides the core functionality to
1412           transparently handle transition between a cluster of A15's
1413           and a cluster of A7's in a big.LITTLE system.
1414 
1415 config BL_SWITCHER_DUMMY_IF
1416         tristate "Simple big.LITTLE switcher user interface"
1417         depends on BL_SWITCHER && DEBUG_KERNEL
1418         help
1419           This is a simple and dummy char dev interface to control
1420           the big.LITTLE switcher core code.  It is meant for
1421           debugging purposes only.
1422 
1423 choice
1424         prompt "Memory split"
1425         depends on MMU
1426         default VMSPLIT_3G
1427         help
1428           Select the desired split between kernel and user memory.
1429 
1430           If you are not absolutely sure what you are doing, leave this
1431           option alone!
1432 
1433         config VMSPLIT_3G
1434                 bool "3G/1G user/kernel split"
1435         config VMSPLIT_3G_OPT
1436                 bool "3G/1G user/kernel split (for full 1G low memory)"
1437         config VMSPLIT_2G
1438                 bool "2G/2G user/kernel split"
1439         config VMSPLIT_1G
1440                 bool "1G/3G user/kernel split"
1441 endchoice
1442 
1443 config PAGE_OFFSET
1444         hex
1445         default PHYS_OFFSET if !MMU
1446         default 0x40000000 if VMSPLIT_1G
1447         default 0x80000000 if VMSPLIT_2G
1448         default 0xB0000000 if VMSPLIT_3G_OPT
1449         default 0xC0000000
1450 
1451 config NR_CPUS
1452         int "Maximum number of CPUs (2-32)"
1453         range 2 32
1454         depends on SMP
1455         default "4"
1456 
1457 config HOTPLUG_CPU
1458         bool "Support for hot-pluggable CPUs"
1459         depends on SMP
1460         help
1461           Say Y here to experiment with turning CPUs off and on.  CPUs
1462           can be controlled through /sys/devices/system/cpu.
1463 
1464 config ARM_PSCI
1465         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1466         depends on HAVE_ARM_SMCCC
1467         select ARM_PSCI_FW
1468         help
1469           Say Y here if you want Linux to communicate with system firmware
1470           implementing the PSCI specification for CPU-centric power
1471           management operations described in ARM document number ARM DEN
1472           0022A ("Power State Coordination Interface System Software on
1473           ARM processors").
1474 
1475 # The GPIO number here must be sorted by descending number. In case of
1476 # a multiplatform kernel, we just want the highest value required by the
1477 # selected platforms.
1478 config ARCH_NR_GPIO
1479         int
1480         default 1024 if ARCH_BRCMSTB || ARCH_SHMOBILE || ARCH_TEGRA || \
1481                 ARCH_ZYNQ
1482         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1483                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1484         default 416 if ARCH_SUNXI
1485         default 392 if ARCH_U8500
1486         default 352 if ARCH_VT8500
1487         default 288 if ARCH_ROCKCHIP
1488         default 264 if MACH_H4700
1489         default 0
1490         help
1491           Maximum number of GPIOs in the system.
1492 
1493           If unsure, leave the default value.
1494 
1495 source kernel/Kconfig.preempt
1496 
1497 config HZ_FIXED
1498         int
1499         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1500                 ARCH_S5PV210 || ARCH_EXYNOS4
1501         default 128 if SOC_AT91RM9200
1502         default 0
1503 
1504 choice
1505         depends on HZ_FIXED = 0
1506         prompt "Timer frequency"
1507 
1508 config HZ_100
1509         bool "100 Hz"
1510 
1511 config HZ_200
1512         bool "200 Hz"
1513 
1514 config HZ_250
1515         bool "250 Hz"
1516 
1517 config HZ_300
1518         bool "300 Hz"
1519 
1520 config HZ_500
1521         bool "500 Hz"
1522 
1523 config HZ_1000
1524         bool "1000 Hz"
1525 
1526 endchoice
1527 
1528 config HZ
1529         int
1530         default HZ_FIXED if HZ_FIXED != 0
1531         default 100 if HZ_100
1532         default 200 if HZ_200
1533         default 250 if HZ_250
1534         default 300 if HZ_300
1535         default 500 if HZ_500
1536         default 1000
1537 
1538 config SCHED_HRTICK
1539         def_bool HIGH_RES_TIMERS
1540 
1541 config THUMB2_KERNEL
1542         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1543         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1544         default y if CPU_THUMBONLY
1545         select AEABI
1546         select ARM_ASM_UNIFIED
1547         select ARM_UNWIND
1548         help
1549           By enabling this option, the kernel will be compiled in
1550           Thumb-2 mode. A compiler/assembler that understand the unified
1551           ARM-Thumb syntax is needed.
1552 
1553           If unsure, say N.
1554 
1555 config THUMB2_AVOID_R_ARM_THM_JUMP11
1556         bool "Work around buggy Thumb-2 short branch relocations in gas"
1557         depends on THUMB2_KERNEL && MODULES
1558         default y
1559         help
1560           Various binutils versions can resolve Thumb-2 branches to
1561           locally-defined, preemptible global symbols as short-range "b.n"
1562           branch instructions.
1563 
1564           This is a problem, because there's no guarantee the final
1565           destination of the symbol, or any candidate locations for a
1566           trampoline, are within range of the branch.  For this reason, the
1567           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1568           relocation in modules at all, and it makes little sense to add
1569           support.
1570 
1571           The symptom is that the kernel fails with an "unsupported
1572           relocation" error when loading some modules.
1573 
1574           Until fixed tools are available, passing
1575           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1576           code which hits this problem, at the cost of a bit of extra runtime
1577           stack usage in some cases.
1578 
1579           The problem is described in more detail at:
1580               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1581 
1582           Only Thumb-2 kernels are affected.
1583 
1584           Unless you are sure your tools don't have this problem, say Y.
1585 
1586 config ARM_ASM_UNIFIED
1587         bool
1588 
1589 config ARM_PATCH_IDIV
1590         bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1591         depends on CPU_32v7 && !XIP_KERNEL
1592         default y
1593         help
1594           The ARM compiler inserts calls to __aeabi_idiv() and
1595           __aeabi_uidiv() when it needs to perform division on signed
1596           and unsigned integers. Some v7 CPUs have support for the sdiv
1597           and udiv instructions that can be used to implement those
1598           functions.
1599 
1600           Enabling this option allows the kernel to modify itself to
1601           replace the first two instructions of these library functions
1602           with the sdiv or udiv plus "bx lr" instructions when the CPU
1603           it is running on supports them. Typically this will be faster
1604           and less power intensive than running the original library
1605           code to do integer division.
1606 
1607 config AEABI
1608         bool "Use the ARM EABI to compile the kernel"
1609         help
1610           This option allows for the kernel to be compiled using the latest
1611           ARM ABI (aka EABI).  This is only useful if you are using a user
1612           space environment that is also compiled with EABI.
1613 
1614           Since there are major incompatibilities between the legacy ABI and
1615           EABI, especially with regard to structure member alignment, this
1616           option also changes the kernel syscall calling convention to
1617           disambiguate both ABIs and allow for backward compatibility support
1618           (selected with CONFIG_OABI_COMPAT).
1619 
1620           To use this you need GCC version 4.0.0 or later.
1621 
1622 config OABI_COMPAT
1623         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1624         depends on AEABI && !THUMB2_KERNEL
1625         help
1626           This option preserves the old syscall interface along with the
1627           new (ARM EABI) one. It also provides a compatibility layer to
1628           intercept syscalls that have structure arguments which layout
1629           in memory differs between the legacy ABI and the new ARM EABI
1630           (only for non "thumb" binaries). This option adds a tiny
1631           overhead to all syscalls and produces a slightly larger kernel.
1632 
1633           The seccomp filter system will not be available when this is
1634           selected, since there is no way yet to sensibly distinguish
1635           between calling conventions during filtering.
1636 
1637           If you know you'll be using only pure EABI user space then you
1638           can say N here. If this option is not selected and you attempt
1639           to execute a legacy ABI binary then the result will be
1640           UNPREDICTABLE (in fact it can be predicted that it won't work
1641           at all). If in doubt say N.
1642 
1643 config ARCH_HAS_HOLES_MEMORYMODEL
1644         bool
1645 
1646 config ARCH_SPARSEMEM_ENABLE
1647         bool
1648 
1649 config ARCH_SPARSEMEM_DEFAULT
1650         def_bool ARCH_SPARSEMEM_ENABLE
1651 
1652 config ARCH_SELECT_MEMORY_MODEL
1653         def_bool ARCH_SPARSEMEM_ENABLE
1654 
1655 config HAVE_ARCH_PFN_VALID
1656         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1657 
1658 config HAVE_GENERIC_RCU_GUP
1659         def_bool y
1660         depends on ARM_LPAE
1661 
1662 config HIGHMEM
1663         bool "High Memory Support"
1664         depends on MMU
1665         help
1666           The address space of ARM processors is only 4 Gigabytes large
1667           and it has to accommodate user address space, kernel address
1668           space as well as some memory mapped IO. That means that, if you
1669           have a large amount of physical memory and/or IO, not all of the
1670           memory can be "permanently mapped" by the kernel. The physical
1671           memory that is not permanently mapped is called "high memory".
1672 
1673           Depending on the selected kernel/user memory split, minimum
1674           vmalloc space and actual amount of RAM, you may not need this
1675           option which should result in a slightly faster kernel.
1676 
1677           If unsure, say n.
1678 
1679 config HIGHPTE
1680         bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1681         depends on HIGHMEM
1682         default y
1683         help
1684           The VM uses one page of physical memory for each page table.
1685           For systems with a lot of processes, this can use a lot of
1686           precious low memory, eventually leading to low memory being
1687           consumed by page tables.  Setting this option will allow
1688           user-space 2nd level page tables to reside in high memory.
1689 
1690 config CPU_SW_DOMAIN_PAN
1691         bool "Enable use of CPU domains to implement privileged no-access"
1692         depends on MMU && !ARM_LPAE
1693         default y
1694         help
1695           Increase kernel security by ensuring that normal kernel accesses
1696           are unable to access userspace addresses.  This can help prevent
1697           use-after-free bugs becoming an exploitable privilege escalation
1698           by ensuring that magic values (such as LIST_POISON) will always
1699           fault when dereferenced.
1700 
1701           CPUs with low-vector mappings use a best-efforts implementation.
1702           Their lower 1MB needs to remain accessible for the vectors, but
1703           the remainder of userspace will become appropriately inaccessible.
1704 
1705 config HW_PERF_EVENTS
1706         def_bool y
1707         depends on ARM_PMU
1708 
1709 config SYS_SUPPORTS_HUGETLBFS
1710        def_bool y
1711        depends on ARM_LPAE
1712 
1713 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1714        def_bool y
1715        depends on ARM_LPAE
1716 
1717 config ARCH_WANT_GENERAL_HUGETLB
1718         def_bool y
1719 
1720 config ARM_MODULE_PLTS
1721         bool "Use PLTs to allow module memory to spill over into vmalloc area"
1722         depends on MODULES
1723         help
1724           Allocate PLTs when loading modules so that jumps and calls whose
1725           targets are too far away for their relative offsets to be encoded
1726           in the instructions themselves can be bounced via veneers in the
1727           module's PLT. This allows modules to be allocated in the generic
1728           vmalloc area after the dedicated module memory area has been
1729           exhausted. The modules will use slightly more memory, but after
1730           rounding up to page size, the actual memory footprint is usually
1731           the same.
1732 
1733           Say y if you are getting out of memory errors while loading modules
1734 
1735 source "mm/Kconfig"
1736 
1737 config FORCE_MAX_ZONEORDER
1738         int "Maximum zone order"
1739         default "12" if SOC_AM33XX
1740         default "9" if SA1111 || ARCH_EFM32
1741         default "11"
1742         help
1743           The kernel memory allocator divides physically contiguous memory
1744           blocks into "zones", where each zone is a power of two number of
1745           pages.  This option selects the largest power of two that the kernel
1746           keeps in the memory allocator.  If you need to allocate very large
1747           blocks of physically contiguous memory, then you may need to
1748           increase this value.
1749 
1750           This config option is actually maximum order plus one. For example,
1751           a value of 11 means that the largest free memory block is 2^10 pages.
1752 
1753 config ALIGNMENT_TRAP
1754         bool
1755         depends on CPU_CP15_MMU
1756         default y if !ARCH_EBSA110
1757         select HAVE_PROC_CPU if PROC_FS
1758         help
1759           ARM processors cannot fetch/store information which is not
1760           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1761           address divisible by 4. On 32-bit ARM processors, these non-aligned
1762           fetch/store instructions will be emulated in software if you say
1763           here, which has a severe performance impact. This is necessary for
1764           correct operation of some network protocols. With an IP-only
1765           configuration it is safe to say N, otherwise say Y.
1766 
1767 config UACCESS_WITH_MEMCPY
1768         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1769         depends on MMU
1770         default y if CPU_FEROCEON
1771         help
1772           Implement faster copy_to_user and clear_user methods for CPU
1773           cores where a 8-word STM instruction give significantly higher
1774           memory write throughput than a sequence of individual 32bit stores.
1775 
1776           A possible side effect is a slight increase in scheduling latency
1777           between threads sharing the same address space if they invoke
1778           such copy operations with large buffers.
1779 
1780           However, if the CPU data cache is using a write-allocate mode,
1781           this option is unlikely to provide any performance gain.
1782 
1783 config SECCOMP
1784         bool
1785         prompt "Enable seccomp to safely compute untrusted bytecode"
1786         ---help---
1787           This kernel feature is useful for number crunching applications
1788           that may need to compute untrusted bytecode during their
1789           execution. By using pipes or other transports made available to
1790           the process as file descriptors supporting the read/write
1791           syscalls, it's possible to isolate those applications in
1792           their own address space using seccomp. Once seccomp is
1793           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1794           and the task is only allowed to execute a few safe syscalls
1795           defined by each seccomp mode.
1796 
1797 config SWIOTLB
1798         def_bool y
1799 
1800 config IOMMU_HELPER
1801         def_bool SWIOTLB
1802 
1803 config PARAVIRT
1804         bool "Enable paravirtualization code"
1805         help
1806           This changes the kernel so it can modify itself when it is run
1807           under a hypervisor, potentially improving performance significantly
1808           over full virtualization.
1809 
1810 config PARAVIRT_TIME_ACCOUNTING
1811         bool "Paravirtual steal time accounting"
1812         select PARAVIRT
1813         default n
1814         help
1815           Select this option to enable fine granularity task steal time
1816           accounting. Time spent executing other tasks in parallel with
1817           the current vCPU is discounted from the vCPU power. To account for
1818           that, there can be a small performance impact.
1819 
1820           If in doubt, say N here.
1821 
1822 config XEN_DOM0
1823         def_bool y
1824         depends on XEN
1825 
1826 config XEN
1827         bool "Xen guest support on ARM"
1828         depends on ARM && AEABI && OF
1829         depends on CPU_V7 && !CPU_V6
1830         depends on !GENERIC_ATOMIC64
1831         depends on MMU
1832         select ARCH_DMA_ADDR_T_64BIT
1833         select ARM_PSCI
1834         select SWIOTLB_XEN
1835         select PARAVIRT
1836         help
1837           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1838 
1839 endmenu
1840 
1841 menu "Boot options"
1842 
1843 config USE_OF
1844         bool "Flattened Device Tree support"
1845         select IRQ_DOMAIN
1846         select OF
1847         help
1848           Include support for flattened device tree machine descriptions.
1849 
1850 config ATAGS
1851         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1852         default y
1853         help
1854           This is the traditional way of passing data to the kernel at boot
1855           time. If you are solely relying on the flattened device tree (or
1856           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1857           to remove ATAGS support from your kernel binary.  If unsure,
1858           leave this to y.
1859 
1860 config DEPRECATED_PARAM_STRUCT
1861         bool "Provide old way to pass kernel parameters"
1862         depends on ATAGS
1863         help
1864           This was deprecated in 2001 and announced to live on for 5 years.
1865           Some old boot loaders still use this way.
1866 
1867 # Compressed boot loader in ROM.  Yes, we really want to ask about
1868 # TEXT and BSS so we preserve their values in the config files.
1869 config ZBOOT_ROM_TEXT
1870         hex "Compressed ROM boot loader base address"
1871         default "0"
1872         help
1873           The physical address at which the ROM-able zImage is to be
1874           placed in the target.  Platforms which normally make use of
1875           ROM-able zImage formats normally set this to a suitable
1876           value in their defconfig file.
1877 
1878           If ZBOOT_ROM is not enabled, this has no effect.
1879 
1880 config ZBOOT_ROM_BSS
1881         hex "Compressed ROM boot loader BSS address"
1882         default "0"
1883         help
1884           The base address of an area of read/write memory in the target
1885           for the ROM-able zImage which must be available while the
1886           decompressor is running. It must be large enough to hold the
1887           entire decompressed kernel plus an additional 128 KiB.
1888           Platforms which normally make use of ROM-able zImage formats
1889           normally set this to a suitable value in their defconfig file.
1890 
1891           If ZBOOT_ROM is not enabled, this has no effect.
1892 
1893 config ZBOOT_ROM
1894         bool "Compressed boot loader in ROM/flash"
1895         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1896         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1897         help
1898           Say Y here if you intend to execute your compressed kernel image
1899           (zImage) directly from ROM or flash.  If unsure, say N.
1900 
1901 config ARM_APPENDED_DTB
1902         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1903         depends on OF
1904         help
1905           With this option, the boot code will look for a device tree binary
1906           (DTB) appended to zImage
1907           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1908 
1909           This is meant as a backward compatibility convenience for those
1910           systems with a bootloader that can't be upgraded to accommodate
1911           the documented boot protocol using a device tree.
1912 
1913           Beware that there is very little in terms of protection against
1914           this option being confused by leftover garbage in memory that might
1915           look like a DTB header after a reboot if no actual DTB is appended
1916           to zImage.  Do not leave this option active in a production kernel
1917           if you don't intend to always append a DTB.  Proper passing of the
1918           location into r2 of a bootloader provided DTB is always preferable
1919           to this option.
1920 
1921 config ARM_ATAG_DTB_COMPAT
1922         bool "Supplement the appended DTB with traditional ATAG information"
1923         depends on ARM_APPENDED_DTB
1924         help
1925           Some old bootloaders can't be updated to a DTB capable one, yet
1926           they provide ATAGs with memory configuration, the ramdisk address,
1927           the kernel cmdline string, etc.  Such information is dynamically
1928           provided by the bootloader and can't always be stored in a static
1929           DTB.  To allow a device tree enabled kernel to be used with such
1930           bootloaders, this option allows zImage to extract the information
1931           from the ATAG list and store it at run time into the appended DTB.
1932 
1933 choice
1934         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1935         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1936 
1937 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1938         bool "Use bootloader kernel arguments if available"
1939         help
1940           Uses the command-line options passed by the boot loader instead of
1941           the device tree bootargs property. If the boot loader doesn't provide
1942           any, the device tree bootargs property will be used.
1943 
1944 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1945         bool "Extend with bootloader kernel arguments"
1946         help
1947           The command-line arguments provided by the boot loader will be
1948           appended to the the device tree bootargs property.
1949 
1950 endchoice
1951 
1952 config CMDLINE
1953         string "Default kernel command string"
1954         default ""
1955         help
1956           On some architectures (EBSA110 and CATS), there is currently no way
1957           for the boot loader to pass arguments to the kernel. For these
1958           architectures, you should supply some command-line options at build
1959           time by entering them here. As a minimum, you should specify the
1960           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1961 
1962 choice
1963         prompt "Kernel command line type" if CMDLINE != ""
1964         default CMDLINE_FROM_BOOTLOADER
1965         depends on ATAGS
1966 
1967 config CMDLINE_FROM_BOOTLOADER
1968         bool "Use bootloader kernel arguments if available"
1969         help
1970           Uses the command-line options passed by the boot loader. If
1971           the boot loader doesn't provide any, the default kernel command
1972           string provided in CMDLINE will be used.
1973 
1974 config CMDLINE_EXTEND
1975         bool "Extend bootloader kernel arguments"
1976         help
1977           The command-line arguments provided by the boot loader will be
1978           appended to the default kernel command string.
1979 
1980 config CMDLINE_FORCE
1981         bool "Always use the default kernel command string"
1982         help
1983           Always use the default kernel command string, even if the boot
1984           loader passes other arguments to the kernel.
1985           This is useful if you cannot or don't want to change the
1986           command-line options your boot loader passes to the kernel.
1987 endchoice
1988 
1989 config XIP_KERNEL
1990         bool "Kernel Execute-In-Place from ROM"
1991         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1992         help
1993           Execute-In-Place allows the kernel to run from non-volatile storage
1994           directly addressable by the CPU, such as NOR flash. This saves RAM
1995           space since the text section of the kernel is not loaded from flash
1996           to RAM.  Read-write sections, such as the data section and stack,
1997           are still copied to RAM.  The XIP kernel is not compressed since
1998           it has to run directly from flash, so it will take more space to
1999           store it.  The flash address used to link the kernel object files,
2000           and for storing it, is configuration dependent. Therefore, if you
2001           say Y here, you must know the proper physical address where to
2002           store the kernel image depending on your own flash memory usage.
2003 
2004           Also note that the make target becomes "make xipImage" rather than
2005           "make zImage" or "make Image".  The final kernel binary to put in
2006           ROM memory will be arch/arm/boot/xipImage.
2007 
2008           If unsure, say N.
2009 
2010 config XIP_PHYS_ADDR
2011         hex "XIP Kernel Physical Location"
2012         depends on XIP_KERNEL
2013         default "0x00080000"
2014         help
2015           This is the physical address in your flash memory the kernel will
2016           be linked for and stored to.  This address is dependent on your
2017           own flash usage.
2018 
2019 config KEXEC
2020         bool "Kexec system call (EXPERIMENTAL)"
2021         depends on (!SMP || PM_SLEEP_SMP)
2022         depends on !CPU_V7M
2023         select KEXEC_CORE
2024         help
2025           kexec is a system call that implements the ability to shutdown your
2026           current kernel, and to start another kernel.  It is like a reboot
2027           but it is independent of the system firmware.   And like a reboot
2028           you can start any kernel with it, not just Linux.
2029 
2030           It is an ongoing process to be certain the hardware in a machine
2031           is properly shutdown, so do not be surprised if this code does not
2032           initially work for you.
2033 
2034 config ATAGS_PROC
2035         bool "Export atags in procfs"
2036         depends on ATAGS && KEXEC
2037         default y
2038         help
2039           Should the atags used to boot the kernel be exported in an "atags"
2040           file in procfs. Useful with kexec.
2041 
2042 config CRASH_DUMP
2043         bool "Build kdump crash kernel (EXPERIMENTAL)"
2044         help
2045           Generate crash dump after being started by kexec. This should
2046           be normally only set in special crash dump kernels which are
2047           loaded in the main kernel with kexec-tools into a specially
2048           reserved region and then later executed after a crash by
2049           kdump/kexec. The crash dump kernel must be compiled to a
2050           memory address not used by the main kernel
2051 
2052           For more details see Documentation/kdump/kdump.txt
2053 
2054 config AUTO_ZRELADDR
2055         bool "Auto calculation of the decompressed kernel image address"
2056         help
2057           ZRELADDR is the physical address where the decompressed kernel
2058           image will be placed. If AUTO_ZRELADDR is selected, the address
2059           will be determined at run-time by masking the current IP with
2060           0xf8000000. This assumes the zImage being placed in the first 128MB
2061           from start of memory.
2062 
2063 config EFI_STUB
2064         bool
2065 
2066 config EFI
2067         bool "UEFI runtime support"
2068         depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
2069         select UCS2_STRING
2070         select EFI_PARAMS_FROM_FDT
2071         select EFI_STUB
2072         select EFI_ARMSTUB
2073         select EFI_RUNTIME_WRAPPERS
2074         ---help---
2075           This option provides support for runtime services provided
2076           by UEFI firmware (such as non-volatile variables, realtime
2077           clock, and platform reset). A UEFI stub is also provided to
2078           allow the kernel to be booted as an EFI application. This
2079           is only useful for kernels that may run on systems that have
2080           UEFI firmware.
2081 
2082 endmenu
2083 
2084 menu "CPU Power Management"
2085 
2086 source "drivers/cpufreq/Kconfig"
2087 
2088 source "drivers/cpuidle/Kconfig"
2089 
2090 endmenu
2091 
2092 menu "Floating point emulation"
2093 
2094 comment "At least one emulation must be selected"
2095 
2096 config FPE_NWFPE
2097         bool "NWFPE math emulation"
2098         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2099         ---help---
2100           Say Y to include the NWFPE floating point emulator in the kernel.
2101           This is necessary to run most binaries. Linux does not currently
2102           support floating point hardware so you need to say Y here even if
2103           your machine has an FPA or floating point co-processor podule.
2104 
2105           You may say N here if you are going to load the Acorn FPEmulator
2106           early in the bootup.
2107 
2108 config FPE_NWFPE_XP
2109         bool "Support extended precision"
2110         depends on FPE_NWFPE
2111         help
2112           Say Y to include 80-bit support in the kernel floating-point
2113           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2114           Note that gcc does not generate 80-bit operations by default,
2115           so in most cases this option only enlarges the size of the
2116           floating point emulator without any good reason.
2117 
2118           You almost surely want to say N here.
2119 
2120 config FPE_FASTFPE
2121         bool "FastFPE math emulation (EXPERIMENTAL)"
2122         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2123         ---help---
2124           Say Y here to include the FAST floating point emulator in the kernel.
2125           This is an experimental much faster emulator which now also has full
2126           precision for the mantissa.  It does not support any exceptions.
2127           It is very simple, and approximately 3-6 times faster than NWFPE.
2128 
2129           It should be sufficient for most programs.  It may be not suitable
2130           for scientific calculations, but you have to check this for yourself.
2131           If you do not feel you need a faster FP emulation you should better
2132           choose NWFPE.
2133 
2134 config VFP
2135         bool "VFP-format floating point maths"
2136         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2137         help
2138           Say Y to include VFP support code in the kernel. This is needed
2139           if your hardware includes a VFP unit.
2140 
2141           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2142           release notes and additional status information.
2143 
2144           Say N if your target does not have VFP hardware.
2145 
2146 config VFPv3
2147         bool
2148         depends on VFP
2149         default y if CPU_V7
2150 
2151 config NEON
2152         bool "Advanced SIMD (NEON) Extension support"
2153         depends on VFPv3 && CPU_V7
2154         help
2155           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2156           Extension.
2157 
2158 config KERNEL_MODE_NEON
2159         bool "Support for NEON in kernel mode"
2160         depends on NEON && AEABI
2161         help
2162           Say Y to include support for NEON in kernel mode.
2163 
2164 endmenu
2165 
2166 menu "Userspace binary formats"
2167 
2168 source "fs/Kconfig.binfmt"
2169 
2170 endmenu
2171 
2172 menu "Power management options"
2173 
2174 source "kernel/power/Kconfig"
2175 
2176 config ARCH_SUSPEND_POSSIBLE
2177         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2178                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2179         def_bool y
2180 
2181 config ARM_CPU_SUSPEND
2182         def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
2183         depends on ARCH_SUSPEND_POSSIBLE
2184 
2185 config ARCH_HIBERNATION_POSSIBLE
2186         bool
2187         depends on MMU
2188         default y if ARCH_SUSPEND_POSSIBLE
2189 
2190 endmenu
2191 
2192 source "net/Kconfig"
2193 
2194 source "drivers/Kconfig"
2195 
2196 source "drivers/firmware/Kconfig"
2197 
2198 source "fs/Kconfig"
2199 
2200 source "arch/arm/Kconfig.debug"
2201 
2202 source "security/Kconfig"
2203 
2204 source "crypto/Kconfig"
2205 if CRYPTO
2206 source "arch/arm/crypto/Kconfig"
2207 endif
2208 
2209 source "lib/Kconfig"
2210 
2211 source "arch/arm/kvm/Kconfig"

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