Version:  2.0.40 2.2.26 2.4.37 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15 3.16 3.17 3.18 3.19 4.0 4.1

Linux/arch/arm/Kconfig

  1 config ARM
  2         bool
  3         default y
  4         select ARCH_HAS_ATOMIC64_DEC_IF_POSITIVE
  5         select ARCH_HAS_ELF_RANDOMIZE
  6         select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
  7         select ARCH_HAVE_CUSTOM_GPIO_H
  8         select ARCH_HAS_GCOV_PROFILE_ALL
  9         select ARCH_MIGHT_HAVE_PC_PARPORT
 10         select ARCH_SUPPORTS_ATOMIC_RMW
 11         select ARCH_USE_BUILTIN_BSWAP
 12         select ARCH_USE_CMPXCHG_LOCKREF
 13         select ARCH_WANT_IPC_PARSE_VERSION
 14         select BUILDTIME_EXTABLE_SORT if MMU
 15         select CLONE_BACKWARDS
 16         select CPU_PM if (SUSPEND || CPU_IDLE)
 17         select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
 18         select GENERIC_ALLOCATOR
 19         select GENERIC_ATOMIC64 if (CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI)
 20         select GENERIC_CLOCKEVENTS_BROADCAST if SMP
 21         select GENERIC_IDLE_POLL_SETUP
 22         select GENERIC_IRQ_PROBE
 23         select GENERIC_IRQ_SHOW
 24         select GENERIC_IRQ_SHOW_LEVEL
 25         select GENERIC_PCI_IOMAP
 26         select GENERIC_SCHED_CLOCK
 27         select GENERIC_SMP_IDLE_THREAD
 28         select GENERIC_STRNCPY_FROM_USER
 29         select GENERIC_STRNLEN_USER
 30         select HANDLE_DOMAIN_IRQ
 31         select HARDIRQS_SW_RESEND
 32         select HAVE_ARCH_AUDITSYSCALL if (AEABI && !OABI_COMPAT)
 33         select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
 34         select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL
 35         select HAVE_ARCH_KGDB
 36         select HAVE_ARCH_SECCOMP_FILTER if (AEABI && !OABI_COMPAT)
 37         select HAVE_ARCH_TRACEHOOK
 38         select HAVE_BPF_JIT
 39         select HAVE_CC_STACKPROTECTOR
 40         select HAVE_CONTEXT_TRACKING
 41         select HAVE_C_RECORDMCOUNT
 42         select HAVE_DEBUG_KMEMLEAK
 43         select HAVE_DMA_API_DEBUG
 44         select HAVE_DMA_ATTRS
 45         select HAVE_DMA_CONTIGUOUS if MMU
 46         select HAVE_DYNAMIC_FTRACE if (!XIP_KERNEL)
 47         select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
 48         select HAVE_FTRACE_MCOUNT_RECORD if (!XIP_KERNEL)
 49         select HAVE_FUNCTION_GRAPH_TRACER if (!THUMB2_KERNEL)
 50         select HAVE_FUNCTION_TRACER if (!XIP_KERNEL)
 51         select HAVE_GENERIC_DMA_COHERENT
 52         select HAVE_HW_BREAKPOINT if (PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7))
 53         select HAVE_IDE if PCI || ISA || PCMCIA
 54         select HAVE_IRQ_TIME_ACCOUNTING
 55         select HAVE_KERNEL_GZIP
 56         select HAVE_KERNEL_LZ4
 57         select HAVE_KERNEL_LZMA
 58         select HAVE_KERNEL_LZO
 59         select HAVE_KERNEL_XZ
 60         select HAVE_KPROBES if !XIP_KERNEL
 61         select HAVE_KRETPROBES if (HAVE_KPROBES)
 62         select HAVE_MEMBLOCK
 63         select HAVE_MOD_ARCH_SPECIFIC if ARM_UNWIND
 64         select HAVE_OPROFILE if (HAVE_PERF_EVENTS)
 65         select HAVE_OPTPROBES if !THUMB2_KERNEL
 66         select HAVE_PERF_EVENTS
 67         select HAVE_PERF_REGS
 68         select HAVE_PERF_USER_STACK_DUMP
 69         select HAVE_RCU_TABLE_FREE if (SMP && ARM_LPAE)
 70         select HAVE_REGS_AND_STACK_ACCESS_API
 71         select HAVE_SYSCALL_TRACEPOINTS
 72         select HAVE_UID16
 73         select HAVE_VIRT_CPU_ACCOUNTING_GEN
 74         select IRQ_FORCED_THREADING
 75         select MODULES_USE_ELF_REL
 76         select NO_BOOTMEM
 77         select OLD_SIGACTION
 78         select OLD_SIGSUSPEND3
 79         select PERF_USE_VMALLOC
 80         select RTC_LIB
 81         select SYS_SUPPORTS_APM_EMULATION
 82         # Above selects are sorted alphabetically; please add new ones
 83         # according to that.  Thanks.
 84         help
 85           The ARM series is a line of low-power-consumption RISC chip designs
 86           licensed by ARM Ltd and targeted at embedded applications and
 87           handhelds such as the Compaq IPAQ.  ARM-based PCs are no longer
 88           manufactured, but legacy ARM-based PC hardware remains popular in
 89           Europe.  There is an ARM Linux project with a web page at
 90           <http://www.arm.linux.org.uk/>.
 91 
 92 config ARM_HAS_SG_CHAIN
 93         select ARCH_HAS_SG_CHAIN
 94         bool
 95 
 96 config NEED_SG_DMA_LENGTH
 97         bool
 98 
 99 config ARM_DMA_USE_IOMMU
100         bool
101         select ARM_HAS_SG_CHAIN
102         select NEED_SG_DMA_LENGTH
103 
104 if ARM_DMA_USE_IOMMU
105 
106 config ARM_DMA_IOMMU_ALIGNMENT
107         int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
108         range 4 9
109         default 8
110         help
111           DMA mapping framework by default aligns all buffers to the smallest
112           PAGE_SIZE order which is greater than or equal to the requested buffer
113           size. This works well for buffers up to a few hundreds kilobytes, but
114           for larger buffers it just a waste of address space. Drivers which has
115           relatively small addressing window (like 64Mib) might run out of
116           virtual space with just a few allocations.
117 
118           With this parameter you can specify the maximum PAGE_SIZE order for
119           DMA IOMMU buffers. Larger buffers will be aligned only to this
120           specified order. The order is expressed as a power of two multiplied
121           by the PAGE_SIZE.
122 
123 endif
124 
125 config MIGHT_HAVE_PCI
126         bool
127 
128 config SYS_SUPPORTS_APM_EMULATION
129         bool
130 
131 config HAVE_TCM
132         bool
133         select GENERIC_ALLOCATOR
134 
135 config HAVE_PROC_CPU
136         bool
137 
138 config NO_IOPORT_MAP
139         bool
140 
141 config EISA
142         bool
143         ---help---
144           The Extended Industry Standard Architecture (EISA) bus was
145           developed as an open alternative to the IBM MicroChannel bus.
146 
147           The EISA bus provided some of the features of the IBM MicroChannel
148           bus while maintaining backward compatibility with cards made for
149           the older ISA bus.  The EISA bus saw limited use between 1988 and
150           1995 when it was made obsolete by the PCI bus.
151 
152           Say Y here if you are building a kernel for an EISA-based machine.
153 
154           Otherwise, say N.
155 
156 config SBUS
157         bool
158 
159 config STACKTRACE_SUPPORT
160         bool
161         default y
162 
163 config HAVE_LATENCYTOP_SUPPORT
164         bool
165         depends on !SMP
166         default y
167 
168 config LOCKDEP_SUPPORT
169         bool
170         default y
171 
172 config TRACE_IRQFLAGS_SUPPORT
173         bool
174         default y
175 
176 config RWSEM_XCHGADD_ALGORITHM
177         bool
178         default y
179 
180 config ARCH_HAS_ILOG2_U32
181         bool
182 
183 config ARCH_HAS_ILOG2_U64
184         bool
185 
186 config ARCH_HAS_BANDGAP
187         bool
188 
189 config GENERIC_HWEIGHT
190         bool
191         default y
192 
193 config GENERIC_CALIBRATE_DELAY
194         bool
195         default y
196 
197 config ARCH_MAY_HAVE_PC_FDC
198         bool
199 
200 config ZONE_DMA
201         bool
202 
203 config NEED_DMA_MAP_STATE
204        def_bool y
205 
206 config ARCH_SUPPORTS_UPROBES
207         def_bool y
208 
209 config ARCH_HAS_DMA_SET_COHERENT_MASK
210         bool
211 
212 config GENERIC_ISA_DMA
213         bool
214 
215 config FIQ
216         bool
217 
218 config NEED_RET_TO_USER
219         bool
220 
221 config ARCH_MTD_XIP
222         bool
223 
224 config VECTORS_BASE
225         hex
226         default 0xffff0000 if MMU || CPU_HIGH_VECTOR
227         default DRAM_BASE if REMAP_VECTORS_TO_RAM
228         default 0x00000000
229         help
230           The base address of exception vectors.  This must be two pages
231           in size.
232 
233 config ARM_PATCH_PHYS_VIRT
234         bool "Patch physical to virtual translations at runtime" if EMBEDDED
235         default y
236         depends on !XIP_KERNEL && MMU
237         depends on !ARCH_REALVIEW || !SPARSEMEM
238         help
239           Patch phys-to-virt and virt-to-phys translation functions at
240           boot and module load time according to the position of the
241           kernel in system memory.
242 
243           This can only be used with non-XIP MMU kernels where the base
244           of physical memory is at a 16MB boundary.
245 
246           Only disable this option if you know that you do not require
247           this feature (eg, building a kernel for a single machine) and
248           you need to shrink the kernel to the minimal size.
249 
250 config NEED_MACH_IO_H
251         bool
252         help
253           Select this when mach/io.h is required to provide special
254           definitions for this platform.  The need for mach/io.h should
255           be avoided when possible.
256 
257 config NEED_MACH_MEMORY_H
258         bool
259         help
260           Select this when mach/memory.h is required to provide special
261           definitions for this platform.  The need for mach/memory.h should
262           be avoided when possible.
263 
264 config PHYS_OFFSET
265         hex "Physical address of main memory" if MMU
266         depends on !ARM_PATCH_PHYS_VIRT
267         default DRAM_BASE if !MMU
268         default 0x00000000 if ARCH_EBSA110 || \
269                         EP93XX_SDCE3_SYNC_PHYS_OFFSET || \
270                         ARCH_FOOTBRIDGE || \
271                         ARCH_INTEGRATOR || \
272                         ARCH_IOP13XX || \
273                         ARCH_KS8695 || \
274                         (ARCH_REALVIEW && !REALVIEW_HIGH_PHYS_OFFSET)
275         default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
276         default 0x20000000 if ARCH_S5PV210
277         default 0x70000000 if REALVIEW_HIGH_PHYS_OFFSET
278         default 0xc0000000 if EP93XX_SDCE0_PHYS_OFFSET || ARCH_SA1100
279         default 0xd0000000 if EP93XX_SDCE1_PHYS_OFFSET
280         default 0xe0000000 if EP93XX_SDCE2_PHYS_OFFSET
281         default 0xf0000000 if EP93XX_SDCE3_ASYNC_PHYS_OFFSET
282         help
283           Please provide the physical address corresponding to the
284           location of main memory in your system.
285 
286 config GENERIC_BUG
287         def_bool y
288         depends on BUG
289 
290 config PGTABLE_LEVELS
291         int
292         default 3 if ARM_LPAE
293         default 2
294 
295 source "init/Kconfig"
296 
297 source "kernel/Kconfig.freezer"
298 
299 menu "System Type"
300 
301 config MMU
302         bool "MMU-based Paged Memory Management Support"
303         default y
304         help
305           Select if you want MMU-based virtualised addressing space
306           support by paged memory management. If unsure, say 'Y'.
307 
308 #
309 # The "ARM system type" choice list is ordered alphabetically by option
310 # text.  Please add new entries in the option alphabetic order.
311 #
312 choice
313         prompt "ARM system type"
314         default ARCH_VERSATILE if !MMU
315         default ARCH_MULTIPLATFORM if MMU
316 
317 config ARCH_MULTIPLATFORM
318         bool "Allow multiple platforms to be selected"
319         depends on MMU
320         select ARCH_WANT_OPTIONAL_GPIOLIB
321         select ARM_HAS_SG_CHAIN
322         select ARM_PATCH_PHYS_VIRT
323         select AUTO_ZRELADDR
324         select CLKSRC_OF
325         select COMMON_CLK
326         select GENERIC_CLOCKEVENTS
327         select MIGHT_HAVE_PCI
328         select MULTI_IRQ_HANDLER
329         select SPARSE_IRQ
330         select USE_OF
331 
332 config ARCH_REALVIEW
333         bool "ARM Ltd. RealView family"
334         select ARCH_WANT_OPTIONAL_GPIOLIB
335         select ARM_AMBA
336         select ARM_TIMER_SP804
337         select COMMON_CLK
338         select COMMON_CLK_VERSATILE
339         select GENERIC_CLOCKEVENTS
340         select GPIO_PL061 if GPIOLIB
341         select ICST
342         select NEED_MACH_MEMORY_H
343         select PLAT_VERSATILE
344         select PLAT_VERSATILE_SCHED_CLOCK
345         help
346           This enables support for ARM Ltd RealView boards.
347 
348 config ARCH_VERSATILE
349         bool "ARM Ltd. Versatile family"
350         select ARCH_WANT_OPTIONAL_GPIOLIB
351         select ARM_AMBA
352         select ARM_TIMER_SP804
353         select ARM_VIC
354         select CLKDEV_LOOKUP
355         select GENERIC_CLOCKEVENTS
356         select HAVE_MACH_CLKDEV
357         select ICST
358         select PLAT_VERSATILE
359         select PLAT_VERSATILE_CLOCK
360         select PLAT_VERSATILE_SCHED_CLOCK
361         select VERSATILE_FPGA_IRQ
362         help
363           This enables support for ARM Ltd Versatile board.
364 
365 config ARCH_CLPS711X
366         bool "Cirrus Logic CLPS711x/EP721x/EP731x-based"
367         select ARCH_REQUIRE_GPIOLIB
368         select AUTO_ZRELADDR
369         select CLKSRC_MMIO
370         select COMMON_CLK
371         select CPU_ARM720T
372         select GENERIC_CLOCKEVENTS
373         select MFD_SYSCON
374         select SOC_BUS
375         help
376           Support for Cirrus Logic 711x/721x/731x based boards.
377 
378 config ARCH_GEMINI
379         bool "Cortina Systems Gemini"
380         select ARCH_REQUIRE_GPIOLIB
381         select CLKSRC_MMIO
382         select CPU_FA526
383         select GENERIC_CLOCKEVENTS
384         help
385           Support for the Cortina Systems Gemini family SoCs
386 
387 config ARCH_EBSA110
388         bool "EBSA-110"
389         select ARCH_USES_GETTIMEOFFSET
390         select CPU_SA110
391         select ISA
392         select NEED_MACH_IO_H
393         select NEED_MACH_MEMORY_H
394         select NO_IOPORT_MAP
395         help
396           This is an evaluation board for the StrongARM processor available
397           from Digital. It has limited hardware on-board, including an
398           Ethernet interface, two PCMCIA sockets, two serial ports and a
399           parallel port.
400 
401 config ARCH_EFM32
402         bool "Energy Micro efm32"
403         depends on !MMU
404         select ARCH_REQUIRE_GPIOLIB
405         select ARM_NVIC
406         select AUTO_ZRELADDR
407         select CLKSRC_OF
408         select COMMON_CLK
409         select CPU_V7M
410         select GENERIC_CLOCKEVENTS
411         select NO_DMA
412         select NO_IOPORT_MAP
413         select SPARSE_IRQ
414         select USE_OF
415         help
416           Support for Energy Micro's (now Silicon Labs) efm32 Giant Gecko
417           processors.
418 
419 config ARCH_EP93XX
420         bool "EP93xx-based"
421         select ARCH_HAS_HOLES_MEMORYMODEL
422         select ARCH_REQUIRE_GPIOLIB
423         select ARCH_USES_GETTIMEOFFSET
424         select ARM_AMBA
425         select ARM_VIC
426         select CLKDEV_LOOKUP
427         select CPU_ARM920T
428         help
429           This enables support for the Cirrus EP93xx series of CPUs.
430 
431 config ARCH_FOOTBRIDGE
432         bool "FootBridge"
433         select CPU_SA110
434         select FOOTBRIDGE
435         select GENERIC_CLOCKEVENTS
436         select HAVE_IDE
437         select NEED_MACH_IO_H if !MMU
438         select NEED_MACH_MEMORY_H
439         help
440           Support for systems based on the DC21285 companion chip
441           ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
442 
443 config ARCH_NETX
444         bool "Hilscher NetX based"
445         select ARM_VIC
446         select CLKSRC_MMIO
447         select CPU_ARM926T
448         select GENERIC_CLOCKEVENTS
449         help
450           This enables support for systems based on the Hilscher NetX Soc
451 
452 config ARCH_IOP13XX
453         bool "IOP13xx-based"
454         depends on MMU
455         select CPU_XSC3
456         select NEED_MACH_MEMORY_H
457         select NEED_RET_TO_USER
458         select PCI
459         select PLAT_IOP
460         select VMSPLIT_1G
461         select SPARSE_IRQ
462         help
463           Support for Intel's IOP13XX (XScale) family of processors.
464 
465 config ARCH_IOP32X
466         bool "IOP32x-based"
467         depends on MMU
468         select ARCH_REQUIRE_GPIOLIB
469         select CPU_XSCALE
470         select GPIO_IOP
471         select NEED_RET_TO_USER
472         select PCI
473         select PLAT_IOP
474         help
475           Support for Intel's 80219 and IOP32X (XScale) family of
476           processors.
477 
478 config ARCH_IOP33X
479         bool "IOP33x-based"
480         depends on MMU
481         select ARCH_REQUIRE_GPIOLIB
482         select CPU_XSCALE
483         select GPIO_IOP
484         select NEED_RET_TO_USER
485         select PCI
486         select PLAT_IOP
487         help
488           Support for Intel's IOP33X (XScale) family of processors.
489 
490 config ARCH_IXP4XX
491         bool "IXP4xx-based"
492         depends on MMU
493         select ARCH_HAS_DMA_SET_COHERENT_MASK
494         select ARCH_REQUIRE_GPIOLIB
495         select ARCH_SUPPORTS_BIG_ENDIAN
496         select CLKSRC_MMIO
497         select CPU_XSCALE
498         select DMABOUNCE if PCI
499         select GENERIC_CLOCKEVENTS
500         select MIGHT_HAVE_PCI
501         select NEED_MACH_IO_H
502         select USB_EHCI_BIG_ENDIAN_DESC
503         select USB_EHCI_BIG_ENDIAN_MMIO
504         help
505           Support for Intel's IXP4XX (XScale) family of processors.
506 
507 config ARCH_DOVE
508         bool "Marvell Dove"
509         select ARCH_REQUIRE_GPIOLIB
510         select CPU_PJ4
511         select GENERIC_CLOCKEVENTS
512         select MIGHT_HAVE_PCI
513         select MVEBU_MBUS
514         select PINCTRL
515         select PINCTRL_DOVE
516         select PLAT_ORION_LEGACY
517         help
518           Support for the Marvell Dove SoC 88AP510
519 
520 config ARCH_MV78XX0
521         bool "Marvell MV78xx0"
522         select ARCH_REQUIRE_GPIOLIB
523         select CPU_FEROCEON
524         select GENERIC_CLOCKEVENTS
525         select MVEBU_MBUS
526         select PCI
527         select PLAT_ORION_LEGACY
528         help
529           Support for the following Marvell MV78xx0 series SoCs:
530           MV781x0, MV782x0.
531 
532 config ARCH_ORION5X
533         bool "Marvell Orion"
534         depends on MMU
535         select ARCH_REQUIRE_GPIOLIB
536         select CPU_FEROCEON
537         select GENERIC_CLOCKEVENTS
538         select MVEBU_MBUS
539         select PCI
540         select PLAT_ORION_LEGACY
541         help
542           Support for the following Marvell Orion 5x series SoCs:
543           Orion-1 (5181), Orion-VoIP (5181L), Orion-NAS (5182),
544           Orion-2 (5281), Orion-1-90 (6183).
545 
546 config ARCH_MMP
547         bool "Marvell PXA168/910/MMP2"
548         depends on MMU
549         select ARCH_REQUIRE_GPIOLIB
550         select CLKDEV_LOOKUP
551         select GENERIC_ALLOCATOR
552         select GENERIC_CLOCKEVENTS
553         select GPIO_PXA
554         select IRQ_DOMAIN
555         select MULTI_IRQ_HANDLER
556         select PINCTRL
557         select PLAT_PXA
558         select SPARSE_IRQ
559         help
560           Support for Marvell's PXA168/PXA910(MMP) and MMP2 processor line.
561 
562 config ARCH_KS8695
563         bool "Micrel/Kendin KS8695"
564         select ARCH_REQUIRE_GPIOLIB
565         select CLKSRC_MMIO
566         select CPU_ARM922T
567         select GENERIC_CLOCKEVENTS
568         select NEED_MACH_MEMORY_H
569         help
570           Support for Micrel/Kendin KS8695 "Centaur" (ARM922T) based
571           System-on-Chip devices.
572 
573 config ARCH_W90X900
574         bool "Nuvoton W90X900 CPU"
575         select ARCH_REQUIRE_GPIOLIB
576         select CLKDEV_LOOKUP
577         select CLKSRC_MMIO
578         select CPU_ARM926T
579         select GENERIC_CLOCKEVENTS
580         help
581           Support for Nuvoton (Winbond logic dept.) ARM9 processor,
582           At present, the w90x900 has been renamed nuc900, regarding
583           the ARM series product line, you can login the following
584           link address to know more.
585 
586           <http://www.nuvoton.com/hq/enu/ProductAndSales/ProductLines/
587                 ConsumerElectronicsIC/ARMMicrocontroller/ARMMicrocontroller>
588 
589 config ARCH_LPC32XX
590         bool "NXP LPC32XX"
591         select ARCH_REQUIRE_GPIOLIB
592         select ARM_AMBA
593         select CLKDEV_LOOKUP
594         select CLKSRC_MMIO
595         select CPU_ARM926T
596         select GENERIC_CLOCKEVENTS
597         select HAVE_IDE
598         select USE_OF
599         help
600           Support for the NXP LPC32XX family of processors
601 
602 config ARCH_PXA
603         bool "PXA2xx/PXA3xx-based"
604         depends on MMU
605         select ARCH_MTD_XIP
606         select ARCH_REQUIRE_GPIOLIB
607         select ARM_CPU_SUSPEND if PM
608         select AUTO_ZRELADDR
609         select CLKDEV_LOOKUP
610         select CLKSRC_MMIO
611         select CLKSRC_OF
612         select GENERIC_CLOCKEVENTS
613         select GPIO_PXA
614         select HAVE_IDE
615         select IRQ_DOMAIN
616         select MULTI_IRQ_HANDLER
617         select PLAT_PXA
618         select SPARSE_IRQ
619         help
620           Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
621 
622 config ARCH_SHMOBILE_LEGACY
623         bool "Renesas ARM SoCs (non-multiplatform)"
624         select ARCH_SHMOBILE
625         select ARM_PATCH_PHYS_VIRT if MMU
626         select CLKDEV_LOOKUP
627         select CPU_V7
628         select GENERIC_CLOCKEVENTS
629         select HAVE_ARM_SCU if SMP
630         select HAVE_ARM_TWD if SMP
631         select HAVE_SMP
632         select MIGHT_HAVE_CACHE_L2X0
633         select MULTI_IRQ_HANDLER
634         select NO_IOPORT_MAP
635         select PINCTRL
636         select PM_GENERIC_DOMAINS if PM
637         select SH_CLK_CPG
638         select SPARSE_IRQ
639         help
640           Support for Renesas ARM SoC platforms using a non-multiplatform
641           kernel. This includes the SH-Mobile, R-Mobile, EMMA-Mobile, R-Car
642           and RZ families.
643 
644 config ARCH_RPC
645         bool "RiscPC"
646         select ARCH_ACORN
647         select ARCH_MAY_HAVE_PC_FDC
648         select ARCH_SPARSEMEM_ENABLE
649         select ARCH_USES_GETTIMEOFFSET
650         select CPU_SA110
651         select FIQ
652         select HAVE_IDE
653         select HAVE_PATA_PLATFORM
654         select ISA_DMA_API
655         select NEED_MACH_IO_H
656         select NEED_MACH_MEMORY_H
657         select NO_IOPORT_MAP
658         select VIRT_TO_BUS
659         help
660           On the Acorn Risc-PC, Linux can support the internal IDE disk and
661           CD-ROM interface, serial and parallel port, and the floppy drive.
662 
663 config ARCH_SA1100
664         bool "SA1100-based"
665         select ARCH_MTD_XIP
666         select ARCH_REQUIRE_GPIOLIB
667         select ARCH_SPARSEMEM_ENABLE
668         select CLKDEV_LOOKUP
669         select CLKSRC_MMIO
670         select CPU_FREQ
671         select CPU_SA1100
672         select GENERIC_CLOCKEVENTS
673         select HAVE_IDE
674         select IRQ_DOMAIN
675         select ISA
676         select MULTI_IRQ_HANDLER
677         select NEED_MACH_MEMORY_H
678         select SPARSE_IRQ
679         help
680           Support for StrongARM 11x0 based boards.
681 
682 config ARCH_S3C24XX
683         bool "Samsung S3C24XX SoCs"
684         select ARCH_REQUIRE_GPIOLIB
685         select ATAGS
686         select CLKDEV_LOOKUP
687         select CLKSRC_SAMSUNG_PWM
688         select GENERIC_CLOCKEVENTS
689         select GPIO_SAMSUNG
690         select HAVE_S3C2410_I2C if I2C
691         select HAVE_S3C2410_WATCHDOG if WATCHDOG
692         select HAVE_S3C_RTC if RTC_CLASS
693         select MULTI_IRQ_HANDLER
694         select NEED_MACH_IO_H
695         select SAMSUNG_ATAGS
696         help
697           Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
698           and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
699           (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
700           Samsung SMDK2410 development board (and derivatives).
701 
702 config ARCH_S3C64XX
703         bool "Samsung S3C64XX"
704         select ARCH_REQUIRE_GPIOLIB
705         select ARM_AMBA
706         select ARM_VIC
707         select ATAGS
708         select CLKDEV_LOOKUP
709         select CLKSRC_SAMSUNG_PWM
710         select COMMON_CLK_SAMSUNG
711         select CPU_V6K
712         select GENERIC_CLOCKEVENTS
713         select GPIO_SAMSUNG
714         select HAVE_S3C2410_I2C if I2C
715         select HAVE_S3C2410_WATCHDOG if WATCHDOG
716         select HAVE_TCM
717         select NO_IOPORT_MAP
718         select PLAT_SAMSUNG
719         select PM_GENERIC_DOMAINS if PM
720         select S3C_DEV_NAND
721         select S3C_GPIO_TRACK
722         select SAMSUNG_ATAGS
723         select SAMSUNG_WAKEMASK
724         select SAMSUNG_WDT_RESET
725         help
726           Samsung S3C64XX series based systems
727 
728 config ARCH_DAVINCI
729         bool "TI DaVinci"
730         select ARCH_HAS_HOLES_MEMORYMODEL
731         select ARCH_REQUIRE_GPIOLIB
732         select CLKDEV_LOOKUP
733         select GENERIC_ALLOCATOR
734         select GENERIC_CLOCKEVENTS
735         select GENERIC_IRQ_CHIP
736         select HAVE_IDE
737         select TI_PRIV_EDMA
738         select USE_OF
739         select ZONE_DMA
740         help
741           Support for TI's DaVinci platform.
742 
743 config ARCH_OMAP1
744         bool "TI OMAP1"
745         depends on MMU
746         select ARCH_HAS_HOLES_MEMORYMODEL
747         select ARCH_OMAP
748         select ARCH_REQUIRE_GPIOLIB
749         select CLKDEV_LOOKUP
750         select CLKSRC_MMIO
751         select GENERIC_CLOCKEVENTS
752         select GENERIC_IRQ_CHIP
753         select HAVE_IDE
754         select IRQ_DOMAIN
755         select NEED_MACH_IO_H if PCCARD
756         select NEED_MACH_MEMORY_H
757         help
758           Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
759 
760 endchoice
761 
762 menu "Multiple platform selection"
763         depends on ARCH_MULTIPLATFORM
764 
765 comment "CPU Core family selection"
766 
767 config ARCH_MULTI_V4
768         bool "ARMv4 based platforms (FA526)"
769         depends on !ARCH_MULTI_V6_V7
770         select ARCH_MULTI_V4_V5
771         select CPU_FA526
772 
773 config ARCH_MULTI_V4T
774         bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
775         depends on !ARCH_MULTI_V6_V7
776         select ARCH_MULTI_V4_V5
777         select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
778                 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
779                 CPU_ARM925T || CPU_ARM940T)
780 
781 config ARCH_MULTI_V5
782         bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
783         depends on !ARCH_MULTI_V6_V7
784         select ARCH_MULTI_V4_V5
785         select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
786                 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
787                 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
788 
789 config ARCH_MULTI_V4_V5
790         bool
791 
792 config ARCH_MULTI_V6
793         bool "ARMv6 based platforms (ARM11)"
794         select ARCH_MULTI_V6_V7
795         select CPU_V6K
796 
797 config ARCH_MULTI_V7
798         bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
799         default y
800         select ARCH_MULTI_V6_V7
801         select CPU_V7
802         select HAVE_SMP
803 
804 config ARCH_MULTI_V6_V7
805         bool
806         select MIGHT_HAVE_CACHE_L2X0
807 
808 config ARCH_MULTI_CPU_AUTO
809         def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
810         select ARCH_MULTI_V5
811 
812 endmenu
813 
814 config ARCH_VIRT
815         bool "Dummy Virtual Machine" if ARCH_MULTI_V7
816         select ARM_AMBA
817         select ARM_GIC
818         select ARM_PSCI
819         select HAVE_ARM_ARCH_TIMER
820 
821 #
822 # This is sorted alphabetically by mach-* pathname.  However, plat-*
823 # Kconfigs may be included either alphabetically (according to the
824 # plat- suffix) or along side the corresponding mach-* source.
825 #
826 source "arch/arm/mach-mvebu/Kconfig"
827 
828 source "arch/arm/mach-alpine/Kconfig"
829 
830 source "arch/arm/mach-asm9260/Kconfig"
831 
832 source "arch/arm/mach-at91/Kconfig"
833 
834 source "arch/arm/mach-axxia/Kconfig"
835 
836 source "arch/arm/mach-bcm/Kconfig"
837 
838 source "arch/arm/mach-berlin/Kconfig"
839 
840 source "arch/arm/mach-clps711x/Kconfig"
841 
842 source "arch/arm/mach-cns3xxx/Kconfig"
843 
844 source "arch/arm/mach-davinci/Kconfig"
845 
846 source "arch/arm/mach-digicolor/Kconfig"
847 
848 source "arch/arm/mach-dove/Kconfig"
849 
850 source "arch/arm/mach-ep93xx/Kconfig"
851 
852 source "arch/arm/mach-footbridge/Kconfig"
853 
854 source "arch/arm/mach-gemini/Kconfig"
855 
856 source "arch/arm/mach-highbank/Kconfig"
857 
858 source "arch/arm/mach-hisi/Kconfig"
859 
860 source "arch/arm/mach-integrator/Kconfig"
861 
862 source "arch/arm/mach-iop32x/Kconfig"
863 
864 source "arch/arm/mach-iop33x/Kconfig"
865 
866 source "arch/arm/mach-iop13xx/Kconfig"
867 
868 source "arch/arm/mach-ixp4xx/Kconfig"
869 
870 source "arch/arm/mach-keystone/Kconfig"
871 
872 source "arch/arm/mach-ks8695/Kconfig"
873 
874 source "arch/arm/mach-meson/Kconfig"
875 
876 source "arch/arm/mach-moxart/Kconfig"
877 
878 source "arch/arm/mach-mv78xx0/Kconfig"
879 
880 source "arch/arm/mach-imx/Kconfig"
881 
882 source "arch/arm/mach-mediatek/Kconfig"
883 
884 source "arch/arm/mach-mxs/Kconfig"
885 
886 source "arch/arm/mach-netx/Kconfig"
887 
888 source "arch/arm/mach-nomadik/Kconfig"
889 
890 source "arch/arm/mach-nspire/Kconfig"
891 
892 source "arch/arm/plat-omap/Kconfig"
893 
894 source "arch/arm/mach-omap1/Kconfig"
895 
896 source "arch/arm/mach-omap2/Kconfig"
897 
898 source "arch/arm/mach-orion5x/Kconfig"
899 
900 source "arch/arm/mach-picoxcell/Kconfig"
901 
902 source "arch/arm/mach-pxa/Kconfig"
903 source "arch/arm/plat-pxa/Kconfig"
904 
905 source "arch/arm/mach-mmp/Kconfig"
906 
907 source "arch/arm/mach-qcom/Kconfig"
908 
909 source "arch/arm/mach-realview/Kconfig"
910 
911 source "arch/arm/mach-rockchip/Kconfig"
912 
913 source "arch/arm/mach-sa1100/Kconfig"
914 
915 source "arch/arm/mach-socfpga/Kconfig"
916 
917 source "arch/arm/mach-spear/Kconfig"
918 
919 source "arch/arm/mach-sti/Kconfig"
920 
921 source "arch/arm/mach-s3c24xx/Kconfig"
922 
923 source "arch/arm/mach-s3c64xx/Kconfig"
924 
925 source "arch/arm/mach-s5pv210/Kconfig"
926 
927 source "arch/arm/mach-exynos/Kconfig"
928 source "arch/arm/plat-samsung/Kconfig"
929 
930 source "arch/arm/mach-shmobile/Kconfig"
931 
932 source "arch/arm/mach-sunxi/Kconfig"
933 
934 source "arch/arm/mach-prima2/Kconfig"
935 
936 source "arch/arm/mach-tegra/Kconfig"
937 
938 source "arch/arm/mach-u300/Kconfig"
939 
940 source "arch/arm/mach-ux500/Kconfig"
941 
942 source "arch/arm/mach-versatile/Kconfig"
943 
944 source "arch/arm/mach-vexpress/Kconfig"
945 source "arch/arm/plat-versatile/Kconfig"
946 
947 source "arch/arm/mach-vt8500/Kconfig"
948 
949 source "arch/arm/mach-w90x900/Kconfig"
950 
951 source "arch/arm/mach-zynq/Kconfig"
952 
953 # Definitions to make life easier
954 config ARCH_ACORN
955         bool
956 
957 config PLAT_IOP
958         bool
959         select GENERIC_CLOCKEVENTS
960 
961 config PLAT_ORION
962         bool
963         select CLKSRC_MMIO
964         select COMMON_CLK
965         select GENERIC_IRQ_CHIP
966         select IRQ_DOMAIN
967 
968 config PLAT_ORION_LEGACY
969         bool
970         select PLAT_ORION
971 
972 config PLAT_PXA
973         bool
974 
975 config PLAT_VERSATILE
976         bool
977 
978 config ARM_TIMER_SP804
979         bool
980         select CLKSRC_MMIO
981         select CLKSRC_OF if OF
982 
983 source "arch/arm/firmware/Kconfig"
984 
985 source arch/arm/mm/Kconfig
986 
987 config IWMMXT
988         bool "Enable iWMMXt support"
989         depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
990         default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
991         help
992           Enable support for iWMMXt context switching at run time if
993           running on a CPU that supports it.
994 
995 config MULTI_IRQ_HANDLER
996         bool
997         help
998           Allow each machine to specify it's own IRQ handler at run time.
999 
1000 if !MMU
1001 source "arch/arm/Kconfig-nommu"
1002 endif
1003 
1004 config PJ4B_ERRATA_4742
1005         bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
1006         depends on CPU_PJ4B && MACH_ARMADA_370
1007         default y
1008         help
1009           When coming out of either a Wait for Interrupt (WFI) or a Wait for
1010           Event (WFE) IDLE states, a specific timing sensitivity exists between
1011           the retiring WFI/WFE instructions and the newly issued subsequent
1012           instructions.  This sensitivity can result in a CPU hang scenario.
1013           Workaround:
1014           The software must insert either a Data Synchronization Barrier (DSB)
1015           or Data Memory Barrier (DMB) command immediately after the WFI/WFE
1016           instruction
1017 
1018 config ARM_ERRATA_326103
1019         bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
1020         depends on CPU_V6
1021         help
1022           Executing a SWP instruction to read-only memory does not set bit 11
1023           of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
1024           treat the access as a read, preventing a COW from occurring and
1025           causing the faulting task to livelock.
1026 
1027 config ARM_ERRATA_411920
1028         bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
1029         depends on CPU_V6 || CPU_V6K
1030         help
1031           Invalidation of the Instruction Cache operation can
1032           fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
1033           It does not affect the MPCore. This option enables the ARM Ltd.
1034           recommended workaround.
1035 
1036 config ARM_ERRATA_430973
1037         bool "ARM errata: Stale prediction on replaced interworking branch"
1038         depends on CPU_V7
1039         help
1040           This option enables the workaround for the 430973 Cortex-A8
1041           r1p* erratum. If a code sequence containing an ARM/Thumb
1042           interworking branch is replaced with another code sequence at the
1043           same virtual address, whether due to self-modifying code or virtual
1044           to physical address re-mapping, Cortex-A8 does not recover from the
1045           stale interworking branch prediction. This results in Cortex-A8
1046           executing the new code sequence in the incorrect ARM or Thumb state.
1047           The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
1048           and also flushes the branch target cache at every context switch.
1049           Note that setting specific bits in the ACTLR register may not be
1050           available in non-secure mode.
1051 
1052 config ARM_ERRATA_458693
1053         bool "ARM errata: Processor deadlock when a false hazard is created"
1054         depends on CPU_V7
1055         depends on !ARCH_MULTIPLATFORM
1056         help
1057           This option enables the workaround for the 458693 Cortex-A8 (r2p0)
1058           erratum. For very specific sequences of memory operations, it is
1059           possible for a hazard condition intended for a cache line to instead
1060           be incorrectly associated with a different cache line. This false
1061           hazard might then cause a processor deadlock. The workaround enables
1062           the L1 caching of the NEON accesses and disables the PLD instruction
1063           in the ACTLR register. Note that setting specific bits in the ACTLR
1064           register may not be available in non-secure mode.
1065 
1066 config ARM_ERRATA_460075
1067         bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
1068         depends on CPU_V7
1069         depends on !ARCH_MULTIPLATFORM
1070         help
1071           This option enables the workaround for the 460075 Cortex-A8 (r2p0)
1072           erratum. Any asynchronous access to the L2 cache may encounter a
1073           situation in which recent store transactions to the L2 cache are lost
1074           and overwritten with stale memory contents from external memory. The
1075           workaround disables the write-allocate mode for the L2 cache via the
1076           ACTLR register. Note that setting specific bits in the ACTLR register
1077           may not be available in non-secure mode.
1078 
1079 config ARM_ERRATA_742230
1080         bool "ARM errata: DMB operation may be faulty"
1081         depends on CPU_V7 && SMP
1082         depends on !ARCH_MULTIPLATFORM
1083         help
1084           This option enables the workaround for the 742230 Cortex-A9
1085           (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
1086           between two write operations may not ensure the correct visibility
1087           ordering of the two writes. This workaround sets a specific bit in
1088           the diagnostic register of the Cortex-A9 which causes the DMB
1089           instruction to behave as a DSB, ensuring the correct behaviour of
1090           the two writes.
1091 
1092 config ARM_ERRATA_742231
1093         bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
1094         depends on CPU_V7 && SMP
1095         depends on !ARCH_MULTIPLATFORM
1096         help
1097           This option enables the workaround for the 742231 Cortex-A9
1098           (r2p0..r2p2) erratum. Under certain conditions, specific to the
1099           Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
1100           accessing some data located in the same cache line, may get corrupted
1101           data due to bad handling of the address hazard when the line gets
1102           replaced from one of the CPUs at the same time as another CPU is
1103           accessing it. This workaround sets specific bits in the diagnostic
1104           register of the Cortex-A9 which reduces the linefill issuing
1105           capabilities of the processor.
1106 
1107 config ARM_ERRATA_643719
1108         bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
1109         depends on CPU_V7 && SMP
1110         default y
1111         help
1112           This option enables the workaround for the 643719 Cortex-A9 (prior to
1113           r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
1114           register returns zero when it should return one. The workaround
1115           corrects this value, ensuring cache maintenance operations which use
1116           it behave as intended and avoiding data corruption.
1117 
1118 config ARM_ERRATA_720789
1119         bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
1120         depends on CPU_V7
1121         help
1122           This option enables the workaround for the 720789 Cortex-A9 (prior to
1123           r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
1124           broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
1125           As a consequence of this erratum, some TLB entries which should be
1126           invalidated are not, resulting in an incoherency in the system page
1127           tables. The workaround changes the TLB flushing routines to invalidate
1128           entries regardless of the ASID.
1129 
1130 config ARM_ERRATA_743622
1131         bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
1132         depends on CPU_V7
1133         depends on !ARCH_MULTIPLATFORM
1134         help
1135           This option enables the workaround for the 743622 Cortex-A9
1136           (r2p*) erratum. Under very rare conditions, a faulty
1137           optimisation in the Cortex-A9 Store Buffer may lead to data
1138           corruption. This workaround sets a specific bit in the diagnostic
1139           register of the Cortex-A9 which disables the Store Buffer
1140           optimisation, preventing the defect from occurring. This has no
1141           visible impact on the overall performance or power consumption of the
1142           processor.
1143 
1144 config ARM_ERRATA_751472
1145         bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
1146         depends on CPU_V7
1147         depends on !ARCH_MULTIPLATFORM
1148         help
1149           This option enables the workaround for the 751472 Cortex-A9 (prior
1150           to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
1151           completion of a following broadcasted operation if the second
1152           operation is received by a CPU before the ICIALLUIS has completed,
1153           potentially leading to corrupted entries in the cache or TLB.
1154 
1155 config ARM_ERRATA_754322
1156         bool "ARM errata: possible faulty MMU translations following an ASID switch"
1157         depends on CPU_V7
1158         help
1159           This option enables the workaround for the 754322 Cortex-A9 (r2p*,
1160           r3p*) erratum. A speculative memory access may cause a page table walk
1161           which starts prior to an ASID switch but completes afterwards. This
1162           can populate the micro-TLB with a stale entry which may be hit with
1163           the new ASID. This workaround places two dsb instructions in the mm
1164           switching code so that no page table walks can cross the ASID switch.
1165 
1166 config ARM_ERRATA_754327
1167         bool "ARM errata: no automatic Store Buffer drain"
1168         depends on CPU_V7 && SMP
1169         help
1170           This option enables the workaround for the 754327 Cortex-A9 (prior to
1171           r2p0) erratum. The Store Buffer does not have any automatic draining
1172           mechanism and therefore a livelock may occur if an external agent
1173           continuously polls a memory location waiting to observe an update.
1174           This workaround defines cpu_relax() as smp_mb(), preventing correctly
1175           written polling loops from denying visibility of updates to memory.
1176 
1177 config ARM_ERRATA_364296
1178         bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
1179         depends on CPU_V6
1180         help
1181           This options enables the workaround for the 364296 ARM1136
1182           r0p2 erratum (possible cache data corruption with
1183           hit-under-miss enabled). It sets the undocumented bit 31 in
1184           the auxiliary control register and the FI bit in the control
1185           register, thus disabling hit-under-miss without putting the
1186           processor into full low interrupt latency mode. ARM11MPCore
1187           is not affected.
1188 
1189 config ARM_ERRATA_764369
1190         bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
1191         depends on CPU_V7 && SMP
1192         help
1193           This option enables the workaround for erratum 764369
1194           affecting Cortex-A9 MPCore with two or more processors (all
1195           current revisions). Under certain timing circumstances, a data
1196           cache line maintenance operation by MVA targeting an Inner
1197           Shareable memory region may fail to proceed up to either the
1198           Point of Coherency or to the Point of Unification of the
1199           system. This workaround adds a DSB instruction before the
1200           relevant cache maintenance functions and sets a specific bit
1201           in the diagnostic control register of the SCU.
1202 
1203 config ARM_ERRATA_775420
1204        bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
1205        depends on CPU_V7
1206        help
1207          This option enables the workaround for the 775420 Cortex-A9 (r2p2,
1208          r2p6,r2p8,r2p10,r3p0) erratum. In case a date cache maintenance
1209          operation aborts with MMU exception, it might cause the processor
1210          to deadlock. This workaround puts DSB before executing ISB if
1211          an abort may occur on cache maintenance.
1212 
1213 config ARM_ERRATA_798181
1214         bool "ARM errata: TLBI/DSB failure on Cortex-A15"
1215         depends on CPU_V7 && SMP
1216         help
1217           On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
1218           adequately shooting down all use of the old entries. This
1219           option enables the Linux kernel workaround for this erratum
1220           which sends an IPI to the CPUs that are running the same ASID
1221           as the one being invalidated.
1222 
1223 config ARM_ERRATA_773022
1224         bool "ARM errata: incorrect instructions may be executed from loop buffer"
1225         depends on CPU_V7
1226         help
1227           This option enables the workaround for the 773022 Cortex-A15
1228           (up to r0p4) erratum. In certain rare sequences of code, the
1229           loop buffer may deliver incorrect instructions. This
1230           workaround disables the loop buffer to avoid the erratum.
1231 
1232 endmenu
1233 
1234 source "arch/arm/common/Kconfig"
1235 
1236 menu "Bus support"
1237 
1238 config ISA
1239         bool
1240         help
1241           Find out whether you have ISA slots on your motherboard.  ISA is the
1242           name of a bus system, i.e. the way the CPU talks to the other stuff
1243           inside your box.  Other bus systems are PCI, EISA, MicroChannel
1244           (MCA) or VESA.  ISA is an older system, now being displaced by PCI;
1245           newer boards don't support it.  If you have ISA, say Y, otherwise N.
1246 
1247 # Select ISA DMA controller support
1248 config ISA_DMA
1249         bool
1250         select ISA_DMA_API
1251 
1252 # Select ISA DMA interface
1253 config ISA_DMA_API
1254         bool
1255 
1256 config PCI
1257         bool "PCI support" if MIGHT_HAVE_PCI
1258         help
1259           Find out whether you have a PCI motherboard. PCI is the name of a
1260           bus system, i.e. the way the CPU talks to the other stuff inside
1261           your box. Other bus systems are ISA, EISA, MicroChannel (MCA) or
1262           VESA. If you have PCI, say Y, otherwise N.
1263 
1264 config PCI_DOMAINS
1265         bool
1266         depends on PCI
1267 
1268 config PCI_DOMAINS_GENERIC
1269         def_bool PCI_DOMAINS
1270 
1271 config PCI_NANOENGINE
1272         bool "BSE nanoEngine PCI support"
1273         depends on SA1100_NANOENGINE
1274         help
1275           Enable PCI on the BSE nanoEngine board.
1276 
1277 config PCI_SYSCALL
1278         def_bool PCI
1279 
1280 config PCI_HOST_ITE8152
1281         bool
1282         depends on PCI && MACH_ARMCORE
1283         default y
1284         select DMABOUNCE
1285 
1286 source "drivers/pci/Kconfig"
1287 source "drivers/pci/pcie/Kconfig"
1288 
1289 source "drivers/pcmcia/Kconfig"
1290 
1291 endmenu
1292 
1293 menu "Kernel Features"
1294 
1295 config HAVE_SMP
1296         bool
1297         help
1298           This option should be selected by machines which have an SMP-
1299           capable CPU.
1300 
1301           The only effect of this option is to make the SMP-related
1302           options available to the user for configuration.
1303 
1304 config SMP
1305         bool "Symmetric Multi-Processing"
1306         depends on CPU_V6K || CPU_V7
1307         depends on GENERIC_CLOCKEVENTS
1308         depends on HAVE_SMP
1309         depends on MMU || ARM_MPU
1310         help
1311           This enables support for systems with more than one CPU. If you have
1312           a system with only one CPU, say N. If you have a system with more
1313           than one CPU, say Y.
1314 
1315           If you say N here, the kernel will run on uni- and multiprocessor
1316           machines, but will use only one CPU of a multiprocessor machine. If
1317           you say Y here, the kernel will run on many, but not all,
1318           uniprocessor machines. On a uniprocessor machine, the kernel
1319           will run faster if you say N here.
1320 
1321           See also <file:Documentation/x86/i386/IO-APIC.txt>,
1322           <file:Documentation/nmi_watchdog.txt> and the SMP-HOWTO available at
1323           <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1324 
1325           If you don't know what to do here, say N.
1326 
1327 config SMP_ON_UP
1328         bool "Allow booting SMP kernel on uniprocessor systems"
1329         depends on SMP && !XIP_KERNEL && MMU
1330         default y
1331         help
1332           SMP kernels contain instructions which fail on non-SMP processors.
1333           Enabling this option allows the kernel to modify itself to make
1334           these instructions safe.  Disabling it allows about 1K of space
1335           savings.
1336 
1337           If you don't know what to do here, say Y.
1338 
1339 config ARM_CPU_TOPOLOGY
1340         bool "Support cpu topology definition"
1341         depends on SMP && CPU_V7
1342         default y
1343         help
1344           Support ARM cpu topology definition. The MPIDR register defines
1345           affinity between processors which is then used to describe the cpu
1346           topology of an ARM System.
1347 
1348 config SCHED_MC
1349         bool "Multi-core scheduler support"
1350         depends on ARM_CPU_TOPOLOGY
1351         help
1352           Multi-core scheduler support improves the CPU scheduler's decision
1353           making when dealing with multi-core CPU chips at a cost of slightly
1354           increased overhead in some places. If unsure say N here.
1355 
1356 config SCHED_SMT
1357         bool "SMT scheduler support"
1358         depends on ARM_CPU_TOPOLOGY
1359         help
1360           Improves the CPU scheduler's decision making when dealing with
1361           MultiThreading at a cost of slightly increased overhead in some
1362           places. If unsure say N here.
1363 
1364 config HAVE_ARM_SCU
1365         bool
1366         help
1367           This option enables support for the ARM system coherency unit
1368 
1369 config HAVE_ARM_ARCH_TIMER
1370         bool "Architected timer support"
1371         depends on CPU_V7
1372         select ARM_ARCH_TIMER
1373         select GENERIC_CLOCKEVENTS
1374         help
1375           This option enables support for the ARM architected timer
1376 
1377 config HAVE_ARM_TWD
1378         bool
1379         depends on SMP
1380         select CLKSRC_OF if OF
1381         help
1382           This options enables support for the ARM timer and watchdog unit
1383 
1384 config MCPM
1385         bool "Multi-Cluster Power Management"
1386         depends on CPU_V7 && SMP
1387         help
1388           This option provides the common power management infrastructure
1389           for (multi-)cluster based systems, such as big.LITTLE based
1390           systems.
1391 
1392 config MCPM_QUAD_CLUSTER
1393         bool
1394         depends on MCPM
1395         help
1396           To avoid wasting resources unnecessarily, MCPM only supports up
1397           to 2 clusters by default.
1398           Platforms with 3 or 4 clusters that use MCPM must select this
1399           option to allow the additional clusters to be managed.
1400 
1401 config BIG_LITTLE
1402         bool "big.LITTLE support (Experimental)"
1403         depends on CPU_V7 && SMP
1404         select MCPM
1405         help
1406           This option enables support selections for the big.LITTLE
1407           system architecture.
1408 
1409 config BL_SWITCHER
1410         bool "big.LITTLE switcher support"
1411         depends on BIG_LITTLE && MCPM && HOTPLUG_CPU
1412         select ARM_CPU_SUSPEND
1413         select CPU_PM
1414         help
1415           The big.LITTLE "switcher" provides the core functionality to
1416           transparently handle transition between a cluster of A15's
1417           and a cluster of A7's in a big.LITTLE system.
1418 
1419 config BL_SWITCHER_DUMMY_IF
1420         tristate "Simple big.LITTLE switcher user interface"
1421         depends on BL_SWITCHER && DEBUG_KERNEL
1422         help
1423           This is a simple and dummy char dev interface to control
1424           the big.LITTLE switcher core code.  It is meant for
1425           debugging purposes only.
1426 
1427 choice
1428         prompt "Memory split"
1429         depends on MMU
1430         default VMSPLIT_3G
1431         help
1432           Select the desired split between kernel and user memory.
1433 
1434           If you are not absolutely sure what you are doing, leave this
1435           option alone!
1436 
1437         config VMSPLIT_3G
1438                 bool "3G/1G user/kernel split"
1439         config VMSPLIT_2G
1440                 bool "2G/2G user/kernel split"
1441         config VMSPLIT_1G
1442                 bool "1G/3G user/kernel split"
1443 endchoice
1444 
1445 config PAGE_OFFSET
1446         hex
1447         default PHYS_OFFSET if !MMU
1448         default 0x40000000 if VMSPLIT_1G
1449         default 0x80000000 if VMSPLIT_2G
1450         default 0xC0000000
1451 
1452 config NR_CPUS
1453         int "Maximum number of CPUs (2-32)"
1454         range 2 32
1455         depends on SMP
1456         default "4"
1457 
1458 config HOTPLUG_CPU
1459         bool "Support for hot-pluggable CPUs"
1460         depends on SMP
1461         help
1462           Say Y here to experiment with turning CPUs off and on.  CPUs
1463           can be controlled through /sys/devices/system/cpu.
1464 
1465 config ARM_PSCI
1466         bool "Support for the ARM Power State Coordination Interface (PSCI)"
1467         depends on CPU_V7
1468         help
1469           Say Y here if you want Linux to communicate with system firmware
1470           implementing the PSCI specification for CPU-centric power
1471           management operations described in ARM document number ARM DEN
1472           0022A ("Power State Coordination Interface System Software on
1473           ARM processors").
1474 
1475 # The GPIO number here must be sorted by descending number. In case of
1476 # a multiplatform kernel, we just want the highest value required by the
1477 # selected platforms.
1478 config ARCH_NR_GPIO
1479         int
1480         default 1024 if ARCH_SHMOBILE || ARCH_TEGRA || ARCH_ZYNQ
1481         default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1482                 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1483         default 416 if ARCH_SUNXI
1484         default 392 if ARCH_U8500
1485         default 352 if ARCH_VT8500
1486         default 288 if ARCH_ROCKCHIP
1487         default 264 if MACH_H4700
1488         default 0
1489         help
1490           Maximum number of GPIOs in the system.
1491 
1492           If unsure, leave the default value.
1493 
1494 source kernel/Kconfig.preempt
1495 
1496 config HZ_FIXED
1497         int
1498         default 200 if ARCH_EBSA110 || ARCH_S3C24XX || \
1499                 ARCH_S5PV210 || ARCH_EXYNOS4
1500         default 128 if SOC_AT91RM9200
1501         default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE_LEGACY
1502         default 0
1503 
1504 choice
1505         depends on HZ_FIXED = 0
1506         prompt "Timer frequency"
1507 
1508 config HZ_100
1509         bool "100 Hz"
1510 
1511 config HZ_200
1512         bool "200 Hz"
1513 
1514 config HZ_250
1515         bool "250 Hz"
1516 
1517 config HZ_300
1518         bool "300 Hz"
1519 
1520 config HZ_500
1521         bool "500 Hz"
1522 
1523 config HZ_1000
1524         bool "1000 Hz"
1525 
1526 endchoice
1527 
1528 config HZ
1529         int
1530         default HZ_FIXED if HZ_FIXED != 0
1531         default 100 if HZ_100
1532         default 200 if HZ_200
1533         default 250 if HZ_250
1534         default 300 if HZ_300
1535         default 500 if HZ_500
1536         default 1000
1537 
1538 config SCHED_HRTICK
1539         def_bool HIGH_RES_TIMERS
1540 
1541 config THUMB2_KERNEL
1542         bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1543         depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1544         default y if CPU_THUMBONLY
1545         select AEABI
1546         select ARM_ASM_UNIFIED
1547         select ARM_UNWIND
1548         help
1549           By enabling this option, the kernel will be compiled in
1550           Thumb-2 mode. A compiler/assembler that understand the unified
1551           ARM-Thumb syntax is needed.
1552 
1553           If unsure, say N.
1554 
1555 config THUMB2_AVOID_R_ARM_THM_JUMP11
1556         bool "Work around buggy Thumb-2 short branch relocations in gas"
1557         depends on THUMB2_KERNEL && MODULES
1558         default y
1559         help
1560           Various binutils versions can resolve Thumb-2 branches to
1561           locally-defined, preemptible global symbols as short-range "b.n"
1562           branch instructions.
1563 
1564           This is a problem, because there's no guarantee the final
1565           destination of the symbol, or any candidate locations for a
1566           trampoline, are within range of the branch.  For this reason, the
1567           kernel does not support fixing up the R_ARM_THM_JUMP11 (102)
1568           relocation in modules at all, and it makes little sense to add
1569           support.
1570 
1571           The symptom is that the kernel fails with an "unsupported
1572           relocation" error when loading some modules.
1573 
1574           Until fixed tools are available, passing
1575           -fno-optimize-sibling-calls to gcc should prevent gcc generating
1576           code which hits this problem, at the cost of a bit of extra runtime
1577           stack usage in some cases.
1578 
1579           The problem is described in more detail at:
1580               https://bugs.launchpad.net/binutils-linaro/+bug/725126
1581 
1582           Only Thumb-2 kernels are affected.
1583 
1584           Unless you are sure your tools don't have this problem, say Y.
1585 
1586 config ARM_ASM_UNIFIED
1587         bool
1588 
1589 config AEABI
1590         bool "Use the ARM EABI to compile the kernel"
1591         help
1592           This option allows for the kernel to be compiled using the latest
1593           ARM ABI (aka EABI).  This is only useful if you are using a user
1594           space environment that is also compiled with EABI.
1595 
1596           Since there are major incompatibilities between the legacy ABI and
1597           EABI, especially with regard to structure member alignment, this
1598           option also changes the kernel syscall calling convention to
1599           disambiguate both ABIs and allow for backward compatibility support
1600           (selected with CONFIG_OABI_COMPAT).
1601 
1602           To use this you need GCC version 4.0.0 or later.
1603 
1604 config OABI_COMPAT
1605         bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1606         depends on AEABI && !THUMB2_KERNEL
1607         help
1608           This option preserves the old syscall interface along with the
1609           new (ARM EABI) one. It also provides a compatibility layer to
1610           intercept syscalls that have structure arguments which layout
1611           in memory differs between the legacy ABI and the new ARM EABI
1612           (only for non "thumb" binaries). This option adds a tiny
1613           overhead to all syscalls and produces a slightly larger kernel.
1614 
1615           The seccomp filter system will not be available when this is
1616           selected, since there is no way yet to sensibly distinguish
1617           between calling conventions during filtering.
1618 
1619           If you know you'll be using only pure EABI user space then you
1620           can say N here. If this option is not selected and you attempt
1621           to execute a legacy ABI binary then the result will be
1622           UNPREDICTABLE (in fact it can be predicted that it won't work
1623           at all). If in doubt say N.
1624 
1625 config ARCH_HAS_HOLES_MEMORYMODEL
1626         bool
1627 
1628 config ARCH_SPARSEMEM_ENABLE
1629         bool
1630 
1631 config ARCH_SPARSEMEM_DEFAULT
1632         def_bool ARCH_SPARSEMEM_ENABLE
1633 
1634 config ARCH_SELECT_MEMORY_MODEL
1635         def_bool ARCH_SPARSEMEM_ENABLE
1636 
1637 config HAVE_ARCH_PFN_VALID
1638         def_bool ARCH_HAS_HOLES_MEMORYMODEL || !SPARSEMEM
1639 
1640 config HAVE_GENERIC_RCU_GUP
1641         def_bool y
1642         depends on ARM_LPAE
1643 
1644 config HIGHMEM
1645         bool "High Memory Support"
1646         depends on MMU
1647         help
1648           The address space of ARM processors is only 4 Gigabytes large
1649           and it has to accommodate user address space, kernel address
1650           space as well as some memory mapped IO. That means that, if you
1651           have a large amount of physical memory and/or IO, not all of the
1652           memory can be "permanently mapped" by the kernel. The physical
1653           memory that is not permanently mapped is called "high memory".
1654 
1655           Depending on the selected kernel/user memory split, minimum
1656           vmalloc space and actual amount of RAM, you may not need this
1657           option which should result in a slightly faster kernel.
1658 
1659           If unsure, say n.
1660 
1661 config HIGHPTE
1662         bool "Allocate 2nd-level pagetables from highmem"
1663         depends on HIGHMEM
1664 
1665 config HW_PERF_EVENTS
1666         bool "Enable hardware performance counter support for perf events"
1667         depends on PERF_EVENTS
1668         default y
1669         help
1670           Enable hardware performance counter support for perf events. If
1671           disabled, perf events will use software events only.
1672 
1673 config SYS_SUPPORTS_HUGETLBFS
1674        def_bool y
1675        depends on ARM_LPAE
1676 
1677 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
1678        def_bool y
1679        depends on ARM_LPAE
1680 
1681 config ARCH_WANT_GENERAL_HUGETLB
1682         def_bool y
1683 
1684 source "mm/Kconfig"
1685 
1686 config FORCE_MAX_ZONEORDER
1687         int "Maximum zone order" if ARCH_SHMOBILE_LEGACY
1688         range 11 64 if ARCH_SHMOBILE_LEGACY
1689         default "12" if SOC_AM33XX
1690         default "9" if SA1111 || ARCH_EFM32
1691         default "11"
1692         help
1693           The kernel memory allocator divides physically contiguous memory
1694           blocks into "zones", where each zone is a power of two number of
1695           pages.  This option selects the largest power of two that the kernel
1696           keeps in the memory allocator.  If you need to allocate very large
1697           blocks of physically contiguous memory, then you may need to
1698           increase this value.
1699 
1700           This config option is actually maximum order plus one. For example,
1701           a value of 11 means that the largest free memory block is 2^10 pages.
1702 
1703 config ALIGNMENT_TRAP
1704         bool
1705         depends on CPU_CP15_MMU
1706         default y if !ARCH_EBSA110
1707         select HAVE_PROC_CPU if PROC_FS
1708         help
1709           ARM processors cannot fetch/store information which is not
1710           naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1711           address divisible by 4. On 32-bit ARM processors, these non-aligned
1712           fetch/store instructions will be emulated in software if you say
1713           here, which has a severe performance impact. This is necessary for
1714           correct operation of some network protocols. With an IP-only
1715           configuration it is safe to say N, otherwise say Y.
1716 
1717 config UACCESS_WITH_MEMCPY
1718         bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1719         depends on MMU
1720         default y if CPU_FEROCEON
1721         help
1722           Implement faster copy_to_user and clear_user methods for CPU
1723           cores where a 8-word STM instruction give significantly higher
1724           memory write throughput than a sequence of individual 32bit stores.
1725 
1726           A possible side effect is a slight increase in scheduling latency
1727           between threads sharing the same address space if they invoke
1728           such copy operations with large buffers.
1729 
1730           However, if the CPU data cache is using a write-allocate mode,
1731           this option is unlikely to provide any performance gain.
1732 
1733 config SECCOMP
1734         bool
1735         prompt "Enable seccomp to safely compute untrusted bytecode"
1736         ---help---
1737           This kernel feature is useful for number crunching applications
1738           that may need to compute untrusted bytecode during their
1739           execution. By using pipes or other transports made available to
1740           the process as file descriptors supporting the read/write
1741           syscalls, it's possible to isolate those applications in
1742           their own address space using seccomp. Once seccomp is
1743           enabled via prctl(PR_SET_SECCOMP), it cannot be disabled
1744           and the task is only allowed to execute a few safe syscalls
1745           defined by each seccomp mode.
1746 
1747 config SWIOTLB
1748         def_bool y
1749 
1750 config IOMMU_HELPER
1751         def_bool SWIOTLB
1752 
1753 config XEN_DOM0
1754         def_bool y
1755         depends on XEN
1756 
1757 config XEN
1758         bool "Xen guest support on ARM"
1759         depends on ARM && AEABI && OF
1760         depends on CPU_V7 && !CPU_V6
1761         depends on !GENERIC_ATOMIC64
1762         depends on MMU
1763         select ARCH_DMA_ADDR_T_64BIT
1764         select ARM_PSCI
1765         select SWIOTLB_XEN
1766         help
1767           Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1768 
1769 endmenu
1770 
1771 menu "Boot options"
1772 
1773 config USE_OF
1774         bool "Flattened Device Tree support"
1775         select IRQ_DOMAIN
1776         select OF
1777         select OF_EARLY_FLATTREE
1778         select OF_RESERVED_MEM
1779         help
1780           Include support for flattened device tree machine descriptions.
1781 
1782 config ATAGS
1783         bool "Support for the traditional ATAGS boot data passing" if USE_OF
1784         default y
1785         help
1786           This is the traditional way of passing data to the kernel at boot
1787           time. If you are solely relying on the flattened device tree (or
1788           the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1789           to remove ATAGS support from your kernel binary.  If unsure,
1790           leave this to y.
1791 
1792 config DEPRECATED_PARAM_STRUCT
1793         bool "Provide old way to pass kernel parameters"
1794         depends on ATAGS
1795         help
1796           This was deprecated in 2001 and announced to live on for 5 years.
1797           Some old boot loaders still use this way.
1798 
1799 # Compressed boot loader in ROM.  Yes, we really want to ask about
1800 # TEXT and BSS so we preserve their values in the config files.
1801 config ZBOOT_ROM_TEXT
1802         hex "Compressed ROM boot loader base address"
1803         default "0"
1804         help
1805           The physical address at which the ROM-able zImage is to be
1806           placed in the target.  Platforms which normally make use of
1807           ROM-able zImage formats normally set this to a suitable
1808           value in their defconfig file.
1809 
1810           If ZBOOT_ROM is not enabled, this has no effect.
1811 
1812 config ZBOOT_ROM_BSS
1813         hex "Compressed ROM boot loader BSS address"
1814         default "0"
1815         help
1816           The base address of an area of read/write memory in the target
1817           for the ROM-able zImage which must be available while the
1818           decompressor is running. It must be large enough to hold the
1819           entire decompressed kernel plus an additional 128 KiB.
1820           Platforms which normally make use of ROM-able zImage formats
1821           normally set this to a suitable value in their defconfig file.
1822 
1823           If ZBOOT_ROM is not enabled, this has no effect.
1824 
1825 config ZBOOT_ROM
1826         bool "Compressed boot loader in ROM/flash"
1827         depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1828         depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1829         help
1830           Say Y here if you intend to execute your compressed kernel image
1831           (zImage) directly from ROM or flash.  If unsure, say N.
1832 
1833 config ARM_APPENDED_DTB
1834         bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1835         depends on OF
1836         help
1837           With this option, the boot code will look for a device tree binary
1838           (DTB) appended to zImage
1839           (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1840 
1841           This is meant as a backward compatibility convenience for those
1842           systems with a bootloader that can't be upgraded to accommodate
1843           the documented boot protocol using a device tree.
1844 
1845           Beware that there is very little in terms of protection against
1846           this option being confused by leftover garbage in memory that might
1847           look like a DTB header after a reboot if no actual DTB is appended
1848           to zImage.  Do not leave this option active in a production kernel
1849           if you don't intend to always append a DTB.  Proper passing of the
1850           location into r2 of a bootloader provided DTB is always preferable
1851           to this option.
1852 
1853 config ARM_ATAG_DTB_COMPAT
1854         bool "Supplement the appended DTB with traditional ATAG information"
1855         depends on ARM_APPENDED_DTB
1856         help
1857           Some old bootloaders can't be updated to a DTB capable one, yet
1858           they provide ATAGs with memory configuration, the ramdisk address,
1859           the kernel cmdline string, etc.  Such information is dynamically
1860           provided by the bootloader and can't always be stored in a static
1861           DTB.  To allow a device tree enabled kernel to be used with such
1862           bootloaders, this option allows zImage to extract the information
1863           from the ATAG list and store it at run time into the appended DTB.
1864 
1865 choice
1866         prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1867         default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1868 
1869 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1870         bool "Use bootloader kernel arguments if available"
1871         help
1872           Uses the command-line options passed by the boot loader instead of
1873           the device tree bootargs property. If the boot loader doesn't provide
1874           any, the device tree bootargs property will be used.
1875 
1876 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1877         bool "Extend with bootloader kernel arguments"
1878         help
1879           The command-line arguments provided by the boot loader will be
1880           appended to the the device tree bootargs property.
1881 
1882 endchoice
1883 
1884 config CMDLINE
1885         string "Default kernel command string"
1886         default ""
1887         help
1888           On some architectures (EBSA110 and CATS), there is currently no way
1889           for the boot loader to pass arguments to the kernel. For these
1890           architectures, you should supply some command-line options at build
1891           time by entering them here. As a minimum, you should specify the
1892           memory size and the root device (e.g., mem=64M root=/dev/nfs).
1893 
1894 choice
1895         prompt "Kernel command line type" if CMDLINE != ""
1896         default CMDLINE_FROM_BOOTLOADER
1897         depends on ATAGS
1898 
1899 config CMDLINE_FROM_BOOTLOADER
1900         bool "Use bootloader kernel arguments if available"
1901         help
1902           Uses the command-line options passed by the boot loader. If
1903           the boot loader doesn't provide any, the default kernel command
1904           string provided in CMDLINE will be used.
1905 
1906 config CMDLINE_EXTEND
1907         bool "Extend bootloader kernel arguments"
1908         help
1909           The command-line arguments provided by the boot loader will be
1910           appended to the default kernel command string.
1911 
1912 config CMDLINE_FORCE
1913         bool "Always use the default kernel command string"
1914         help
1915           Always use the default kernel command string, even if the boot
1916           loader passes other arguments to the kernel.
1917           This is useful if you cannot or don't want to change the
1918           command-line options your boot loader passes to the kernel.
1919 endchoice
1920 
1921 config XIP_KERNEL
1922         bool "Kernel Execute-In-Place from ROM"
1923         depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1924         help
1925           Execute-In-Place allows the kernel to run from non-volatile storage
1926           directly addressable by the CPU, such as NOR flash. This saves RAM
1927           space since the text section of the kernel is not loaded from flash
1928           to RAM.  Read-write sections, such as the data section and stack,
1929           are still copied to RAM.  The XIP kernel is not compressed since
1930           it has to run directly from flash, so it will take more space to
1931           store it.  The flash address used to link the kernel object files,
1932           and for storing it, is configuration dependent. Therefore, if you
1933           say Y here, you must know the proper physical address where to
1934           store the kernel image depending on your own flash memory usage.
1935 
1936           Also note that the make target becomes "make xipImage" rather than
1937           "make zImage" or "make Image".  The final kernel binary to put in
1938           ROM memory will be arch/arm/boot/xipImage.
1939 
1940           If unsure, say N.
1941 
1942 config XIP_PHYS_ADDR
1943         hex "XIP Kernel Physical Location"
1944         depends on XIP_KERNEL
1945         default "0x00080000"
1946         help
1947           This is the physical address in your flash memory the kernel will
1948           be linked for and stored to.  This address is dependent on your
1949           own flash usage.
1950 
1951 config KEXEC
1952         bool "Kexec system call (EXPERIMENTAL)"
1953         depends on (!SMP || PM_SLEEP_SMP)
1954         help
1955           kexec is a system call that implements the ability to shutdown your
1956           current kernel, and to start another kernel.  It is like a reboot
1957           but it is independent of the system firmware.   And like a reboot
1958           you can start any kernel with it, not just Linux.
1959 
1960           It is an ongoing process to be certain the hardware in a machine
1961           is properly shutdown, so do not be surprised if this code does not
1962           initially work for you.
1963 
1964 config ATAGS_PROC
1965         bool "Export atags in procfs"
1966         depends on ATAGS && KEXEC
1967         default y
1968         help
1969           Should the atags used to boot the kernel be exported in an "atags"
1970           file in procfs. Useful with kexec.
1971 
1972 config CRASH_DUMP
1973         bool "Build kdump crash kernel (EXPERIMENTAL)"
1974         help
1975           Generate crash dump after being started by kexec. This should
1976           be normally only set in special crash dump kernels which are
1977           loaded in the main kernel with kexec-tools into a specially
1978           reserved region and then later executed after a crash by
1979           kdump/kexec. The crash dump kernel must be compiled to a
1980           memory address not used by the main kernel
1981 
1982           For more details see Documentation/kdump/kdump.txt
1983 
1984 config AUTO_ZRELADDR
1985         bool "Auto calculation of the decompressed kernel image address"
1986         help
1987           ZRELADDR is the physical address where the decompressed kernel
1988           image will be placed. If AUTO_ZRELADDR is selected, the address
1989           will be determined at run-time by masking the current IP with
1990           0xf8000000. This assumes the zImage being placed in the first 128MB
1991           from start of memory.
1992 
1993 endmenu
1994 
1995 menu "CPU Power Management"
1996 
1997 source "drivers/cpufreq/Kconfig"
1998 
1999 source "drivers/cpuidle/Kconfig"
2000 
2001 endmenu
2002 
2003 menu "Floating point emulation"
2004 
2005 comment "At least one emulation must be selected"
2006 
2007 config FPE_NWFPE
2008         bool "NWFPE math emulation"
2009         depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
2010         ---help---
2011           Say Y to include the NWFPE floating point emulator in the kernel.
2012           This is necessary to run most binaries. Linux does not currently
2013           support floating point hardware so you need to say Y here even if
2014           your machine has an FPA or floating point co-processor podule.
2015 
2016           You may say N here if you are going to load the Acorn FPEmulator
2017           early in the bootup.
2018 
2019 config FPE_NWFPE_XP
2020         bool "Support extended precision"
2021         depends on FPE_NWFPE
2022         help
2023           Say Y to include 80-bit support in the kernel floating-point
2024           emulator.  Otherwise, only 32 and 64-bit support is compiled in.
2025           Note that gcc does not generate 80-bit operations by default,
2026           so in most cases this option only enlarges the size of the
2027           floating point emulator without any good reason.
2028 
2029           You almost surely want to say N here.
2030 
2031 config FPE_FASTFPE
2032         bool "FastFPE math emulation (EXPERIMENTAL)"
2033         depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
2034         ---help---
2035           Say Y here to include the FAST floating point emulator in the kernel.
2036           This is an experimental much faster emulator which now also has full
2037           precision for the mantissa.  It does not support any exceptions.
2038           It is very simple, and approximately 3-6 times faster than NWFPE.
2039 
2040           It should be sufficient for most programs.  It may be not suitable
2041           for scientific calculations, but you have to check this for yourself.
2042           If you do not feel you need a faster FP emulation you should better
2043           choose NWFPE.
2044 
2045 config VFP
2046         bool "VFP-format floating point maths"
2047         depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
2048         help
2049           Say Y to include VFP support code in the kernel. This is needed
2050           if your hardware includes a VFP unit.
2051 
2052           Please see <file:Documentation/arm/VFP/release-notes.txt> for
2053           release notes and additional status information.
2054 
2055           Say N if your target does not have VFP hardware.
2056 
2057 config VFPv3
2058         bool
2059         depends on VFP
2060         default y if CPU_V7
2061 
2062 config NEON
2063         bool "Advanced SIMD (NEON) Extension support"
2064         depends on VFPv3 && CPU_V7
2065         help
2066           Say Y to include support code for NEON, the ARMv7 Advanced SIMD
2067           Extension.
2068 
2069 config KERNEL_MODE_NEON
2070         bool "Support for NEON in kernel mode"
2071         depends on NEON && AEABI
2072         help
2073           Say Y to include support for NEON in kernel mode.
2074 
2075 endmenu
2076 
2077 menu "Userspace binary formats"
2078 
2079 source "fs/Kconfig.binfmt"
2080 
2081 endmenu
2082 
2083 menu "Power management options"
2084 
2085 source "kernel/power/Kconfig"
2086 
2087 config ARCH_SUSPEND_POSSIBLE
2088         depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
2089                 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
2090         def_bool y
2091 
2092 config ARM_CPU_SUSPEND
2093         def_bool PM_SLEEP
2094 
2095 config ARCH_HIBERNATION_POSSIBLE
2096         bool
2097         depends on MMU
2098         default y if ARCH_SUSPEND_POSSIBLE
2099 
2100 endmenu
2101 
2102 source "net/Kconfig"
2103 
2104 source "drivers/Kconfig"
2105 
2106 source "drivers/firmware/Kconfig"
2107 
2108 source "fs/Kconfig"
2109 
2110 source "arch/arm/Kconfig.debug"
2111 
2112 source "security/Kconfig"
2113 
2114 source "crypto/Kconfig"
2115 if CRYPTO
2116 source "arch/arm/crypto/Kconfig"
2117 endif
2118 
2119 source "lib/Kconfig"
2120 
2121 source "arch/arm/kvm/Kconfig"

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