Version:  2.0.40 2.2.26 2.4.37 2.6.39 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 3.13 3.14 3.15

Linux/arch/arc/plat-arcfpga/Kconfig

  1 #
  2 # Copyright (C) 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
  3 #
  4 # This program is free software; you can redistribute it and/or modify
  5 # it under the terms of the GNU General Public License version 2 as
  6 # published by the Free Software Foundation.
  7 #
  8 
  9 menuconfig ARC_PLAT_FPGA_LEGACY
 10         bool "\"Legacy\" ARC FPGA dev Boards"
 11         select ISS_SMP_EXTN if SMP
 12         help
 13           Support for ARC development boards, provided by Synopsys.
 14           These are based on FPGA or ISS. e.g.
 15           - ARCAngel4
 16           - ML509
 17           - MetaWare ISS
 18 
 19 if ARC_PLAT_FPGA_LEGACY
 20 
 21 config ARC_BOARD_ANGEL4
 22         bool "ARC Angel4"
 23         default y
 24         help
 25           ARC Angel4 FPGA Ref Platform (Xilinx Virtex Based)
 26 
 27 config ARC_BOARD_ML509
 28         bool "ML509"
 29         help
 30           ARC ML509 FPGA Ref Platform (Xilinx Virtex-5 Based)
 31 
 32 config ISS_SMP_EXTN
 33         bool "ARC SMP Extensions (ISS Models only)"
 34         default n
 35         depends on SMP
 36         help
 37           SMP Extensions to ARC700, in a "simulation only" Model, supported in
 38           ARC ISS (Instruction Set Simulator).
 39           The SMP extensions include:
 40           -IDU (Interrupt Distribution Unit)
 41           -XTL (To enable CPU start/stop/set-PC for another CPU)
 42           It doesn't provide coherent Caches and/or Atomic Ops (LLOCK/SCOND)
 43 
 44 config ARC_SERIAL_BAUD
 45         int "UART Baud rate"
 46         default "115200"
 47         depends on SERIAL_ARC || SERIAL_ARC_CONSOLE
 48         help
 49           Baud rate for the ARC UART
 50 
 51 menuconfig ARC_HAS_BVCI_LAT_UNIT
 52         bool "BVCI Bus Latency Unit"
 53         depends on ARC_BOARD_ML509 || ARC_BOARD_ANGEL4
 54         help
 55           IP to add artificial latency to BVCI Bus Based FPGA builds.
 56           The default latency (even worst case) for FPGA is non-realistic
 57           (~10 SDRAM, ~5 SSRAM).
 58 
 59 config BVCI_LAT_UNITS
 60         hex "Latency Unit(s) Bitmap"
 61         default "0x0"
 62         depends on ARC_HAS_BVCI_LAT_UNIT
 63         help
 64           There are multiple Latency Units corresponding to the many
 65           interfaces of the system bus arbiter (both CPU side as well as
 66           the peripheral side).
 67           To add latency to ALL memory transaction, choose Unit 0, otherwise
 68           for finer grainer - interface wise latency, specify a bitmap (1 bit
 69           per unit) of all units. e.g. 1,2,12 will be 0x1003
 70 
 71           Unit  0 - System Arb and Mem Controller
 72           Unit  1 - I$ and System Bus
 73           Unit  2 - D$ and System Bus
 74           ..
 75           Unit 12 - IDE Disk controller and System Bus
 76 
 77 config BVCI_LAT_CYCLES
 78         int "Latency Value in cycles"
 79         range 0 63
 80         default "30"
 81         depends on ARC_HAS_BVCI_LAT_UNIT
 82 
 83 endif

This page was automatically generated by LXR 0.3.1 (source).  •  Linux is a registered trademark of Linus Torvalds  •  Contact us