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Linux/arch/arc/Kconfig

  1 #
  2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
  3 #
  4 # This program is free software; you can redistribute it and/or modify
  5 # it under the terms of the GNU General Public License version 2 as
  6 # published by the Free Software Foundation.
  7 #
  8 
  9 config ARC
 10         def_bool y
 11         select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
 12         select BUILDTIME_EXTABLE_SORT
 13         select COMMON_CLK
 14         select CLONE_BACKWARDS
 15         # ARC Busybox based initramfs absolutely relies on DEVTMPFS for /dev
 16         select DEVTMPFS if !INITRAMFS_SOURCE=""
 17         select GENERIC_ATOMIC64
 18         select GENERIC_CLOCKEVENTS
 19         select GENERIC_FIND_FIRST_BIT
 20         # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
 21         select GENERIC_IRQ_SHOW
 22         select GENERIC_PENDING_IRQ if SMP
 23         select GENERIC_SMP_IDLE_THREAD
 24         select HAVE_ARCH_KGDB
 25         select HAVE_ARCH_TRACEHOOK
 26         select HAVE_FUTEX_CMPXCHG
 27         select HAVE_IOREMAP_PROT
 28         select HAVE_KPROBES
 29         select HAVE_KRETPROBES
 30         select HAVE_MEMBLOCK
 31         select HAVE_MOD_ARCH_SPECIFIC if ARC_DW2_UNWIND
 32         select HAVE_OPROFILE
 33         select HAVE_PERF_EVENTS
 34         select IRQ_DOMAIN
 35         select MODULES_USE_ELF_RELA
 36         select NO_BOOTMEM
 37         select OF
 38         select OF_EARLY_FLATTREE
 39         select PERF_USE_VMALLOC
 40         select HAVE_DEBUG_STACKOVERFLOW
 41 
 42 config TRACE_IRQFLAGS_SUPPORT
 43         def_bool y
 44 
 45 config LOCKDEP_SUPPORT
 46         def_bool y
 47 
 48 config SCHED_OMIT_FRAME_POINTER
 49         def_bool y
 50 
 51 config GENERIC_CSUM
 52         def_bool y
 53 
 54 config RWSEM_GENERIC_SPINLOCK
 55         def_bool y
 56 
 57 config ARCH_FLATMEM_ENABLE
 58         def_bool y
 59 
 60 config MMU
 61         def_bool y
 62 
 63 config NO_IOPORT_MAP
 64         def_bool y
 65 
 66 config GENERIC_CALIBRATE_DELAY
 67         def_bool y
 68 
 69 config GENERIC_HWEIGHT
 70         def_bool y
 71 
 72 config STACKTRACE_SUPPORT
 73         def_bool y
 74         select STACKTRACE
 75 
 76 config HAVE_LATENCYTOP_SUPPORT
 77         def_bool y
 78 
 79 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
 80         def_bool y
 81         depends on ARC_MMU_V4
 82 
 83 source "init/Kconfig"
 84 source "kernel/Kconfig.freezer"
 85 
 86 menu "ARC Architecture Configuration"
 87 
 88 menu "ARC Platform/SoC/Board"
 89 
 90 source "arch/arc/plat-sim/Kconfig"
 91 source "arch/arc/plat-tb10x/Kconfig"
 92 source "arch/arc/plat-axs10x/Kconfig"
 93 #New platform adds here
 94 
 95 endmenu
 96 
 97 choice
 98         prompt "ARC Instruction Set"
 99         default ISA_ARCOMPACT
100 
101 config ISA_ARCOMPACT
102         bool "ARCompact ISA"
103         help
104           The original ARC ISA of ARC600/700 cores
105 
106 config ISA_ARCV2
107         bool "ARC ISA v2"
108         help
109           ISA for the Next Generation ARC-HS cores
110 
111 endchoice
112 
113 menu "ARC CPU Configuration"
114 
115 choice
116         prompt "ARC Core"
117         default ARC_CPU_770 if ISA_ARCOMPACT
118         default ARC_CPU_HS if ISA_ARCV2
119 
120 if ISA_ARCOMPACT
121 
122 config ARC_CPU_750D
123         bool "ARC750D"
124         select ARC_CANT_LLSC
125         help
126           Support for ARC750 core
127 
128 config ARC_CPU_770
129         bool "ARC770"
130         select ARC_HAS_SWAPE
131         help
132           Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
133           This core has a bunch of cool new features:
134           -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
135                    Shared Address Spaces (for sharing TLB entires in MMU)
136           -Caches: New Prog Model, Region Flush
137           -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
138 
139 endif   #ISA_ARCOMPACT
140 
141 config ARC_CPU_HS
142         bool "ARC-HS"
143         depends on ISA_ARCV2
144         help
145           Support for ARC HS38x Cores based on ARCv2 ISA
146           The notable features are:
147             - SMP configurations of upto 4 core with coherency
148             - Optional L2 Cache and IO-Coherency
149             - Revised Interrupt Architecture (multiple priorites, reg banks,
150                 auto stack switch, auto regfile save/restore)
151             - MMUv4 (PIPT dcache, Huge Pages)
152             - Instructions for
153                 * 64bit load/store: LDD, STD
154                 * Hardware assisted divide/remainder: DIV, REM
155                 * Function prologue/epilogue: ENTER_S, LEAVE_S
156                 * IRQ enable/disable: CLRI, SETI
157                 * pop count: FFS, FLS
158                 * SETcc, BMSKN, XBFU...
159 
160 endchoice
161 
162 config CPU_BIG_ENDIAN
163         bool "Enable Big Endian Mode"
164         default n
165         help
166           Build kernel for Big Endian Mode of ARC CPU
167 
168 config SMP
169         bool "Symmetric Multi-Processing"
170         default n
171         select ARC_HAS_COH_CACHES if ISA_ARCV2
172         select ARC_MCIP if ISA_ARCV2
173         help
174           This enables support for systems with more than one CPU.
175 
176 if SMP
177 
178 config ARC_HAS_COH_CACHES
179         def_bool n
180 
181 config ARC_HAS_REENTRANT_IRQ_LV2
182         def_bool n
183 
184 config ARC_MCIP
185         bool "ARConnect Multicore IP (MCIP) Support "
186         depends on ISA_ARCV2
187         help
188           This IP block enables SMP in ARC-HS38 cores.
189           It provides for cross-core interrupts, multi-core debug
190           hardware semaphores, shared memory,....
191 
192 config NR_CPUS
193         int "Maximum number of CPUs (2-4096)"
194         range 2 4096
195         default "4"
196 
197 config ARC_SMP_HALT_ON_RESET
198         bool "Enable Halt-on-reset boot mode"
199         default y if ARC_UBOOT_SUPPORT
200         help
201           In SMP configuration cores can be configured as Halt-on-reset
202           or they could all start at same time. For Halt-on-reset, non
203           masters are parked until Master kicks them so they can start of
204           at designated entry point. For other case, all jump to common
205           entry point and spin wait for Master's signal.
206 
207 endif   #SMP
208 
209 menuconfig ARC_CACHE
210         bool "Enable Cache Support"
211         default y
212         # if SMP, cache enabled ONLY if ARC implementation has cache coherency
213         depends on !SMP || ARC_HAS_COH_CACHES
214 
215 if ARC_CACHE
216 
217 config ARC_CACHE_LINE_SHIFT
218         int "Cache Line Length (as power of 2)"
219         range 5 7
220         default "6"
221         help
222           Starting with ARC700 4.9, Cache line length is configurable,
223           This option specifies "N", with Line-len = 2 power N
224           So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
225           Linux only supports same line lengths for I and D caches.
226 
227 config ARC_HAS_ICACHE
228         bool "Use Instruction Cache"
229         default y
230 
231 config ARC_HAS_DCACHE
232         bool "Use Data Cache"
233         default y
234 
235 config ARC_CACHE_PAGES
236         bool "Per Page Cache Control"
237         default y
238         depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
239         help
240           This can be used to over-ride the global I/D Cache Enable on a
241           per-page basis (but only for pages accessed via MMU such as
242           Kernel Virtual address or User Virtual Address)
243           TLB entries have a per-page Cache Enable Bit.
244           Note that Global I/D ENABLE + Per Page DISABLE works but corollary
245           Global DISABLE + Per Page ENABLE won't work
246 
247 config ARC_CACHE_VIPT_ALIASING
248         bool "Support VIPT Aliasing D$"
249         depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
250         default n
251 
252 endif   #ARC_CACHE
253 
254 config ARC_HAS_ICCM
255         bool "Use ICCM"
256         help
257           Single Cycle RAMS to store Fast Path Code
258         default n
259 
260 config ARC_ICCM_SZ
261         int "ICCM Size in KB"
262         default "64"
263         depends on ARC_HAS_ICCM
264 
265 config ARC_HAS_DCCM
266         bool "Use DCCM"
267         help
268           Single Cycle RAMS to store Fast Path Data
269         default n
270 
271 config ARC_DCCM_SZ
272         int "DCCM Size in KB"
273         default "64"
274         depends on ARC_HAS_DCCM
275 
276 config ARC_DCCM_BASE
277         hex "DCCM map address"
278         default "0xA0000000"
279         depends on ARC_HAS_DCCM
280 
281 config ARC_HAS_HW_MPY
282         bool "Use Hardware Multiplier (Normal or Faster XMAC)"
283         default y
284         help
285           Influences how gcc generates code for MPY operations.
286           If enabled, MPYxx insns are generated, provided by Standard/XMAC
287           Multipler. Otherwise software multipy lib is used
288 
289 choice
290         prompt "MMU Version"
291         default ARC_MMU_V3 if ARC_CPU_770
292         default ARC_MMU_V2 if ARC_CPU_750D
293         default ARC_MMU_V4 if ARC_CPU_HS
294 
295 if ISA_ARCOMPACT
296 
297 config ARC_MMU_V1
298         bool "MMU v1"
299         help
300           Orig ARC700 MMU
301 
302 config ARC_MMU_V2
303         bool "MMU v2"
304         help
305           Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
306           when 2 D-TLB and 1 I-TLB entries index into same 2way set.
307 
308 config ARC_MMU_V3
309         bool "MMU v3"
310         depends on ARC_CPU_770
311         help
312           Introduced with ARC700 4.10: New Features
313           Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
314           Shared Address Spaces (SASID)
315 
316 endif
317 
318 config ARC_MMU_V4
319         bool "MMU v4"
320         depends on ISA_ARCV2
321 
322 endchoice
323 
324 
325 choice
326         prompt "MMU Page Size"
327         default ARC_PAGE_SIZE_8K
328 
329 config ARC_PAGE_SIZE_8K
330         bool "8KB"
331         help
332           Choose between 8k vs 16k
333 
334 config ARC_PAGE_SIZE_16K
335         bool "16KB"
336         depends on ARC_MMU_V3 || ARC_MMU_V4
337 
338 config ARC_PAGE_SIZE_4K
339         bool "4KB"
340         depends on ARC_MMU_V3 || ARC_MMU_V4
341 
342 endchoice
343 
344 if ISA_ARCOMPACT
345 
346 config ARC_COMPACT_IRQ_LEVELS
347         bool "ARCompact IRQ Priorities: High(2)/Low(1)"
348         default n
349         # Timer HAS to be high priority, for any other high priority config
350         select ARC_IRQ3_LV2
351         # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
352         depends on !SMP || ARC_HAS_REENTRANT_IRQ_LV2
353 
354 if ARC_COMPACT_IRQ_LEVELS
355 
356 config ARC_IRQ3_LV2
357         bool
358 
359 config ARC_IRQ5_LV2
360         bool
361 
362 config ARC_IRQ6_LV2
363         bool
364 
365 endif   #ARC_COMPACT_IRQ_LEVELS
366 
367 config ARC_FPU_SAVE_RESTORE
368         bool "Enable FPU state persistence across context switch"
369         default n
370         help
371           Double Precision Floating Point unit had dedictaed regs which
372           need to be saved/restored across context-switch.
373           Note that ARC FPU is overly simplistic, unlike say x86, which has
374           hardware pieces to allow software to conditionally save/restore,
375           based on actual usage of FPU by a task. Thus our implemn does
376           this for all tasks in system.
377 
378 endif   #ISA_ARCOMPACT
379 
380 config ARC_CANT_LLSC
381         def_bool n
382 
383 config ARC_HAS_LLSC
384         bool "Insn: LLOCK/SCOND (efficient atomic ops)"
385         default y
386         depends on !ARC_CANT_LLSC
387 
388 config ARC_STAR_9000923308
389         bool "Workaround for llock/scond livelock"
390         default y
391         depends on ISA_ARCV2 && SMP && ARC_HAS_LLSC
392 
393 config ARC_HAS_SWAPE
394         bool "Insn: SWAPE (endian-swap)"
395         default y
396 
397 if ISA_ARCV2
398 
399 config ARC_HAS_LL64
400         bool "Insn: 64bit LDD/STD"
401         help
402           Enable gcc to generate 64-bit load/store instructions
403           ISA mandates even/odd registers to allow encoding of two
404           dest operands with 2 possible source operands.
405         default y
406 
407 config ARC_HAS_DIV_REM
408         bool "Insn: div, divu, rem, remu"
409         default y
410 
411 config ARC_HAS_RTC
412         bool "Local 64-bit r/o cycle counter"
413         default n
414         depends on !SMP
415 
416 config ARC_HAS_GRTC
417         bool "SMP synchronized 64-bit cycle counter"
418         default y
419         depends on SMP
420 
421 config ARC_NUMBER_OF_INTERRUPTS
422         int "Number of interrupts"
423         range 8 240
424         default 32
425         help
426           This defines the number of interrupts on the ARCv2HS core.
427           It affects the size of vector table.
428           The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
429           in hardware, it keep things simple for Linux to assume they are always
430           present.
431 
432 endif   # ISA_ARCV2
433 
434 endmenu   # "ARC CPU Configuration"
435 
436 config LINUX_LINK_BASE
437         hex "Linux Link Address"
438         default "0x80000000"
439         help
440           ARC700 divides the 32 bit phy address space into two equal halves
441           -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
442           -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
443           Typically Linux kernel is linked at the start of untransalted addr,
444           hence the default value of 0x8zs.
445           However some customers have peripherals mapped at this addr, so
446           Linux needs to be scooted a bit.
447           If you don't know what the above means, leave this setting alone.
448           This needs to match memory start address specified in Device Tree
449 
450 config HIGHMEM
451         bool "High Memory Support"
452         help
453           With ARC 2G:2G address split, only upper 2G is directly addressable by
454           kernel. Enable this to potentially allow access to rest of 2G and PAE
455           in future
456 
457 config ARC_HAS_PAE40
458         bool "Support for the 40-bit Physical Address Extension"
459         default n
460         depends on ISA_ARCV2
461         select HIGHMEM
462         help
463           Enable access to physical memory beyond 4G, only supported on
464           ARC cores with 40 bit Physical Addressing support
465 
466 config ARCH_PHYS_ADDR_T_64BIT
467         def_bool ARC_HAS_PAE40
468 
469 config ARCH_DMA_ADDR_T_64BIT
470         bool
471 
472 config ARC_CURR_IN_REG
473         bool "Dedicate Register r25 for current_task pointer"
474         default y
475         help
476           This reserved Register R25 to point to Current Task in
477           kernel mode. This saves memory access for each such access
478 
479 
480 config ARC_EMUL_UNALIGNED
481         bool "Emulate unaligned memory access (userspace only)"
482         default N
483         select SYSCTL_ARCH_UNALIGN_NO_WARN
484         select SYSCTL_ARCH_UNALIGN_ALLOW
485         depends on ISA_ARCOMPACT
486         help
487           This enables misaligned 16 & 32 bit memory access from user space.
488           Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
489           potential bugs in code
490 
491 config HZ
492         int "Timer Frequency"
493         default 100
494 
495 config ARC_METAWARE_HLINK
496         bool "Support for Metaware debugger assisted Host access"
497         default n
498         help
499           This options allows a Linux userland apps to directly access
500           host file system (open/creat/read/write etc) with help from
501           Metaware Debugger. This can come in handy for Linux-host communication
502           when there is no real usable peripheral such as EMAC.
503 
504 menuconfig ARC_DBG
505         bool "ARC debugging"
506         default y
507 
508 if ARC_DBG
509 
510 config ARC_DW2_UNWIND
511         bool "Enable DWARF specific kernel stack unwind"
512         default y
513         select KALLSYMS
514         help
515           Compiles the kernel with DWARF unwind information and can be used
516           to get stack backtraces.
517 
518           If you say Y here the resulting kernel image will be slightly larger
519           but not slower, and it will give very useful debugging information.
520           If you don't debug the kernel, you can say N, but we may not be able
521           to solve problems without frame unwind information
522 
523 config ARC_DBG_TLB_PARANOIA
524         bool "Paranoia Checks in Low Level TLB Handlers"
525         default n
526 
527 config ARC_DBG_TLB_MISS_COUNT
528         bool "Profile TLB Misses"
529         default n
530         select DEBUG_FS
531         help
532           Counts number of I and D TLB Misses and exports them via Debugfs
533           The counters can be cleared via Debugfs as well
534 
535 if SMP
536 
537 config ARC_IPI_DBG
538         bool "Debug Inter Core interrupts"
539         default n
540 
541 endif
542 
543 endif
544 
545 config ARC_UBOOT_SUPPORT
546         bool "Support uboot arg Handling"
547         default n
548         help
549           ARC Linux by default checks for uboot provided args as pointers to
550           external cmdline or DTB. This however breaks in absence of uboot,
551           when booting from Metaware debugger directly, as the registers are
552           not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
553           registers look like uboot args to kernel which then chokes.
554           So only enable the uboot arg checking/processing if users are sure
555           of uboot being in play.
556 
557 config ARC_BUILTIN_DTB_NAME
558         string "Built in DTB"
559         help
560           Set the name of the DTB to embed in the vmlinux binary
561           Leaving it blank selects the minimal "skeleton" dtb
562 
563 source "kernel/Kconfig.preempt"
564 
565 menu "Executable file formats"
566 source "fs/Kconfig.binfmt"
567 endmenu
568 
569 endmenu  # "ARC Architecture Configuration"
570 
571 source "mm/Kconfig"
572 source "net/Kconfig"
573 source "drivers/Kconfig"
574 source "fs/Kconfig"
575 source "arch/arc/Kconfig.debug"
576 source "security/Kconfig"
577 source "crypto/Kconfig"
578 source "lib/Kconfig"
579 source "kernel/power/Kconfig"

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