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Linux/arch/arc/Kconfig

  1 #
  2 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
  3 #
  4 # This program is free software; you can redistribute it and/or modify
  5 # it under the terms of the GNU General Public License version 2 as
  6 # published by the Free Software Foundation.
  7 #
  8 
  9 config ARC
 10         def_bool y
 11         select ARC_TIMERS
 12         select ARCH_HAS_SG_CHAIN
 13         select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
 14         select BUILDTIME_EXTABLE_SORT
 15         select CLONE_BACKWARDS
 16         select COMMON_CLK
 17         select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
 18         select GENERIC_CLOCKEVENTS
 19         select GENERIC_FIND_FIRST_BIT
 20         # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
 21         select GENERIC_IRQ_SHOW
 22         select GENERIC_PCI_IOMAP
 23         select GENERIC_PENDING_IRQ if SMP
 24         select GENERIC_SMP_IDLE_THREAD
 25         select HAVE_ARCH_KGDB
 26         select HAVE_ARCH_TRACEHOOK
 27         select HAVE_FUTEX_CMPXCHG
 28         select HAVE_IOREMAP_PROT
 29         select HAVE_KPROBES
 30         select HAVE_KRETPROBES
 31         select HAVE_MEMBLOCK
 32         select HAVE_MOD_ARCH_SPECIFIC
 33         select HAVE_OPROFILE
 34         select HAVE_PERF_EVENTS
 35         select HANDLE_DOMAIN_IRQ
 36         select IRQ_DOMAIN
 37         select MODULES_USE_ELF_RELA
 38         select NO_BOOTMEM
 39         select OF
 40         select OF_EARLY_FLATTREE
 41         select OF_RESERVED_MEM
 42         select PERF_USE_VMALLOC
 43         select HAVE_DEBUG_STACKOVERFLOW
 44         select HAVE_GENERIC_DMA_COHERENT
 45         select HAVE_KERNEL_GZIP
 46         select HAVE_KERNEL_LZMA
 47 
 48 config MIGHT_HAVE_PCI
 49         bool
 50 
 51 config TRACE_IRQFLAGS_SUPPORT
 52         def_bool y
 53 
 54 config LOCKDEP_SUPPORT
 55         def_bool y
 56 
 57 config SCHED_OMIT_FRAME_POINTER
 58         def_bool y
 59 
 60 config GENERIC_CSUM
 61         def_bool y
 62 
 63 config RWSEM_GENERIC_SPINLOCK
 64         def_bool y
 65 
 66 config ARCH_DISCONTIGMEM_ENABLE
 67         def_bool n
 68 
 69 config ARCH_FLATMEM_ENABLE
 70         def_bool y
 71 
 72 config MMU
 73         def_bool y
 74 
 75 config NO_IOPORT_MAP
 76         def_bool y
 77 
 78 config GENERIC_CALIBRATE_DELAY
 79         def_bool y
 80 
 81 config GENERIC_HWEIGHT
 82         def_bool y
 83 
 84 config STACKTRACE_SUPPORT
 85         def_bool y
 86         select STACKTRACE
 87 
 88 config HAVE_ARCH_TRANSPARENT_HUGEPAGE
 89         def_bool y
 90         depends on ARC_MMU_V4
 91 
 92 source "init/Kconfig"
 93 source "kernel/Kconfig.freezer"
 94 
 95 menu "ARC Architecture Configuration"
 96 
 97 menu "ARC Platform/SoC/Board"
 98 
 99 source "arch/arc/plat-sim/Kconfig"
100 source "arch/arc/plat-tb10x/Kconfig"
101 source "arch/arc/plat-axs10x/Kconfig"
102 #New platform adds here
103 source "arch/arc/plat-eznps/Kconfig"
104 
105 endmenu
106 
107 choice
108         prompt "ARC Instruction Set"
109         default ISA_ARCOMPACT
110 
111 config ISA_ARCOMPACT
112         bool "ARCompact ISA"
113         select CPU_NO_EFFICIENT_FFS
114         help
115           The original ARC ISA of ARC600/700 cores
116 
117 config ISA_ARCV2
118         bool "ARC ISA v2"
119         select ARC_TIMERS_64BIT
120         help
121           ISA for the Next Generation ARC-HS cores
122 
123 endchoice
124 
125 menu "ARC CPU Configuration"
126 
127 choice
128         prompt "ARC Core"
129         default ARC_CPU_770 if ISA_ARCOMPACT
130         default ARC_CPU_HS if ISA_ARCV2
131 
132 if ISA_ARCOMPACT
133 
134 config ARC_CPU_750D
135         bool "ARC750D"
136         select ARC_CANT_LLSC
137         help
138           Support for ARC750 core
139 
140 config ARC_CPU_770
141         bool "ARC770"
142         select ARC_HAS_SWAPE
143         help
144           Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
145           This core has a bunch of cool new features:
146           -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
147                    Shared Address Spaces (for sharing TLB entires in MMU)
148           -Caches: New Prog Model, Region Flush
149           -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
150 
151 endif   #ISA_ARCOMPACT
152 
153 config ARC_CPU_HS
154         bool "ARC-HS"
155         depends on ISA_ARCV2
156         help
157           Support for ARC HS38x Cores based on ARCv2 ISA
158           The notable features are:
159             - SMP configurations of upto 4 core with coherency
160             - Optional L2 Cache and IO-Coherency
161             - Revised Interrupt Architecture (multiple priorites, reg banks,
162                 auto stack switch, auto regfile save/restore)
163             - MMUv4 (PIPT dcache, Huge Pages)
164             - Instructions for
165                 * 64bit load/store: LDD, STD
166                 * Hardware assisted divide/remainder: DIV, REM
167                 * Function prologue/epilogue: ENTER_S, LEAVE_S
168                 * IRQ enable/disable: CLRI, SETI
169                 * pop count: FFS, FLS
170                 * SETcc, BMSKN, XBFU...
171 
172 endchoice
173 
174 config CPU_BIG_ENDIAN
175         bool "Enable Big Endian Mode"
176         default n
177         help
178           Build kernel for Big Endian Mode of ARC CPU
179 
180 config SMP
181         bool "Symmetric Multi-Processing"
182         default n
183         select ARC_HAS_COH_CACHES if ISA_ARCV2
184         select ARC_MCIP if ISA_ARCV2
185         help
186           This enables support for systems with more than one CPU.
187 
188 if SMP
189 
190 config ARC_HAS_COH_CACHES
191         def_bool n
192 
193 config NR_CPUS
194         int "Maximum number of CPUs (2-4096)"
195         range 2 4096
196         default "4"
197 
198 config ARC_SMP_HALT_ON_RESET
199         bool "Enable Halt-on-reset boot mode"
200         default y if ARC_UBOOT_SUPPORT
201         help
202           In SMP configuration cores can be configured as Halt-on-reset
203           or they could all start at same time. For Halt-on-reset, non
204           masters are parked until Master kicks them so they can start of
205           at designated entry point. For other case, all jump to common
206           entry point and spin wait for Master's signal.
207 
208 endif   #SMP
209 
210 config ARC_MCIP
211         bool "ARConnect Multicore IP (MCIP) Support "
212         depends on ISA_ARCV2
213         default y if SMP
214         help
215           This IP block enables SMP in ARC-HS38 cores.
216           It provides for cross-core interrupts, multi-core debug
217           hardware semaphores, shared memory,....
218 
219 menuconfig ARC_CACHE
220         bool "Enable Cache Support"
221         default y
222         # if SMP, cache enabled ONLY if ARC implementation has cache coherency
223         depends on !SMP || ARC_HAS_COH_CACHES
224 
225 if ARC_CACHE
226 
227 config ARC_CACHE_LINE_SHIFT
228         int "Cache Line Length (as power of 2)"
229         range 5 7
230         default "6"
231         help
232           Starting with ARC700 4.9, Cache line length is configurable,
233           This option specifies "N", with Line-len = 2 power N
234           So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
235           Linux only supports same line lengths for I and D caches.
236 
237 config ARC_HAS_ICACHE
238         bool "Use Instruction Cache"
239         default y
240 
241 config ARC_HAS_DCACHE
242         bool "Use Data Cache"
243         default y
244 
245 config ARC_CACHE_PAGES
246         bool "Per Page Cache Control"
247         default y
248         depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
249         help
250           This can be used to over-ride the global I/D Cache Enable on a
251           per-page basis (but only for pages accessed via MMU such as
252           Kernel Virtual address or User Virtual Address)
253           TLB entries have a per-page Cache Enable Bit.
254           Note that Global I/D ENABLE + Per Page DISABLE works but corollary
255           Global DISABLE + Per Page ENABLE won't work
256 
257 config ARC_CACHE_VIPT_ALIASING
258         bool "Support VIPT Aliasing D$"
259         depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
260         default n
261 
262 endif   #ARC_CACHE
263 
264 config ARC_HAS_ICCM
265         bool "Use ICCM"
266         help
267           Single Cycle RAMS to store Fast Path Code
268         default n
269 
270 config ARC_ICCM_SZ
271         int "ICCM Size in KB"
272         default "64"
273         depends on ARC_HAS_ICCM
274 
275 config ARC_HAS_DCCM
276         bool "Use DCCM"
277         help
278           Single Cycle RAMS to store Fast Path Data
279         default n
280 
281 config ARC_DCCM_SZ
282         int "DCCM Size in KB"
283         default "64"
284         depends on ARC_HAS_DCCM
285 
286 config ARC_DCCM_BASE
287         hex "DCCM map address"
288         default "0xA0000000"
289         depends on ARC_HAS_DCCM
290 
291 choice
292         prompt "MMU Version"
293         default ARC_MMU_V3 if ARC_CPU_770
294         default ARC_MMU_V2 if ARC_CPU_750D
295         default ARC_MMU_V4 if ARC_CPU_HS
296 
297 if ISA_ARCOMPACT
298 
299 config ARC_MMU_V1
300         bool "MMU v1"
301         help
302           Orig ARC700 MMU
303 
304 config ARC_MMU_V2
305         bool "MMU v2"
306         help
307           Fixed the deficiency of v1 - possible thrashing in memcpy sceanrio
308           when 2 D-TLB and 1 I-TLB entries index into same 2way set.
309 
310 config ARC_MMU_V3
311         bool "MMU v3"
312         depends on ARC_CPU_770
313         help
314           Introduced with ARC700 4.10: New Features
315           Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
316           Shared Address Spaces (SASID)
317 
318 endif
319 
320 config ARC_MMU_V4
321         bool "MMU v4"
322         depends on ISA_ARCV2
323 
324 endchoice
325 
326 
327 choice
328         prompt "MMU Page Size"
329         default ARC_PAGE_SIZE_8K
330 
331 config ARC_PAGE_SIZE_8K
332         bool "8KB"
333         help
334           Choose between 8k vs 16k
335 
336 config ARC_PAGE_SIZE_16K
337         bool "16KB"
338         depends on ARC_MMU_V3 || ARC_MMU_V4
339 
340 config ARC_PAGE_SIZE_4K
341         bool "4KB"
342         depends on ARC_MMU_V3 || ARC_MMU_V4
343 
344 endchoice
345 
346 choice
347         prompt "MMU Super Page Size"
348         depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
349         default ARC_HUGEPAGE_2M
350 
351 config ARC_HUGEPAGE_2M
352         bool "2MB"
353 
354 config ARC_HUGEPAGE_16M
355         bool "16MB"
356 
357 endchoice
358 
359 config NODES_SHIFT
360         int "Maximum NUMA Nodes (as a power of 2)"
361         default "0" if !DISCONTIGMEM
362         default "1" if DISCONTIGMEM
363         depends on NEED_MULTIPLE_NODES
364         ---help---
365           Accessing memory beyond 1GB (with or w/o PAE) requires 2 memory
366           zones.
367 
368 if ISA_ARCOMPACT
369 
370 config ARC_COMPACT_IRQ_LEVELS
371         bool "Setup Timer IRQ as high Priority"
372         default n
373         # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
374         depends on !SMP
375 
376 config ARC_FPU_SAVE_RESTORE
377         bool "Enable FPU state persistence across context switch"
378         default n
379         help
380           Double Precision Floating Point unit had dedictaed regs which
381           need to be saved/restored across context-switch.
382           Note that ARC FPU is overly simplistic, unlike say x86, which has
383           hardware pieces to allow software to conditionally save/restore,
384           based on actual usage of FPU by a task. Thus our implemn does
385           this for all tasks in system.
386 
387 endif   #ISA_ARCOMPACT
388 
389 config ARC_CANT_LLSC
390         def_bool n
391 
392 config ARC_HAS_LLSC
393         bool "Insn: LLOCK/SCOND (efficient atomic ops)"
394         default y
395         depends on !ARC_CANT_LLSC
396 
397 config ARC_HAS_SWAPE
398         bool "Insn: SWAPE (endian-swap)"
399         default y
400 
401 if ISA_ARCV2
402 
403 config ARC_HAS_LL64
404         bool "Insn: 64bit LDD/STD"
405         help
406           Enable gcc to generate 64-bit load/store instructions
407           ISA mandates even/odd registers to allow encoding of two
408           dest operands with 2 possible source operands.
409         default y
410 
411 config ARC_HAS_DIV_REM
412         bool "Insn: div, divu, rem, remu"
413         default y
414 
415 config ARC_NUMBER_OF_INTERRUPTS
416         int "Number of interrupts"
417         range 8 240
418         default 32
419         help
420           This defines the number of interrupts on the ARCv2HS core.
421           It affects the size of vector table.
422           The initial 8 IRQs are fixed (Timer, ICI etc) and although configurable
423           in hardware, it keep things simple for Linux to assume they are always
424           present.
425 
426 endif   # ISA_ARCV2
427 
428 endmenu   # "ARC CPU Configuration"
429 
430 config LINUX_LINK_BASE
431         hex "Linux Link Address"
432         default "0x80000000"
433         help
434           ARC700 divides the 32 bit phy address space into two equal halves
435           -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
436           -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
437           Typically Linux kernel is linked at the start of untransalted addr,
438           hence the default value of 0x8zs.
439           However some customers have peripherals mapped at this addr, so
440           Linux needs to be scooted a bit.
441           If you don't know what the above means, leave this setting alone.
442           This needs to match memory start address specified in Device Tree
443 
444 config HIGHMEM
445         bool "High Memory Support"
446         select ARCH_DISCONTIGMEM_ENABLE
447         help
448           With ARC 2G:2G address split, only upper 2G is directly addressable by
449           kernel. Enable this to potentially allow access to rest of 2G and PAE
450           in future
451 
452 config ARC_HAS_PAE40
453         bool "Support for the 40-bit Physical Address Extension"
454         default n
455         depends on ISA_ARCV2
456         help
457           Enable access to physical memory beyond 4G, only supported on
458           ARC cores with 40 bit Physical Addressing support
459 
460 config ARCH_PHYS_ADDR_T_64BIT
461         def_bool ARC_HAS_PAE40
462 
463 config ARCH_DMA_ADDR_T_64BIT
464         bool
465 
466 config ARC_PLAT_NEEDS_PHYS_TO_DMA
467         bool
468 
469 config ARC_KVADDR_SIZE
470         int "Kernel Virtaul Address Space size (MB)"
471         range 0 512
472         default "256"
473         help
474           The kernel address space is carved out of 256MB of translated address
475           space for catering to vmalloc, modules, pkmap, fixmap. This however may
476           not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
477           this to be stretched to 512 MB (by extending into the reserved
478           kernel-user gutter)
479 
480 config ARC_CURR_IN_REG
481         bool "Dedicate Register r25 for current_task pointer"
482         default y
483         help
484           This reserved Register R25 to point to Current Task in
485           kernel mode. This saves memory access for each such access
486 
487 
488 config ARC_EMUL_UNALIGNED
489         bool "Emulate unaligned memory access (userspace only)"
490         default N
491         select SYSCTL_ARCH_UNALIGN_NO_WARN
492         select SYSCTL_ARCH_UNALIGN_ALLOW
493         depends on ISA_ARCOMPACT
494         help
495           This enables misaligned 16 & 32 bit memory access from user space.
496           Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
497           potential bugs in code
498 
499 config HZ
500         int "Timer Frequency"
501         default 100
502 
503 config ARC_METAWARE_HLINK
504         bool "Support for Metaware debugger assisted Host access"
505         default n
506         help
507           This options allows a Linux userland apps to directly access
508           host file system (open/creat/read/write etc) with help from
509           Metaware Debugger. This can come in handy for Linux-host communication
510           when there is no real usable peripheral such as EMAC.
511 
512 menuconfig ARC_DBG
513         bool "ARC debugging"
514         default y
515 
516 if ARC_DBG
517 
518 config ARC_DW2_UNWIND
519         bool "Enable DWARF specific kernel stack unwind"
520         default y
521         select KALLSYMS
522         help
523           Compiles the kernel with DWARF unwind information and can be used
524           to get stack backtraces.
525 
526           If you say Y here the resulting kernel image will be slightly larger
527           but not slower, and it will give very useful debugging information.
528           If you don't debug the kernel, you can say N, but we may not be able
529           to solve problems without frame unwind information
530 
531 config ARC_DBG_TLB_PARANOIA
532         bool "Paranoia Checks in Low Level TLB Handlers"
533         default n
534 
535 endif
536 
537 config ARC_UBOOT_SUPPORT
538         bool "Support uboot arg Handling"
539         default n
540         help
541           ARC Linux by default checks for uboot provided args as pointers to
542           external cmdline or DTB. This however breaks in absence of uboot,
543           when booting from Metaware debugger directly, as the registers are
544           not zeroed out on reset by mdb and/or ARCv2 based cores. The bogus
545           registers look like uboot args to kernel which then chokes.
546           So only enable the uboot arg checking/processing if users are sure
547           of uboot being in play.
548 
549 config ARC_BUILTIN_DTB_NAME
550         string "Built in DTB"
551         help
552           Set the name of the DTB to embed in the vmlinux binary
553           Leaving it blank selects the minimal "skeleton" dtb
554 
555 source "kernel/Kconfig.preempt"
556 
557 menu "Executable file formats"
558 source "fs/Kconfig.binfmt"
559 endmenu
560 
561 endmenu  # "ARC Architecture Configuration"
562 
563 source "mm/Kconfig"
564 
565 config FORCE_MAX_ZONEORDER
566         int "Maximum zone order"
567         default "12" if ARC_HUGEPAGE_16M
568         default "11"
569 
570 source "net/Kconfig"
571 source "drivers/Kconfig"
572 
573 menu "Bus Support"
574 
575 config PCI
576         bool "PCI support" if MIGHT_HAVE_PCI
577         help
578           PCI is the name of a bus system, i.e., the way the CPU talks to
579           the other stuff inside your box.  Find out if your board/platform
580           has PCI.
581 
582           Note: PCIe support for Synopsys Device will be available only
583           when HAPS DX is configured with PCIe RC bitmap. If you have PCI,
584           say Y, otherwise N.
585 
586 config PCI_SYSCALL
587         def_bool PCI
588 
589 source "drivers/pci/Kconfig"
590 
591 endmenu
592 
593 source "fs/Kconfig"
594 source "arch/arc/Kconfig.debug"
595 source "security/Kconfig"
596 source "crypto/Kconfig"
597 source "lib/Kconfig"
598 source "kernel/power/Kconfig"

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